Abstract: The present invention is directed to a method of attaching a leadframe to a singulated good die using a wet film adhesive applied in a predetermined pattern on the active surface of the good die, the lead finger of a leadframe, or both. By applying the adhesive only to identified good dice, time and material are saved over a process that applies adhesive to the entire wafer. By attaching the leadframe to the good die with a wet film, it is possible to remove the leadframe from the good die for rework if the good die subsequently tests unacceptable.

Abstract: A lead frame for manufacturing semiconductor device packages has inner leads, tie bars and a die pad that are formed with irregular dimples on their respective upper and lower surfaces. This improves the bonding strength between the lead frame and the molding compound as well as between the die pad and a semiconductor device. The dimples are formed during the manufacture of the lead frame which allows the lead frame to be economically and easily manufactured.

Abstract: A structure and methods for reinforcing a semiconductor device to prevent cracking is provided. The device may take the form of a semiconductor chip or a semiconductor chip package. When a semiconductor chip is provided, an adhesion layer is applied over its top surface, followed by the application of a reinforcing layer over the adhesion layer. When a semiconductor chip package is provided, the package first undergoes a cleaning process, followed by the application of an adhesion layer over its top surface and, lastly, the application of a reinforcing layer over the adhesion layer.

Abstract: An object of the present invention is to provide a method of fabricating a semiconductor device having a relatively small package structure and hence a relatively small mounting area. An insulating board with a plurality of device carrier areas thereon is prepared, and semiconductor chips are mounted on the respective device carrier areas and then covered with a common resin layer. The resin layer and said insulating board are separated along dicing lines into segments including the device carrier areas thereby to produce individual semiconductor devices. External electrodes connected to electrodes of the semiconductor chips are mounted on the back of the insulating board. The external electrodes are positioned symmetrically with respect to central lines of the packaged semiconductor device for preventing various problems which would otherwise be caused when such a small package is mounted.

Abstract: A stacked semiconductor package with ultrahigh integration and a fabrication method thereof according to the present invention are provided to meet the requirements of a system device of being miniaturized and light-weighted and having high efficiency. Also, there is provide a jig for package aligning to fabricate the stacked semiconductor package. The semiconductor package according to the present invention is fabricated by mounting a second-type package including a molding portion and leads exposed at a lower surface of the molding portion of the second-type package on a first-type package including a molding portion and leads, each of being formed in a ‘J’ shape, which are respectively extended out of both sides of the molding portion. Here, uppermost surfaces of the leads of the first-type package are welded by solder to bottom surfaces of the leads of the second-type package.

Abstract: A method of forming a semiconductor package that includes at least one structure having a central hole formed at a center portion of the structure, a plurality of outer holes around the center hole, and a plurality of conductor pieces buried in the outer holes; at least one TAB having lead lines extending from sides of the TAB, the TAB having a configuration substantially corresponding to the central hole of the structure and formed over the central hole of the structure; and a molding material covering at least a portion of the TAB.

Abstract: An integrated circuit package for improved warp resistance and heat dissipation is described. The LOC package includes: an integrated circuit die having an upper, active face, and a multi-layered, substantially planar lead frame mounted to the active face of the die, where the lead frame is preferably comprised of layers configured as Cu/INVAR/Cu or Cu/Alloy 42/Cu. The choice of the middle layer of the lead frame is selected to minimize the warping forces on the package such that the coefficient of thermal expansion of the composite lead frame approximates that of silicon. The copper layers of the lead frame provide improved heat dissipation.

Abstract: A memory device is described which is fabricated as an integrated circuit and uses distributed bond pads for electrical connection to an external conductive lead. The distributed bond pads are attached to a external lead, thereby eliminating bus lines on the integrated circuit memory. Distributed buffer circuits are described which can be included with the distributed bond pads to increase data communication time between the memory device and an external processor.

Abstract: This invention provides an extended lead package and method of forming the extended lead package for electronic circuit packages. A lead frame having extended leads is used. The extended leads extend under the bottom side of an integrated circuit element or chip. The bottom side of the chip is attached to the extended leads using bonding material which is a thermal conductor and an electrical insulator. Electrical connections between the chip input/output pads and the leads are provided by wire bonds using standard wire bonding techniques. The bonding material can be a tape having adhesive on one or both sides which attaches the chip to the lead frame using mechanical pressure, and/or other means such as curing or the addition of heat. Thermal energy is removed from the package by the thermal conduction path provided by the bonding material. The completed assembly can be encapsulated using standard methods.

Abstract: A semiconductor device is disclosed wherein a pair of radiating terminals and a plurality of lead terminals are formed from a single lead frame. A hole or holes in each radiating terminal are formed with an equal width and in an equal pitch to those of gaps between the lead terminals, and the opposite sides of each hole of the radiating terminal are connected to each other by a support element. The support elements of the radiating terminals and support elements which interconnect the lead terminals are formed with an equal length and in an equal pitch to allow the support elements to be cut away by a plurality of punches which are arranged in an equal pitch and have an equal width.

Abstract: A leadframe configuration for a semiconductor device has a die attach paddle with paddle support bars. In addition, clamp tabs extend outwardly from lesser supported locations of the paddle to underlie a conventional lead clamp. The clamp tabs are formed as an integral part of the paddle. Normal clamping during die attach and wire bonding operations prevents paddle movement and enhances integrity of the die bond and wire bonds.

Abstract: An integrated circuit package that has the ability for interdevice communication. The integrated circuit package has a first device mounted within the integrated circuit package. A second device is also mounted within the integrated circuit package. The second device is directly coupled to the first device through interdevice bonding for allowing the first device and the second device to communicate and control one another.

Abstract: Memory devices, such as random access memory, are affixed to an electrical contact frame and coupled to signals lines on the contact frame which is, in turn, mounted on a top surface of an integrated circuit. The signal leads are coupled to electrical contact pads disposed on the top surface of the integrated circuit. The contact pads and signal leads transfer control and power signals between the integrated circuit and the memory devices.

Abstract: To determine leadframe tip positions, a circular arc portion where leadframe tips are to be arranged is determined so as to be opposed to each of the four corners of a die pad by performing a search. Then, straight line portions are set so as to extend from the circular arc portion and to be opposed to the die pad sidelines. The shape of each leadframe tip on the circular arc portion is defined as a region that is sectioned by two concentric circles and two radial rays extending from the center of the concentric circles. The division between the circular arc portion and straight line portions and the setting of the center of the circular arc portion are performed automatically. The leadframe tip width and interval are determined independently of each other.

Abstract: A wire and method of making the wire for use in conjunction with the fabrication of semiconductor devices which consists essentially of forming one of an alloy or composite of from a finite amount approaching zero to about 50 percent by weight of at least one of carbon and the metals taken from the class consisting of platinum, silver and electrically conductive base metals and the rest gold. A wire is then formed from the alloy or composite. The noble metal alloyed with gold is preferably silver and the base metals that can be used are preferably copper or aluminum.

Abstract: To enable readily forming the etching stop layer of a lead frame with multilayer structure by plating without using a large-scale device, enhance adhesive strength between the etching stop layer and an adjacent metal layer and prevent peeling caused by deterioration caused by the invasion of a chemical between the etching stop layer and each adjacent metal layer from occurring, an etching stop layer is formed by nickel or a nickel alloy in a method of manufacturing a lead frame at least provided with an etching process for selectively etching metal layers using an etching stop layer as an etching stopper in a state in which a thick metal layer is formed on one side of the etching stop layer as an intermediate layer and a thin metal layer is formed on the other side and a process for etching the etching stop layer using the metal layers on both sides as a mask.

Abstract: Disclosed is a chip stack package having a remarkably short interconnection paths between the semiconductor chips and external device, and between the respective semiconductor chips. The chip stack package comprises: at least two semiconductor chips disposed in series vertically in the package, wherein bonding pads are disposed at both sides of the respective semiconductor chips and vertically open slots are formed in the bonding pads; lead frames inserted into the slots of the respective semiconductor chips so as to electrically connect the respective bonding pads; and an epoxy compound for molding the resultant structure entirely so as to expose an interconnection portion of the respective lead frames.

Abstract: Disclosed are a circuit member, which can cope with an ever-increasing demand for multiple terminals and is advantageous in productivity, cost, and quality, a semiconductor device using the circuit member, a process for producing the circuit member, and a process for producing a semiconductor device using the circuit member. The circuit member for a semiconductor device comprises: a conductive substrate; and a circuit section two-dimensionally formed using a conductive metal by plating on the conductive substrate, a part of the conductive metal constituting the circuit section being provided by plating on one side of the conductive substrate after subjecting the one side of the conductive substrate to surface treatment to create irregularities and to release treatment to impart releasability.

Abstract: An architecture for a dual-chip IC package and a method of manufacturing the same are provided. The dual-chip IC package allows two chips to be mounted on the same leadframe in the same package. The two chips can be either the same type of a semiconductor device or two different types of semiconductor devices with different functions such as a memory chip and a logic control chip. The architecture allows a simplified manufacturing process and an increased good yield rate for the two IC chips that are to be enclosed in the dual-chip IC package. Moreover, the dual-chip IC package can be manufactured with existing packaging equipment and processes, so that it can be realized without having to invest on and install additional ones.

Abstract: A plastic encapsulated semiconductor device comprises a die pad, die pad support pins suspending the die pad, a semiconductor chip mounted on the die pad, thin metal wires for connecting the electrode of the semiconductor chip to leads, and a sealing resin sealing the foregoing components, while the respective bottom faces of the leads forming terminal portions are exposed. An upset process is performed with respect to the die pad support pins of a lead frame to form stepped portions such that the die pad is positioned higher in level than the leads. Since the lower portion of the sealing resin also underlies the die pad, enhanced adhesion is achieved between the die pad and the sealing rein, resulting in higher reliability. With the die pad positioned higher in level than the leads, there is no possibility of interference between the leads and the semiconductor chip even when the size of the semiconductor chip is freely changed.

Abstract: A process for manufacturing a molded elecronic component such as a solid electrolyte capacitor comprising a capacitor element including a cathode layer, an anode lead, a pre-plated anode lead terminal connected to the anode lead, a pre-plated cathode lead terminal connected to the cathode layer, and an insulating member which encapsulates the capacitor element and leaves a portion of the anode and cathode lead terminals exposed. The encapsulated portions of the pre-plated anode and cathode lead terminals have a plating layer formed thereon containing organic substances in an amount of 0.03 wt. % or less.

Abstract: The present invention provides for a semiconductor device that facilitates optical recognition to prevent poor wire bonding from occurring. The semiconductor device associated with the present invention comprises a semiconductor chip (20) having a plurality of electrodes and a lead (16) comprising an inner lead portion (16a) connected to each of the electrodes with a wire (24) and an outer lead portion (16b) providing an external terminal. The inner lead portion (16a) is formed with a groove (18) providing a center index portion at a center along its width in a bonding area of the wire (24).

Abstract: A conductive plastic lead frame and method of manufacturing same suitable for use in IC packaging. In a preferred embodiment, the lead frame is constructed of a plastic or polymer based lead frame structure with an intrinsic conductive polymer coating. In a second embodiment the lead frame is a composite plastic or polymeric material intermixed with an intrinsic conductive polymer coating.

Abstract: A method of manufacturing a semiconductor device including two semiconductor chips having mutually different element forming face areas on respective surfaces of a die pad of a lead frame prepared by sealing the semiconductor chips with resin by setting the lead frame in a resin sealing use mold having an injection gate for injecting therethrough a sealing resin, includes the steps of: (a) mounting the semiconductor chips on respective surfaces of the die pad in such a manner that when setting the lead frame in the resin sealing use mold, a distance between a side face of the semiconductor chip having a larger element forming face area on the injection gate side and a side face of the semiconductor chip having a smaller element forming face area on the injection gate side becomes shorter than a distance when these semiconductor chips are mounted at a center on respective surfaces of the die pad; (b) setting the lead frame in the resin sealing use mold so that the above side faces of the semiconductor chips ar

Abstract: A method of bonding wire between at least one pair of bond locations in a semiconductor device and the bonder. A conveyor is provided having a conveying surface for conveying in a predetermined direction a partially fabricated semiconductor device having first and second bonding locations. A first capillary is provided for forming a stitch bond to the first bonding location, the first capillary being disposed at an angle of about 45 degrees with respect to the predetermined direction and a line normal thereto and substantially parallel to the plane of the conveying surface. A stitch bond is formed on the first bonding location with the first capillary. The first capillary is at an angle of substantially 45 degrees with respect to a line normal to the plane of the conveying surface.

Abstract: The present invention relates to a ball grid array (BGA) semiconductor package member and its manufacturing method employing a carrier frame and a substrate, and to a method of manufacturing a BGA semiconductor package using the BGA semiconductor package member. In manufacturing the conventional BGA semiconductor package, conventional package manufacturing equipment cannot be employed because a boat is used during processing which requires additional equipment, and thus increases the costs of production. However, a BGA semiconductor package manufacturing method employing a carrier frame and substrate according to the present invention is compatible with conventional semiconductor package manufacturing equipment.

Abstract: A leadframe and a method of manufacturing a semiconductor device make it possible to manufacture easily and efficiently such small-size semiconductor devices as have many leads but rarely suffer from short circuits between the leads when mounted on a circuit board. To achieve this, in a leadframe having a plurality of leads, an island for mounting a semiconductor chip, and a tie-bar for joining the leads together, the leads are given bends at their intermediate positions so that the pitch with which they are arranged is greater in a region farther from the island than in a region closer thereto, and the tie-bar is formed between those bends and the island. After the semiconductor chip mounted on the island, together with the portion surrounding it, is sealed in in a resin mold, those portions of the tie-bar which come between the leads are removed by cutting them apart parallel to the side edges of the leads.

Abstract: A molded electronic circuit package is described to which stabilizing tape can be attached using automatic or semi-automatic means. The stabilizing tape stabilizes the assembly for further processing operations such as dicing or attachment to a higher level package. The assembly comprises a substrate to which devices are attached. Molded caps are formed over the devices. Molded tape supports are formed at the same time as the molded caps and are located adjacent to opposite sides of the molded cap. The molded tape supports have the same height as the molded cap. The stabilizing tape can then be attached to the tops of the molded tape supports and the molded caps using automatic or semi-automatic means.

Abstract: The lead frame includes outer leads plated with tin (Sn) alloy so as to withstand the high temperatures generated during a subsequent semiconductor packaging process. In addition to the outer leads, the lead frame includes a die pad and inner leads composed of a base metal, such as copper (Cu), a copper alloy, or a nickel alloy. The die pad and the inner leads are plated with silver for improved conductivity. In order to withstand relatively high temperatures as well as to resist corrosion and have good solder wettability, the outer leads are preferably plated with a tin antimony alloy, such as a tin-antimony alloy consisting of 90.+-.5 weight percent of tin and 10.+-.5 weight percent antimony. Alternatively, the outer leads can be plated with a tin-antimony-lead alloy, such as a tin-antimony-lead alloy consisting of 10.+-.5 weight percent of tin, 10.+-.5 weight percent of antimony and 80.+-.10 weight percent of lead. A method of plating a lead frame is also provided.

Abstract: There is provided a method for manufacturing a lead frame which can easily manufacture a high quality lead frame.A pattern layer is selectively formed on a copper plate and the surface of the substrate having formed this pattern layer is then plated with gold to form a gold layer using the pattern layer as the mask. Next, the gold layer is then plated with copper to form a copper layer, thereby forming a fine lead consisting of two layers of gold layer and copper layer. Thereafter, the pattern layer is selectively removed, an insulated resist film is formed and the copper plate is etched. In this case, the gold layer is used as the etching stop layer. Thereby, the lead frame having the fine lead of double-layer structure can be formed.

Abstract: An inventive electronic device, such as a multi-chip module (MCM), a Single In-line Memory Module (SIMM), or a Dual In-line Memory Module (DIMM), includes a base, such as a printed circuit board, having a surface on which flip-chip pads and wire-bondable pads are provided. The flip-chip pads define an area on the surface of the base at least partially bounded by the wire-bondable pads. A first integrated circuit (IC) die is flip-chip bonded to the flip-chip pads, and a second IC die is back-side attached to the first IC die and then wire-bonded to the wire-bondable pads. As a result, the flip-chip mounted first IC die is stacked with the second IC die in a simple, novel manner.

Abstract: Disclosed is a packaging method of semiconductor device comprising the following step, preparing a PCB or BGA substrate with array-typed dam formed thereupon; placing a plurality of semiconductor devices into the array-typed dam, and attaching each semiconductor devices onto the dam grid; wire-bonding the semiconductor devices; performing lid-covering or resin-sealing process. The present invention forms the dam structure necessary for the package by an off-line process, and then attaches the dam structure on the substrate. Therefore, the problems of damage of PCB or substrate and short circuit due to the high-temperature and high-pressure pressing process can be prevented, moreover, the yield and the reliability can be enhanced.

Abstract: An electronic package is made by electrically bonding groups of conductive leads to two circuitized members after aligning the leads with electrical conductors on the circuitized members. Retention members may be used to hold the leads in alignment relative to each other prior to bonding and then are removed. Removal may include tearing away the retention member in propinquity to notches in the leads.

Abstract: A process for making a semiconductor device and the resulting device having standardized die-to-substrate bonding locations are herein disclosed. The semiconductor die provides a standardized ball grid or other array of a particular size, pitch and pattern such that as the size, configuration or bond pad arrangement of the die changes, a standard substrate, (the term including leadframes) having a similarly standardized array of terminals or trace ends can be employed to form a semiconductor device. It is also contemplated that dice having markedly different circuitry but a common array pattern may be employed with the same substrate or other carrier.

Abstract: A semiconductor package for a bipolar transistor comprises a lead frame including a plurality of inner leads arranged in a resin mold package. The inner leads include a collector lead mounting thereon a transistor element and occupying substantially the upper half area of the package, a base lead located at a central part of the lower half area, and an emitter lead extending between the spaces between the collector lead and base lead for improvement of transistor characteristics in a high frequency range. The gap (0.2 mm) between the leads is smaller than the thickness (0.26 mm) of the lead frame for reduction of package size. After punching press of the metallic plate, the metallic pattern plate is subjected to press-bending and/or non-press bending technique for reducing the gap between the lead portions of the lead frame.

Abstract: A lead frame comprises an island supported by island supports at its four corners and leads extending from its frame section to the island. The leads are composed of inner leads and outer leads which are connected to each other with dam bars. Plating layers are formed on the surfaces of the tip sections of the inner leads, and lead-fixing tape is bonded to the distal portions of the inner leads with an adhesive which acquires elastic properties when set. The lead-fixing tape is bonded with its inner side located 0.1 mm-2 mm inward from the tips of the inner leads.

Abstract: A method for fabricating a semiconductor package having a semiconductor chip and leads attached to the chip includes the steps of placing a tape over the leads attached to the semiconductor chip, forming a mold to encapsulate the semiconductor chip and the leads while exposing a portion of the leads contacting the tape, and removing the tape over the leads after the mold forming step.

Abstract: In a bonding apparatus such as a wire bonding apparatus, die bonding apparatus and the like in which lead frames are supplied from a lead frame magazine to a bonding section via a frame conveying path, when the absence of a lead frame in the frame storing section of a lead frame magazine is detected by a sensor in spite of the fact that a frame pusher for pushing out the lead frame from the magazine has operated, a judgement is made that no more lead frames are contained in the frame magazine, so that a lowermost frame storing section of the next magazine is moved to the level of the frame conveying path.

Abstract: In a lead frame carrying method and apparatus, first and second press units are provided on sides of a pair of carrier rails. When carrying a lead frame along the carrier rails, a side edge portion of the lead frame is clamped by being pressed from a surface and a back face of the lead frame almost perpendicularly thereto by the first and second press units. In the lead frame, the clamped side edge portion is floated by a predetermined height above one of the carrier rails during carrying. Accordingly, the lead frame can surely be clamped and carried. In addition, when carrying the lead frame along the carrier rails, the lead frame is damaged with difficulty by the carrier rails.

Abstract: A method and apparatus for cutting and applying adhesive tape to a leadframe for a lead-on-chip (LOC) semiconductor package are provided. The method includes indexing double sided adhesive tape into a guide opening, and then moving a tape cutter through the guide opening to cut the tape into a decal having finished dimension equal to the width of the tape. The finished dimension can be either the width or length of the decal. In either case the decal is formed with only two cut edges and no wasted tape. The tape cutter in addition to cutting the tape also presses the cut decal against the leadframe. The apparatus includes a support frame; a pair of tape feed rollers for indexing the tape; a tape guide for guiding and positioning the tape for cutting; and a tape cutter assembly for cutting and pressing the cut decal against the lead frame. The tape cutter assembly includes the guide opening and a tape cutter adapted to move through the guide opening.

Abstract: Provided with a method of manufacturing a ball grid array semiconductor package using a flexible circuit board strip, which is directed to prevent minute conductive traces in the outer part of a circuit pattern formed in the flexible circuit board and thus minimize the short-circuits by forming notches on the flexible circuit board in the vicinity of the lower side ends of a resin encapsulant section by use of a punch, and pressing down the resin encapsulant section with a singulation tool to remove the carrier frame and separate the ball grid array semiconductor packages in the piece.

Abstract: The present invention is directed to a method of attaching a leadframe to a singulated good die using a wet film adhesive applied in a predetermined pattern on the active surface of the good die, the lead finger of a leadframe, or both. By applying the adhesive only to identified good dice, time and material are saved over a process that applies adhesive to the entire wafer. By attaching the leadframe to the good die with a wet film, it is possible to remove the leadframe from the good die for rework if the good die subsequently tests unacceptable.

Abstract: An integrated circuit package includes an integrated circuit chip having first and second opposing faces and a plurality of pads on the first face of the integrated circuit chip. A plurality of external pins is also included along with a plurality of wires, a respective one of which electrically connects a respective external pin to a respective pad. A conductive lead frame is located adjacent and electrically contacting the second face of the integrated circuit chip. A first wire electrically connects a select one of the pads to the conductive lead frame. A second wire electrically connects a selected one of the pins to the conductive lead frame. Accordingly, power can be distributed to an integrated circuit package with reduced variation across the chip.

Abstract: A method for applying a viscous material to a lead frame element. A method of the invention includes positioning the lead frame facing downward and bringing the lead fingers into contact with a pool of adhesive material. The contact of the lead fingers to the adhesive material results in a portion of the lead fingers receiving a portion of the adhesive material from the pool of adhesive material. The gravitational forces on the adhesive material on the downward facing lead frame maintain the shape and boundary definition of the adhesive material.

Abstract: A method for planarizing the surface of a semiconductor device which employs spin on glass (SOG) and an etching operation to remove high portions of the SOG prior to a chemical metal polish (CMP) operation. The SOG is baked and cured before etching. Additional layers of SOG and etching operations may be employed as necessary. A thick encapsulating oxide layer is deposited over the SOG layer. For surface irregularities caused by metal lines, an insulating layer may be deposited over the surface before the SOG. Where an additional metal line is to be deposited on the surface, an additional insulating layer is deposited after the CMP operation. In the case of metal lines made of aluminum, provision is also made for preventing Hillock formations on the metal lines.

Abstract: A method for producing a lead frame having outer leads and inner leads, for use in constructing a resin-sealed semiconductor package comprises etching processes for etching a blank. A first resist pattern having a first opening and a second resist pattern having second openings are formed on the first and the second major surfaces of a blank. The first and the second major surfaces of the blank are etched through the first and the second resist pattern by a first etching process using a first etchant to form a first recess corresponding to the first opening and second recesses corresponding to the second recesses in the first and the second major surfaces, respectively. The first recess is filled up with an etch-resistant layer. The second major surface is etched through the second resist pattern by a second etching process using a second etchant so that portions of the blank corresponding to the second openings of the second resist pattern are etched through to form the tips of the inner leads.

Abstract: A method and apparatus for connecting a lead of a lead frame to a contact pad of a semiconductor chip using a laser or other energy beam is herein disclosed. The lead may be wire bonded to the contact pad by heating the ends of a wire until the wire fuses to the contact pad and lead or an energy-fusible, electrically-conductive material may be used to bond the ends of the wire to the contact pad and lead. In addition, this invention has utility for both conventional lead frame/semiconductor chip configurations and lead-over-chip configurations. In addition, with a lead-over-chip configuration, the lead may be directly bonded to the contact pad with a conductive material disposed between the lead and the contact pad.

Abstract: In a bonding apparatus such as a wire bonding apparatus, die bonding apparatus and the like in which lead frames are supplied from a lead frame magazine to a bonding section via a frame conveying path, when the absence of a lead frame in the frame storing section of a lead frame magazine is detected by a sensor in spite of the fact that a frame pusher for pushing out the lead frame from the magazine has operated, a judgement is made that no more lead frames are contained in the frame magazine, so that a lowermost frame storing section of the next magazine is moved to the level of the frame conveying path.

Abstract: A semiconductor device includes a tape carrier, a semiconductor chip, a metal heat spreader, a support ring, and a projection, recess, and spot welding portion. The tape carrier includes a TAB tape. The semiconductor chip is mounted on the tape carrier. The metal heat spreader is fixed to a surface of the semiconductor chip opposite to the tape carrier to dissipate heat generated in the semiconductor chip. The heat spreader has a shape larger than that of the semiconductor chip. The support ring is arranged between the heat spreader and tape carrier and is adhered to the tape carrier. The support ring serves to ensure a predetermined gap between the heat spreader and the tape carrier and to prevent warp of the tape carrier. The projection, recess, and spot welding portion bond the heat spreader and reinforcing member to each other by employing one of mechanical engagement and fusion welding. A method of manufacturing a semiconductor device is also disclosed.

Abstract: A packaged semiconductor device, such as a lead frame device, includes a circuit supported within an enclosure. The circuit is coupled to a plurality of conductive leads within the enclosure. The leads extend from the enclosure for electrically coupling the circuit to external circuitry. At least one of the leads is shielded to reduce inductive coupling and crosstalk between the leads during high frequency switching. The shielded lead has a conductive base, a non-conductive layer disposed on the base, and a conductive layer disposed on the non-conductive layer. The non-conductive and conductive layers may be formed prior to electrically coupling the lead to the circuit, or following assembly of the lead frame package. The shielding may extend into the package enclosure, or may terminate external to the enclosure.