Abstract: The invention relates to a method of manufacturing an assembly (100) of conductors (1), wherein a void (11) is provided in an electroconductive plate (10), within which void an island (12) is formed which serves as a carrier for a semiconductor element (13) and which is connected to the assembly (100) by a part (14) of the plate (10). Within the void (11), a number of strip-shaped conductors (1) are formed which surround the island (12), and the void (11) is formed so that one (1n) of the strip-shaped conductors (1) is connected to the island (12) by means of a further part (15) of the plate (10). Such a method has the drawback that it is not capable of providing an assembly (100) which can suitably be used for any semiconductor element (13). In particular, said method is expensive for ICs (13) which must demonstrate an electrical connection to the island (12) and which must be supplied in relatively small numbers.

Abstract: Two semiconductor chips sealed with a mold resin are stacked on each other so that their backs are opposite to each other. The two semiconductor chips are supported by suspension leads fixedly secured to a circuit forming surface (lower surface) of the lower chip. A pair of bus bar leads is placed in the vicinity of the sides of these chips, and a plurality of leads are placed thereoutside. Wires are bonded between one surfaces of both the bus bar leads and the leads and one of the two semiconductor chips. Further, wires are bonded between the other surfaces of both the bus bar leads and the leads and the other of the semiconductor chips. Thus, a semiconductor device wherein the two semiconductor chips are laminated and sealed with a resin, is reduced in manufacturing cost, and the thinning of the present semiconductor device is pushed forward.

Abstract: A method is provided for forming a thin, inexpensive, high-performance semiconductor device provided with busbar leads, power leads and signal leads. A portion of the power lead connected to the busbar lead is depressed toward a major surface of a semiconductor chip to form a depressed portion, and the depressed portion is bonded to the major surface of the semiconductor chip by an adhesive layer. The signal lead and the busbar lead are spaced apart from the major surface of the semiconductor chip.

Abstract: A lead frame used for a resin-sealed semiconductor device includes a die-mount portion on which a semiconductor chip rests; and a plurality of leads arranged along a common portion of the lead frame. The plurality of leads include at least one adjusting lead, and the adjusting lead has a length that is less than the others of the plurality of leads such that a tip of the adjusting lead is sufficiently proximate to an outer peripheral surface of a resin-seal body to prevent resin flash during a formation of the semiconductor device and to allow the adjusting lead to be removed after the resin-seal body is formed over a portion of the lead frame.

Abstract: A conductive plastic lead frame and method of manufacturing same suitable for use in IC packaging. In a preferred embodiment, the lead frame is constructed of a plastic or polymer based lead frame structure with an intrinsic conductive polymer coating. In a second embodiment the lead frame is a composite plastic or polymeric material intermixed with an intrinsic conductive polymer coating.

Abstract: Microelectronic assemblies are encapsulated using disposable frames. The microelectronic assemblies are disposed within an aperture defined by a frame. The aperture is covered by top and bottom sealing layers so that the frame and sealing layers define an enclosed space encompassing the assemblies. The encapsulant is injected into this closed space. The frame is then separated from the encapsulation fixture and held in a curing oven. After cure, the frame is cut apart and the individual assemblies are severed from one another. Because the frame need not be held in the encapsulation fixture during curing, the process achieves a high throughput.

Abstract: A method of making a microelectronic assembly comprises providing a first side assembly juxtaposed with a second side assembly and a first resilient element disposed therebetween. Leads extend between the first side assembly and the second side assembly. A compressive force is applied to the juxtaposed assemblies so as to compress the first resilient element and the compressive force is at least partially released so as to allow the first resilient element to expand, thereby moving one or both of the first side assembly and the second side assembly to deform the leads.

Abstract: A semiconductor package and method for fabricating the package are provided. The package includes a semiconductor die and a heat sink in thermal communication with the die. The heat sink includes one or more pad structures adapted to form bonded connections, and thermal paths to contacts on a substrate. The method includes forming multiple heat sinks on a frame similar to a lead frame, and etching or stamping the pad structures on the heat sink. The frame can then be attached to a leadframe containing encapsulated dice, and the assembly singulated to form separate packages. The packages can be used to form electronic assemblies such as circuit board assemblies and multi chip modules.

Abstract: A leadframe configuration for a semiconductor device has a die attach paddle with paddle support bars. In addition, clamp tabs extend outwardly from lesser supported locations of the paddle to underlie a conventional lead clamp. The clamp tabs are formed as an integral part of the paddle. Normal clamping during die attach and wire bonding operations prevents paddle movement and enhances integrity of the die bond and wire bonds.

Abstract: A semiconductor device includes a two-part, coplanar, interdigitated decoupling capacitor formed as a part of the conductive lead frame. For down-bonded dice, the die attach paddle is formed as the interdigitated member. Alternatively, an interdigitated capacitor may be placed as a LOC type lead frame member between electrical bond pads on the die. The capacitor sections comprise Vcc and Vss bus bars.

Abstract: In a lead frame with a reinforcing ring surrounding a semiconductor element which are electrically connected to leads through electrodes is integrally formed through suspending portions, reinforcing portions for reinforcing the suspending portions are provided on the suspending portions. Upon application of a lead frame forming technique in which a laminate plate of three or more layers is used as a base, and inner leads are formed at one side while outer leads are formed by the surface layer at the other side, the lead frame is formed by forming a ring in place of outer leads, for example. A semiconductor package is formed by mounting the lead frame on a semiconductor chip.

Abstract: Providing a method of producing a semiconductor device wherein semiconductor element are sealed with a resin by using the same lead and other means regardless of the specifications of the semiconductor elements, and a semiconductor device which can be reduced in size and weight and has good heat dissipation performance and high-frequency performance.

Abstract: A metal frame patterned by die stamping has the outermost end portion of each patterned pin extending freely, without constraints, from a line of metal bridge connections (dam bar). The end face of each pin is also covered, as well as other surfaces of the frame, by a coating layer or multilayer of metals different from the metal of the die stamped frame. The coating layer or multilayer contains at least on its outer surface, a noble metal such as palladium or gold. The tip of the pins are not subject to cutting and/or trimming after plating the die stamped frame. The pins are not even cut or trimmed during separation of the patterned frame from the surrounding metal at the end of the encapsulation process, when the pins are then eventually bent into shape.

Abstract: The present invention is directed to a method of attaching a leadframe to a singulated good die using a wet film adhesive applied in a predetermined pattern on the active surface of the good die, the lead finger of a leadframe, or both. By applying the adhesive only to identified good dice, time and material are saved over a process that applies adhesive to the entire wafer. By attaching the leadframe to the good die with a wet film, it is possible to remove the leadframe from the good die for rework if the good die subsequently tests unacceptable.

Abstract: A method of manufacturing a leadless semiconductor chip package comprises the steps of: attaching a semiconductor die onto a die pad of a lead frame, wherein the lead frame comprises a plurality of leads arranged about the periphery of the die pad and each lead has a notch formed at the to-be-punched position thereof; wire bonding the inner ends of the leads to bonding pads on the semiconductor die; sucking a film against a lower part of a molding die; closing and clamping the molding die in a manner that the semiconductor die is positioned in a cavity of the molding die and the lead frame is disposed against the film; transferring a hardenable molding compound into the cavity; hardening the molding compound; opening the molding die to take out the molded product; and punching the molded product along the notches of the leads thereby making the singulation process more convenient and correct.

Abstract: A semiconductor device and a manufacturing method thereof are provided, wherein both bumps of a semiconductor chip and leads on a tape substrate can be accurately connected at the time of performing thermocompression bonding of the two using a heating tool. The film tape carrier and semiconductor chip expand due to heat applied from the heating tool of the gang bonding apparatus, so setting the pitch of the bumps and the pitch of the inner leads, taking into consideration beforehand the difference in linear expansion coefficient of the two at the time of gang bonding, solves the problem.

Abstract: An object of the present invention is to provide a method of fabricating a semiconductor device having a relatively small package structure and hence a relatively small mounting area. An insulating board with a plurality of device carrier areas thereon is prepared, and semiconductor chips are mounted on the respective device carrier areas and then covered with a common resin layer. The resin layer and said insulating board are separated along dicing lines into segments including the device carrier areas thereby to produce individual semiconductor devices. External electrodes connected to electrodes of the semiconductor chips are mounted on the back of the insulating board. The external electrodes are positioned symmetrically with respect to central lines of the packaged semiconductor device for preventing various problems which would otherwise be caused when such a small package is mounted.

Abstract: Recently, there have been increasing demands for the reduction in size and weight of mobile computing/communication terminals as well as the elongation of the use time of the internal batteries. This invention alters the assembling structure of power MOSFET for reducing the on-state resistance and improving the production efficiency. This semiconductor device includes a lower frame having a header 2 for fixing a semiconductor chip and corresponding external leads 3d, 3g, a semiconductor chip fixed on the header, an upper frame 7 having a connection electrode 6 fixed on a current passage electrode 5 formed on the top face of the semiconductor chip 1 and the corresponding leads 3s, and a resin mold 8. This two-frame configuration provides extremely low on-state resistance and good production efficiency.

Abstract: A semiconductor device having power supply leads and signal leads on the main surface of a semiconductor chip. Since floating capacitance applied to the power supply leads can be made large and floating capacitance applied to the signal leads can be made small by making the interval between the signal leads and the semiconductor chip larger than the interval between the power supply leads and the semiconductor chip, the prevention of fluctuations in power source potential and the acceleration of the signal propagation speed can be carried out at the same time. As a result, the electric characteristics of the semiconductor device can be improved.

Abstract: A film carrier tape and laminated multi-chip semiconductor device incorporating the same and method thereof wherein a plurality of chip semiconductor devices are laminated onto a substrate. Each chip semiconductor device includes a film carrier tape having leads, a semiconductor chip electrically connected to the leads, a heat sink mounted to a surface of the chip, and a connector for mounting the heat sink, the connector being electrically connected to the leads of the film carrier tape. The film carrier tape includes a carrier member having a metallic layer superposed thereon which is etched so as to form the leads and the heat sink.

Abstract: A conductive plastic lead frame and method of manufacturing same suitable for use in IC packaging. In a preferred embodiment, the lead frame is constructed of a plastic or polymer based lead frame structure with an intrinsic conductive polymer coating. In a second embodiment the lead frame is a composite plastic or polymeric material intermixed with an intrinsic conductive polymer coating.

Abstract: A method of forming a semiconductor memory device comprises the steps of providing a semiconductor die, forming a temporary protective material over a surface of the die, and attaching the die to a first lead frame portion. Next, a protective material is contacted with a second lead frame portion and, subsequently, the second lead frame portion is electrically connected with the second lead frame portion with bond pads on the first surface of the die with bond wires. Subsequent to electrically connecting the die and the second lead frame portion the protective material is removed.

Abstract: A lead frame is described which has at least one integrated electronic circuit. The integrated electronic circuit is situated in a region of a main area of the lead frame. The lead frame has at least one signal line, at least one electrically insulating plate, and an electrically conductive, grounded plate are situated. The electrically insulating plate, and the electrically conductive, grounded plate are situated, at least in sections, between the integrated electronic circuit and the signal line. A method for producing the lead frame is also described.

Abstract: A semiconductor leadframe assembly (20A) and a method for manufacturing a semiconductor component (50) using the semiconductor leadframe assembly (20A). The semiconductor leadframe assembly (20A) includes a leadframe (10A) having flag portions (18A), lead portions (19A), and vias (14A). The vias (14A) serve as dielectric receiving areas. The assembly (20A) further includes semiconductor chips (21A) mounted on the flag portions (18A) and a dielectric material (33A) that covers the semiconductor chips (21A) and fills the vias (14A). The surface mount semiconductor component (50) is singulated from the semiconductor leadframe assembly (20A) to form electrical interconnects (18, 19) of the surface mount semiconductor component (50).

Abstract: A method for fabricating semiconductor components, such as BGA packages, chip scale packages, and multi chip modules, includes the steps of cutting decals from ribbons of adhesive tape, and then attaching a semiconductor die to a substrate using the decals. A system for performing the method includes a tape cutting apparatus configured to cut the decals from the tape without wasted tape, and then to apply the cut decals to the substrate. A first finished dimension (e.g., width) of the decals is determined by a width of the tape, and a second finished dimension (e.g., length) of the decals is determined by indexing the tape through a selected distance. The tape cutting apparatus includes cutters configured to move through guide openings to cut and apply the decals to the substrate. The guide openings align the tape to the cutters, and also align the cut decals to the substrate. The system also includes a substrate handling apparatus configured to index and position the substrate relative to the guide openings.

Abstract: Two phase bridge rectifier, plastic encapsulated devices having four external terminal leads are batch fabricated using a workpiece of three stacked together lead frames wherein, at each of a plurality of device sites on the workpiece, two, two-chip stacks of semiconductor diode chips are provided; each chip of each stack being sandwiched between respective pairs of bonding pads on either top and middle lead frames or middle and bottom lead frames. Each of the two bonding pads of the middle frame is connected to a respective integral terminal lead of the middle frame. An integral extension of a bonding pad of each of the top and bottom lead frames is bent out of the plane of its respective lead frame to include a flat terminal lead portion lying in the plane of the middle frame but not connected thereto. All four in-plane terminal leads include dam bars for use during device encapsulating; the dam bars from the top and bottom lead frames cooperating to form a single, in-plane dam bar.

Abstract: The invention provides means for effectively preventing a wire disconnection generated due to an increase of calorie applied to a semiconductor integrated circuit device. The semiconductor integrated circuit device is structured such that a metal layer containing a Pd layer is provided in a portion to which a connecting member having a conductivity is connected, and an alloy layer having a melting point higher than that of an Sn—Pb eutectic solder and containing no Pb as a main composing metal is provided outside a portion molded by a resin. Further, a metal layer in which a thickness in a portion to which the connecting member having the conductivity is adhered is equal to or more than 10 &mgr;m is provided in the connecting member.

Abstract: A variety of improved substrate structures and substrate fabrication techniques for use in integrated circuit packaging are described. In one aspect, a substrate strip fabrication technique that facilitates strip testing of the dice mounted thereon is described. The described technique works well even when landings on the substrate are electrolytically plated. In a preferred embodiment, the substrate is formed in a manner that facilitates the use of non-stick detection during wire bonding. In a distinct aspect of the invention the substrate strip has a plurality of distinct molding area tiles that each have a two dimensional array of substrate segments formed thereon. The substrate segments each have a die attach area, a plurality of landing one surface and a plurality of contact pads on the other. The contact pads are positioned substantially across from the landings and are electrically connected thereto by associated vias.

Abstract: A back-to-back semiconductor device module including two semiconductor devices, the backs of each being secured to one another. Each of the bond pads of both of the semiconductor devices are disposed adjacent a single, mutual edge of the back-to-back semiconductor device module. The back-to-back semiconductor device module may be secured to a carrier substrate in a substantially perpendicular orientation relative to the former. A process for securing the back-to-back semiconductor device module directly to the carrier substrate may employ a solder reflow technique. Alternatively, a module-securing device may be employed to secure the back-to-back semiconductor device module to the carrier substrate. An embodiment of a module-securing device comprises an alignment device having one or more receptacles formed therein and intermediate conductive elements that are disposed within the receptacles to establish an electrical connection between the semiconductor devices and the carrier substrate.

Abstract: A semiconductor device of this invention has an LOC (Lead On Chip) structure, and a protective film consisting of a thermoplastic (thermosetting) resin material such as a thermoplastic (thermosetting) polyimide resin or a thermoplastic (thermosetting) polyamide resin is formed on the surface of a semiconductor chip having a DRAM. The lower surface of a lead frame is positioned to the upper surface of the semiconductor chip, on which the protective film is formed, and the upper surface of the semiconductor chip is bonded and fixed to the lower surface of the distal end portion of an inner lead with only the protective film interposed therebetween such that bonding pads appear between opposing bus bars. According to this invention, the protective film serves not only as an &agr;-ray protective film but also as an insulating material and an adhesive material.

Abstract: A method and article for attaching an electronic component, such as a semiconductor die, to a substrate includes applying a relatively low-melting-temperature solder preform to the substrate; and applying a bead of a curable bonding material to the substrate around the periphery of the solder preform in an amount sufficient to substantially contain the solder material and bridge the gap between the die and the substrate upon a subsequent collapse of the solder preform along its thickness dimension. After placing the die atop the solder preform so as to at least partially overlie the bonding material, the method includes heating the solder preform and the bonding material so as to reflow the solder, whereupon the solder preform collapses to allow the bonding material to engage the underside of the die, and to subsequently cure the bonding material.

Abstract: This is a semiconductor device made by using a film carrier tape and method of making the same, wherein the package size is close to the chip size and connection portions for electrodes of a semiconductor chip are not exposed. Electroplating is performed in a state where connection leads 24, plating leads 26 and plating electrodes 28 are all conductive, the connection leads being are formed within a region to be filled with a molding material 36 and being connected to electrodes 42 of a semiconductor chip 40 and pad portions 22, the plating leads 26 being connected to the connection leads 24, and plating electrodes 28 being connected to the plating leads 26. The connection portions 29 are punched out into the region to be filled with the molding material, the connection leads 24 and the electrodes 42 are connected, and the molding material 36 is poured in. The end surfaces of the connection leads 24 that are exposed from the holes 32 are also covered by the molding material 36 so as not to be exposed.

Abstract: A semiconductor device includes a lead frame, a dielectric tape layer, a plurality of conductive contacts and a semiconductor die. The lead frame is provided with a plurality of leads. The dielectric tape layer has a first adhesive surface adhered onto the leads, and a second adhesive surface opposite to the first adhesive surface. The dielectric tape layer is formed with a plurality of holes at positions registered with the leads for access thereto. Each of the holes is confined by a wall that cooperates with a registered one of the leads to form a contact receiving space. The conductive contacts are placed in the contact receiving spaces, respectively. The die has a die mounting surface adhered onto the second adhesive surface of the dielectric tape layer. The die mounting surface is provided with a plurality of contact pads that are bonded to the conductive contacts to establish electrical connection with the leads of the lead frame. A method for fabricating the semiconductor device is also disclosed.

Abstract: One method for packaging at least one circuit chip includes: providing an interconnect layer including insulative material having a first side and a second side, initial metallization patterned on second side metallized portions of the second side and not on second side non-metallized portions of the second side, at least one substrate via extending from the first side to one of the second side metallized portions, and at least one chip via extending from the first side to one of the second side non-metallized portions; positioning the at least one circuit chip on the second side with at least one chip pad of the at least one circuit chip being aligned with the at least one chip via; and patterning connection metallization on selected portions of the first side of the interconnect layer and in the vias so as to extend to the at least one second side metallized portion and to the at least one chip pad.

Abstract: A method and apparatus for connecting a lead of a lead frame to a contact pad of a semiconductor chip using a laser or other energy beam is herein disclosed. The lead may be wire bonded to the contact pad by heating the ends of a wire until the wire fuses to the contact pad and lead or an energy-fusible, electrically-conductive material may be used to bond the ends of the wire to the contact pad and lead. In addition, this invention has utility for both conventional lead frame/semiconductor chip configurations and lead-over-chip configurations. In addition, with a lead-over-chip configuration, the lead may be directly bonded to the contact pad with a conductive material disposed between the lead and the contact pad.

Abstract: A semiconductor device comprising: a tape substrate which supports a semiconductor chip, said chip having surface electrodes, said tape substrate being provided with a plurality of leads corresponding to the surface electrodes of the semiconductor chip and bonded thereto, and with dummy leads formed in vacant regions in corner portions of the tape substrate where the leads are not formed; conductive members for bonding the surface electrodes of the semiconductor chip to the leads of the tape substrate; and a plurality of external terminals arranged on an outside periphery of the semiconductor chip and mounted on the tape substrate.

Abstract: A multi-chip semiconductor package using a lead-on-chip lead frame. The lead-on-chip package places two or more lead-on-chip dice into one package that are either attached to their own lead-on-chip lead frame or are mounted to the same lead-on-chip lead frame and subsequently wire bonded to provide electrical connection from the dice to the lead frame while in substantially the same arrangement without requiring the assembly of the multiple semiconductor dice and lead frame to be flipped for additional wire bonding attachment of the dice to the lead frame.

Abstract: A semiconductor package provided with a reinforcing plate on the side of the lead joined face of which a chip housing concave portion is formed, a semiconductor chip housed and fixed in the chip housing concave portion of this reinforcing plate, a plurality of leads joined and held on the lead joined face of the reinforcing plate, the inner lead section of which is joined to the semiconductor chip via a bump and in the outer lead section of which a protruded electrode is formed, a solder resist film formed on the lead except the bump formed area and the electrode formed area of this lead and a polyimide film formed on the side of the inner lead section of the lead on the solder resist film and the manufacturing method are disclosed and hereby, the quality of the semiconductor package with ultra-multipin structure is stabilized.

Abstract: The present invention includes a package for housing an integrated circuit device. The present invention also includes leadframes and methods for making such packages. The package includes an integrated circuit device on a metal die pad. A metal ring is between the die pad and leads and surrounds the die pad. The ring is connected to the die pad by a nonconductive tape. Encapsulant material covers the entire structure. The ring is connected to a lead identified for connection to an external power voltage supply. The ring in turn is connected to a power voltage input pad on the integrated circuit device. The die pad floats, or is connected to a lead that is connected to an external ground voltage. The package is made from a leadframe that has a die pad, a metal ring between the die pad and radiating leads, and a nonconductive tape that connects the ring to the die pad. In one embodiment, the leadframe and package also include a bypass or decoupling capacitor attached between the die pad and the ring.

Abstract: Resin sealed lead frames are processed by modular processing work stations related in number to a plurality of steps used in processing the lead or leads of the resin sealed lead frame. The work stations are separate modules which are detachably interconnected, whereby the number of modules can be exactly correlated to the number of steps actually required for processing the lead or leads of the resin sealed lead frame. As required, modules can be added or omitted. The resin sealed lead frame is sequentially advanced through the modules in steps corresponding to at least two pitches, whereby one pitch is defined as the on-center spacing between two neighboring products on the lead frame. Such feed advance permits performing at least two processing steps simultaneously. Thus, the method for processing the resin sealed lead frame and the apparatus therefore are adaptable to a change in the type of processing and to the production volume.

Abstract: A light-emitting diode device, such as a blue, green, blue-green light-emitting diode, with a one-wire-bonding characteristic and the method of manufacturing the same have been disclosed. The light-emitting diode device has a GaN-based semiconductor laminated structure formed on an insulating substrate. The GaN-based semiconductor laminated structure includes an n-type layer on its bottom side, a p-type layer on its top side, and an active layer, for generating light, sandwiched between the n-type and p-type layers. An annular isolation portion such as a trench or a high resistivity portion formed by ion implantation is formed in the GaN-based semiconductor laminated structure to separate the p-type layer into a central p-type layer and a peripheral p-type layer and to separate the active layer into a central active layer and a peripheral active layer. A p-type electrode is formed on the central p-type layer without electrically connecting to the peripheral p-type layer.

Abstract: A lead member includes a plurality of conductors arranged in parallel and an insulating film fixing the conductors at a predetermined pitch. Each conductor includes a first end portion, a second end portion, and a flat portion extending between the first and second end portions. The flat portion is located on a plane different from a plane on which the first end portion and the second end portion lie. The flat portion may be formed by bending the lead member along a bent line such that the bent line is kept straight. Preferably, each conductor includes a narrow portion and a wide portion, wherein a width of each conductor along the bent line is greater than half of the pitch between adjacent conductors.

Abstract: A wiring patterned film wherein a gold lead 18 which extends from a wiring pattern formed on the adhesive side of a resin film adhered to the side of a semiconductor element on which an electrode terminal is formed, and which bridges a window section opening on the resin film, is cut off at a prescribed location facing the window section and bent so that the lead tip is connected to the electrode terminal, wherein a notch section is formed at a prescribed location of the gold lead 18 bridging the window section to facilitate cutting of the gold lead 18, and at least the narrowest part of the notch section 42a is formed into an upward protruding convex curve at the surface opposite the back side facing the window section.

Abstract: Provided are a method for manufacturing a semiconductor device in which a sealing resin is prevented from being damaged and generation of a resin piece is suppressed, a press die for suppressing the generation of the resin piece, and a guide rail. A frame receiving die (11) includes a cavity (11d) having a rectangular contour shape seen on a plane which serves to house a sealing resin (3) therein, and a remaining gate housing section (11c) provided on any of four corners of the cavity (11d) corresponding to a remaining gate (3b) on a lower face of a corner (2a) of a lead frame (2). A lower gate punch (11a) is provided in a boundary portion between the cavity (11d) and the remaining gate housing section (11c). When the lead frame (2) is mounted on the frame receiving die (11), the sealing resin (3) is housed in the cavity (11d) and the remaining gate (3b) is housed in the remaining gate housing section (11c).

Abstract: This invention provides an extended lead package and method of forming the extended lead package for electronic circuit packages. A lead frame having extended leads is used. The extended leads extend under the bottom side of an integrated circuit element or chip. The bottom side of the chip is attached to the extended leads using bonding material which is a thermal conductor and an electrical insulator. Electrical connections between the chip input/output pads and the leads are provided by wire bonds using standard wire bonding techniques. The bonding material can be a tape having adhesive on one or both sides which attaches the chip to the lead frame using mechanical pressure, and/or other means such as curing or the addition of heat. Thermal energy is removed from the package by the thermal conduction path provided by the bonding material. The completed assembly can be encapsulated using standard methods.

Abstract: A multi-component electronic assembly (100) including a leadframe (101) having upper and lower surfaces and a plurality of conductive leads (203). Each lead (203) has first bonding surfaces (201) on the upper surface of each lead and second bonding surfaces (201) on the lower surface of each lead (203). Preferably, each lead has a plurality of third bonding surfaces (202) formed on at least some of the plurality of leads where the third bonding surfaces (202) are formed by conductive extensions of the leads (203) that extend towards the center of the assembly (100). A first passive component (102) is electrically and mechanically coupled to the first bonding surfaces. A second passive component (104) is electrically and mechanically coupled to the second bonding surfaces. Where third bonding surfaces (202) are used, a third component (103) is electrically and mechanically coupled to the third bonding surfaces (202).

Abstract: A device and method for increasing integrated circuit density comprising at least a pair of superimposed dice, wherein at least one of the superimposed dice has at least one bond pad variably positioned on an active surface of the die. A plurality of lead fingers from a leadframe extend between the dice. The leadframe comprises at least one lead with leads of non-uniform length and configuration to attach to the differently positioned bond pads of the multiple dice. An advantage of the present invention is that it allows dice with differing bond pad arrangements to be used in a superimposed configuration to increase circuit density, while eliminating the use of bond wires in such a configuration.

Abstract: A plurality of integrated circuit chip (IC chip) packages are fabricated simultaneously from a single insulating substrate having sections. In each section, an IC chip is attached. Bonding pads on the IC chip are electrically connected to first metallizations on a substrate first surface. The first metallizations, IC chip including bonding pads and first substrate surface are then encapsulated. Interconnection balls or pads are formed at substrate bonding locations on a substrate second surface, the interconnection pads or balls being electrically connected to corresponding first metallizations. The substrate and encapsulant are then cut along the periphery of each section to form the plurality of IC chip packages.

Abstract: An LOC die assembly includes a die dielectrically adhered to the underside of a lead frame. The active surface of the die underlying the attached lead frame is coated with a polymeric material such as polyimide. The underside of the lead frame overlying the die is coated with a layer of soft material, such as silver, which has a lower hardness than the coating on the active surface for absorbing point stresses. Penetration of stacked filler particles into the soft material reduces point stresses on the active die surface and disadhesion stresses on the lead frame components.

Abstract: A method and apparatus for connecting a lead of a lead frame to a contact pad of a semiconductor chip using a laser or other energy beam is herein disclosed. The lead may be wire bonded to the contact pad by heating the ends of a wire until the wire fuses to the contact pad and lead or an energy-fusible, electrically-conductive material may be used to bond the ends of the wire to the contact pad and lead. In addition, this invention has utility for both conventional lead frame/semiconductor chip configurations and lead-over-chip configurations. In addition, with a lead-over-chip configuration, the lead may be directly bonded to the contact pad with a conductive material disposed between the lead and the contact pad.