Abstract: A chip package includes: a substrate having a first and a second surfaces; a device region formed in or disposed on the substrate; a dielectric layer disposed on the first surface; at least one conducting pad disposed in the dielectric layer and electrically connected to the device region; a planar layer disposed on the dielectric layer, wherein a vertical distance between upper surfaces of the planar layer and the conducting pad is larger than about 2 ?m; a transparent substrate disposed on the first surface; a first spacer layer disposed between the transparent substrate and the planar layer; and a second spacer layer disposed between the transparent substrate and the substrate and extending into an opening of the dielectric layer to contact with the conducting pad, wherein there is substantially no gap between the second spacer layer and the conducting pad.

Abstract: There is provided a method for producing a semiconductor device, capable of suppressing generation of voids at an interface between a semiconductor element and an under-fill sheet to produce a semiconductor device with high reliability. The method includes providing a sealing sheet having a support and an under-fill material laminated on the support; thermally pressure-bonding a circuit surface of a semiconductor wafer, on which a connection member is formed, and the under-fill material of the sealing sheet under conditions of a reduced-pressure atmosphere of 10000 Pa or less, a bonding pressure of 0.2 MPa or more and a heat pressure-bonding temperature of 40° C. or higher; dicing the semiconductor wafer to form a semiconductor element with the under-fill material; and electrically connecting the semiconductor element and the adherend through the connection member while filling a space between the adherend and the semiconductor element using the under-fill material.

Abstract: An exemplary implementation of the present disclosure includes a stacked package having a top die from a top reconstituted wafer situated over a bottom die from a bottom reconstituted wafer. The top die and the bottom die are insulated from one another by an insulation arrangement. The top die and the bottom die are also interconnected through the insulation arrangement. The insulation arrangement can include a top molding compound that flanks the top die and a bottom molding compound that flanks the bottom die. The top die and the bottom die can be interconnected through at least the top molding compound. Furthermore, the top die and the bottom die can be interconnected through a conductive via that extends within the insulation arrangement.

Abstract: Provided is a method of manufacturing a semiconductor element having at a cut portion with excellent quality, which minimizes a region on a silicon substrate necessary for cutting, and which prevents cutting water used when cutting by dicing is carried out from entering the semiconductor element. The method of manufacturing a semiconductor element includes: arranging, on the silicon substrate, multiple semiconductor element portions so as to be adjacent to one another; bonding the silicon substrate and a glass substrate together using the resin; and cutting the silicon substrate and the glass substrate, respectively, in a region in which the resin is provided, the cutting the silicon substrate and the glass substrate including: half-cutting the silicon substrate by dicing; cutting the glass substrate by scribing; and dividing the silicon substrate, the glass substrate, and the resin.

Abstract: A method for manufacturing a semiconductor light emitting apparatus of side emission type includes disposing a light emitting device on a substrate having a predetermined electrode pattern. A side member is disposed on the substrate to be spaced apart from the light emitting device with a predetermined space. The light emitting device and the electrode pattern are electrically connected. A light reflecting member is disposed in the space between the side member and at least one side surface of the light emitting device so that the light reflecting member is in contact with the at least one side surface of the light emitting device. A light-transmitting sealing member is disposed to surround the light emitting device other than the at least one side surface that is in contact with the light reflecting member. A light-reflective ceiling member is disposed at least over the sealing member.

Abstract: Exemplary semiconductor device packaging structure and packaging method are provided. The packaging method uses an adhesive layer to bond multiple wafer pieces onto a first surface of a carrier substrate, each adjacent two of the wafer pieces having a gap formed therebetween for exposing a part of the adhesive layer. A packaging layer is filled in each of the gaps. At least one through silicon via is formed each of the wafer pieces to expose a bonding pad formed on an active surface of the wafer pieces. Redistribution circuit layers are formed on back surfaces of the respective wafer pieces and filled into the through silicon vias for electrical connection with the bonding pads. A sawing process is performed to saw starting from each of the packaging layers to a second surface of the carrier substrate, and thereby multiple semiconductor device packaging structures are obtained.

Abstract: A method of forming a semiconductor package includes providing a transfer film and placing electronic components on the transfer film with active sides of the electronic components facing the transfer film. The electronic components include a first assembled package and one or more of a second assembled package and a passive component. A molding operation is performed to encapsulate the electronic components and one side of the transfer film. The transfer film is then removed, which exposes the active sides of the electronic components. An electrical distribution layer is formed over the active sides of the electronic components and electrically connects the electronic components. Conductive bumps are then formed on the electrical distribution layer.

Abstract: A method for producing a plurality of optoelectronic devices is specified, comprising the following steps: providing a connection carrier assemblage having a plurality of device regions, wherein at least one electrical connection region is provided in each of the device regions, providing a semiconductor body carrier, on which a plurality of separate semiconductor bodies connected to the semiconductor body carrier are arranged, wherein the semiconductor bodies each have a semiconductor layer sequence having an active region, arranging the connection carrier assemblage and the semiconductor body carrier relative to one another in such a way that the semiconductor bodies face the device regions, mechanically connecting a plurality of semiconductor bodies to the connection carrier assemblage in a mounting region of a device region assigned to the respective semiconductor body, electrically conductively connecting the respective semiconductor body to the connection region of the device region assigned to the semi

Abstract: A method of forming a semiconductor package includes attaching a semiconductor substrate on a support substrate, wherein the semiconductor substrate includes a plurality of first semiconductor chips and a chip cutting region that separates respective ones of the semiconductor chips. A first cutting groove is formed that has a first kerf width between first and second ones of the plurality of first semiconductor chips. A plurality of second semiconductor chips is attached to the plurality of first semiconductor chips. A molding layer is formed so as to fill the first cutting groove and a second cutting groove having a second kerf width that is less than the first kerf width is formed in the molding layer so as to form individual molding layers covering one of the plurality of first semiconductor chips and one of the plurality of second semiconductor chips.

Abstract: A method for manufacturing light emitting diodes includes steps: providing a substrate having an upper conductive layer and a lower conductive layer formed on a top face and bottom face thereof; dividing each of the upper conductive layer and the lower conductive layer into first areas and second areas; defining cavities in the substrate through the first areas of the upper conductive layer to expose the lower conductive layer; forming conductive posts within the substrate; forming an overlaying layer to connect the first areas of the upper and lower conductive layers; mounting chips on the overlaying layer within the cavities and electrically connecting each chip with an adjacent first area and post; forming an encapsulant on the substrate to cover the chips; and cutting the substrate into individual packages.

Abstract: The present invention relates to a dicing tape-integrated film for semiconductor back surface including: a dicing tape including a base material and a pressure-sensitive adhesive layer laminated in this order, and a film for semiconductor back surface provided on the pressure-sensitive adhesive layer of the dicing tape, where the pressure-sensitive adhesive layer has a thickness of from 20 ?m to 40 ?m.

Abstract: A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure.

Abstract: A method of manufacturing a light-emitting device using laser scribing to improve overall light output is disclosed. Upon placing a semiconductor wafer having light emitting diode (“LED”) devices separated by streets on a wafer chuck, the process arranges a first surface of semiconductor wafer containing front sides of the LED devices facing up and a second surface of semiconductor wafer containing back sides of the LED devices facing toward the wafer chuck. After aligning a laser device over the first surface of the semiconductor wafer above a street, the process is configured to focus a high intensity portion of a laser beam generated by the laser device at a location in a substrate closer to the back sides of the LED devices.

Abstract: A chip-package includes a chip-carrier configured to carry a chip, the chip arranged over a chip-carrier side, wherein the chip-carrier side is configured in electrical connection with a chip back side; an insulation material including: a first insulation portion formed over a first chip lateral side; a second insulation portion formed over a second chip lateral side, wherein the first chip lateral side and the second chip lateral side each abuts opposite edges of the chip back side; and a third insulation portion formed over at least part of a chip front side, the chip front side including one or more electrical contacts formed within the chip front side; wherein at least part of the first insulation portion is arranged over the chip-carrier side and wherein the first insulation portion is configured to extend in a direction perpendicular to the first chip lateral side further than the chip-carrier.

Abstract: The present invention provides an under-fill material with which a semiconductor device having a high connection reliability can be provided while securing a usable material by reducing a difference in thermal-responsive behavior between a semiconductor element and an adherend, and a method for producing a semiconductor device using the under-fill material. In the under-fill material of the present invention, a storage elastic modulus E? [MPa] and a thermal expansion coefficient ? [ppm/K] after carrying out a heat-curing treatment at 175° C. for an hour satisfy the following formula (1) at 25° C.

Abstract: An integrated circuit assembly includes an insulating layer having a having a first surface and a second surface. A first active layer contacts the first surface of the insulating layer. A metal bond pad is electrically connected to the first active layer and formed on the second surface of the insulating layer. A substrate having a first surface and a second surface, with a second active layer formed in the first surface, is provided such that the first active layer is coupled to the second surface of the substrate.

Abstract: There is provided a method for producing a semiconductor device, which is capable of suppressing voids during mounting of a semiconductor element to produce a semiconductor device with high reliability. A method for producing a semiconductor device of the present invention includes the steps of: providing a sealing sheet having a base material and an under-fill material laminated on the base material; bonding the sealing sheet to a surface of a semiconductor wafer on which a connection member is formed; dicing the semiconductor wafer to form a semiconductor element with the under-fill material; retaining the semiconductor element with the under-fill material at 100 to 200° C. for 1 second or more; and electrically connecting the semiconductor element and the adherend through the connection member while filling a space between the adherend and the semiconductor element with the under-fill material.

Abstract: A double-side exposed semiconductor device includes an electric conductive first lead frame attached on top of a thermal conductive but electrical nonconductive second lead frame and a semiconductor chip flipped and attached on top of the first lead frame. The gate and source electrodes on top of the flipped chip form electrical connections with gate and source pins of the first lead frame respectively. The flipped chip and center portions of the first and second lead frames are then encapsulated with a molding compound, such that the heat sink formed at the center of the second lead frame and the drain electrode at bottom of the semiconductor chip are exposed on two opposite sides of the semiconductor device. Thus, heat dissipation performance of the semiconductor device is effectively improved without increasing the size of the semiconductor device.

Abstract: A semiconductor wafer has a plurality of semiconductor die distributed over a surface area. The semiconductor die are singulated from the semiconductor wafer. The semiconductor die are mounted to a carrier to form a reconstituted semiconductor wafer. The carrier has a surface area 10-50% larger than the surface area of the semiconductor wafer. The number of semiconductor die mounted to the carrier is greater than a number of semiconductor die singulated from the semiconductor wafer. The reconstituted wafer is mounted within a chase mold. The chase mold is closed with the semiconductor die disposed within a cavity of the chase mold. An encapsulant is dispersed around the semiconductor die within the cavity under temperature and pressure. The encapsulant can be injected into the cavity of the chase mold. The reconstituted wafer is removed from the chase mold. An interconnect structure is formed over the reconstituted wafer.

Abstract: The invention generally relates to a packaging method of an ultra-thin chip, more specifically, the invention relates to a method for packaging the ultra-thin chip with solder ball thermo-compression in wafer level packaging process. The method starts with disposing solder balls on metal pads arranged on the front surface of semiconductor chips that are formed at the front surface of a semiconductor wafer. The solder balls are soften by heating the wafer, a compression plate is applied with a pressure on the top ends of the solder balls thus forming a co-planar top surface at the top ends of the solder balls. A molding compound is deposited on the front surface of the wafer with the top ends of the solder balls exposed. The wafer is then ground from its back surface to reduce its thickness to achieve ultra-thin chip.

Abstract: The invention is related to a chip package including: a semiconductor substrate having at least one bonding pad region and at least one device region, wherein the semiconductor substrate includes a plurality of heavily doped regions in the bonding pad region, and two of the heavily doped regions are insulatively isolated; a plurality of conductive pad structures disposed over the bonding pad region; at least one opening disposed at a sidewall of the chip package to expose the heavily doped regions; and a conductive pattern disposed in the opening to electrically contact with the heavily doped region.

Abstract: A leadframe, device package, and mode of construction configured to attain a thin profile and improved thermal performance. Leadframes of this invention include a raised die attachment pad arrange above distal ends of leadframe leads. A package will further include a die electrically coupled with an underside surface of the raised die attachment pad, in one example, using ball bonds, the whole sealed in an encapsulant that exposed a bottom portion of the die and a portion of a lead. Two leadframe stacks of such packages are also disclosed as are methods of manufacture.

Abstract: A method of fabricating a composite semiconductor structure includes providing a substrate including a plurality of devices and providing a compound semiconductor substrate including a plurality of photonic devices. The method also includes dicing the compound semiconductor substrate to provide a plurality of photonic dies. Each die includes one or more of the plurality of photonics devices. The method further includes providing an assembly substrate, mounting the plurality of photonic dies on predetermined portions of the assembly substrate, aligning the substrate and the assembly substrate, joining the substrate and the assembly substrate to form a composite substrate structure, and removing at least a portion of the assembly substrate from the composite substrate structure.

Abstract: A semiconductor device includes a first die having top, bottom, and peripheral surfaces. A bond pad is formed over the top surface. An organic material is connected to the first die and disposed around the peripheral surface. A via hole is formed in the organic material. A metal trace connects the via hole to the bond pad. A conductive material is deposited in the via hole. A redistribution layer (RDL) has an interconnection pad disposed over the top surface of the first die.

Abstract: A microelectronic element is disclosed that includes a semiconductor chip and a continuous monolithic metallic edge-reinforcement ring that covers each of the plurality of edge surfaces of the semiconductor chip and extending onto the front surface. The semiconductor chip may have front and rear opposed surfaces and a plurality of contacts at the front surface and edge surfaces extending between the front and rear surfaces. The semiconductor chip may also embody at least an active device or a passive device.

Abstract: Disclosed herein is a semiconductor package including an electrical device having a first lateral surface; and a core substrate including a cavity in which the electrical device is positioned, wherein the core substrate is inclined in a thickness direction of the core substrate and has a second lateral surface that defines the cavity.

Abstract: A method of making a wafer level chip size package (WCSP) comprising providing a die having a first face with a plurality of bond pads thereon, a second face opposite the first face and a plurality of side faces extending between the first face and the second face, at least one of the plurality of side faces having saw induced microcracks therein; and coating at least one of the plurality of side faces with a thin veneer of adhesive that penetrates the microcracks. A WCSP produced by the method is also disclosed.

Abstract: A wafer level package includes a semiconductor die bonded on a supporting wafer. The semiconductor die has at least a step recess at its substrate. An underfill layer is formed between the semiconductor die and the supporting wafer. Moreover, the height of the underfill layer is limited by the step recess. During a fabrication process of the wafer level package, the step recess helps to reduce the stress on the wafer level package.

Abstract: An integrated circuit including an active region a passive region and a cut line in the passive region includes a passivation layer that includes an outer nitride layer over an oxide layer. The integrated circuit also includes a crack stop below the passivation layer and in the passive region, and a solder ball in the active region. The passivation layer has a trench formed therein in a location that is further from the active region than the crack stop and closer to the active region than the cut line, the trench passing completely through the outer nitride layer and a least a portion of the way through the oxide layer.

Abstract: The present disclosure provides methods for manufacturing a radio frequency (RF) powder including a plurality of RF particles, each of which includes a circuit element. A plurality of circuit elements, each corresponding to a different RF particle, may be formed on a first surface of a substrate. Grooves may be etched into the first surface of the substrate between the plurality of circuit elements. A protection film may be formed on each of the plurality of circuit elements and a portion of the substrate between a second, opposite surface of the substrate and bottoms of the grooves may be removed so that each of the plurality of circuit elements is associated with the remaining portion of the substrate.

Abstract: A semiconductor device includes an element forming region including at least one semiconductor element formed on at least one compound semiconductor layer formed on a substrate and a trench formed between an outer edge of the semiconductor device and the element forming region. The trench spatially separates the compound semiconductor layer, and the trench is formed at least to reach the substrate.

Abstract: A resin composition which can be formed into a film for use in molding a large diameter thin film wafer is provided. The composition comprises components (A) a silicone resin containing repeating units represented by the following formulae (1-1), (1-2), and (1-3) and having a weight average molecular weight as measured by GPC in terms of polystyrene of 3,000 to 500,000, wherein r, s, and t are independently a positive integer; the silicon atom at the terminal of the units constituting the repeating units represented by the formulae (1-1), (1-2), and (1-3) is bonded to the terminal carbon atom of the X1, X2, or X3 in the same or different unit; R1 is independently a monovalent hydrocarbon group containing 1 to 8 carbon atoms; X1, X2, and X3 are independently a divalent group; (B) a thermosetting resin; and (C) a filler.

Abstract: A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure.

Abstract: A method for separating a plurality of dies is provided.

Abstract: An embodiment electronic device comprises a semiconductor chip including a first main face, a second main face and side faces each connecting the first main face to the second main face. A metal layer is disposed above the second main face and the side faces, the metal layer including a porous structure.

Abstract: A substrate table used for manufacturing a chip is provided. The substrate table includes a substrate stage, a substrate placement surface formed on the substrate stage, and on which a substrate is placed, and a guiding member that can project and retract from the substrate placement surface. The guiding member positions the substrate when the guiding member is at a projected position abutting an edge portion of the substrate placed on the substrate placement surface, and the guiding member retracts at a time of applying a tape to the substrate.

Abstract: An electronic multi-component package is assembled by placing multiple electronic components within multiple openings of a package substrate, then depositing and curing adhesive filler in gaps between the components and the inner peripheries of the openings. Circuit features, including conductive interconnects, are formed by thin-film photolithography over both front and back surfaces of the package substrate. Preformed conductive vias through the package substrate provide electrical connection between circuit features on opposite substrate surfaces. Additional electronic components may be attached to conductive lands on at least one side of the package. The circuit features also include contact pads for external package connections, such as in a ball-grid-array or equivalent structure.

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, forming dielectric material surrounding the die, forming buildup layers in the dielectric material to form a coreless bumpless buildup package structure, and patterning the carrier material to form microchannel structures on the package structure.

Abstract: A fabricating process of circuit substrate sequently includes: providing a substrate with a pad and a dielectric stack layer disposed at the substrate and overlaying the pad, in which the stack layer includes two dielectric layers and a third dielectric layer located between the two dielectric layers, and the etching rate of the third dielectric layer is greater than the etching rate of the two dielectric layers; forming an opening corresponding to the pad at the stack layer; performing a wet etching process on the stack layer to remove the portion of the third dielectric layer surrounding the opening to form a gap between the portions of the two dielectric layers surrounding the opening; performing a plating process on the stack layer and the pad to respectively form two plating layers at the stack layer and the pad, in which the gap isolates the two plating layers from each other.

Abstract: A method of making a stacked microelectronic package by forming a microelectronic assembly by stacking a first subassembly including a plurality of microelectronic elements onto a second subassembly including a plurality of microelectronic elements, at least some of the plurality of microelectronic elements of said first subassembly and said second subassembly having traces that extend to respective edges of the microelectronic elements, then forming notches in the microelectronic assembly so as to expose the traces of at least some of the plurality of microelectronic elements, then forming leads at the side walls of the notches, the leads being in electrical communication with at least some of the traces and dicing the assembly into packages. Additional embodiments include methods for creating stacked packages using substrates and having additional traces that extend to both the top and bottom of the package.

Abstract: An optical device wafer processing method including a laser processed groove forming step of applying a laser beam for performing ablation to the front side or back side of a substrate of an optical device wafer along streets, thereby forming a laser processed groove as a break start point on the front side or back side of the substrate along each street, and a wafer dividing step of applying an external force to the optical device wafer after performing the laser processed groove forming step to thereby break the wafer along each laser processed groove, thereby dividing the wafer into individual optical devices. In performing the laser processed groove forming step, an etching gas atmosphere for etching a modified substance produced by applying the laser beam to the substrate is generated, whereby an etching gas in the etching gas atmosphere is converted into a plasma by the application of the laser beam to thereby etch away the modified substance.

Abstract: A method of manufacturing semiconductor chips includes providing a semiconductor substrate including circuit regions, irradiating the semiconductor substrate with a laser beam onto to form a frangible layer, and polishing the semiconductor substrate to separate the circuit regions of the semiconductor substrate from one another into semiconductor chips. The frangible layer may be removed completely during the polishing of the semiconductor substrate.

Abstract: Circuit modules including identification codes and a method of managing them are provided. A module substrate includes signal input output terminals and outer ground terminals provided at the peripheral portions of a surface which becomes a mounting surface when the circuit module is completed. An inner-ground-terminal formation area surrounded by the signal input output terminals and the outer ground terminals includes a plurality of inner ground terminals arranged in a matrix of rows and columns. One of the edge portions is a direction identification area. The inner ground terminal is not provided in the direction identification area, and a first identification code having information about the position of the module substrate is provided in the direction identification area.

Abstract: A light emitting device package structure is described. The light emitting device package structure includes a substrate serving as a carrier supporting a light emitting device chip. The substrate and the light emitting device chip have a chip side and a substrate side separately. A first electrode layer is disposed on a first surface of the light emitting device chip and a second electrode layer is disposed on a second surface of the light emitting device chip, in which the first surface and the second surface are not coplanar. A first conductive trace is electrically connected to the first electrode layer and a second conductive trace is electrically connected to the second electrode layer. At least the first conductive trace or the second conductive trace is formed along the chip side and the substrate side simultaneously.

Abstract: A method of manufacturing a semiconductor package includes placing a semiconductor chip in a recess provided on a surface of a supporting body so that a part of the semiconductor chip projects from the recess; forming a resin part on the surface of the supporting body, the resin part encapsulating the projecting part of the semiconductor chip; removing the supporting body; and forming an interconnection structure electrically connected to the semiconductor chip by using the resin part as a part of the base body of the semiconductor package.

Abstract: An improved structure of semiconductor chips with enhanced die strength and a fabrication method thereof are disclosed. The improved structure comprises a substrate, an active layer, and a backside metal layer, in which the active layer is formed on the front side of the substrate and includes at least one integrated circuit; the backside metal layer is formed on the backside of the substrate, which fully covers the area corresponding to the area covered by the integrated circuits in the active layer. By using the specific dicing process of the present invention, the backside metal layer and the substrate can be diced tidily. Die cracking on the border between the substrate and the backside metal layer of the diced single chip can be prevented, and thereby the die strength can be significantly enhanced.

Abstract: According to an embodiment, a method of forming a semiconductor device includes: providing a wafer having a semiconductor substrate with a first side a second side opposite the first side, and a dielectric region arranged on the first side; mounting the wafer with the first side on a carrier system; etching a deep vertical trench from the second side through the semiconductor substrate to the dielectric region, thereby insulating a mesa region from the remaining semiconductor substrate; and filling the deep vertical trench with a dielectric material.

Abstract: It is an object of the present invention to decrease a unit cost of an IC chip and to achieve the mass-production of IC chips. According to the present invention, a substrate having no limitation in size, such as a glass substrate, is used instead of a silicon substrate. This achieves the mass-production and the decrease of the unit cost of the IC chip. Further, a thin IC chip is provided by grinding and polishing the substrate such as the glass substrate.

Abstract: In a semiconductor device package having a stress relief spacer, and a manufacturing method thereof, metal interconnect fingers extend from the body of a chip provide for chip interconnection. The metal fingers are isolated from the body of the chip by a stress-relief spacer. In one example, such isolation takes the form of an air gap. In another example, such isolation takes the form of an elastomer material. In either case, mismatch in coefficient of thermal expansion between the metal interconnect fingers and the body of the chip is avoided, alleviating the problems associated with cracking and delamination, and leading to improved device yield and device reliability.

Abstract: A method of manufacturing a semiconductor device includes providing a carrier and attaching a plurality of semiconductor chips to the carrier. The semiconductor chips have a first electrode pad on a first main face and at least a second electrode pad on a second main face opposite to the first main face, whereby the first electrode pad is electrically connected to the carrier. A plurality of first bumps are formed on the carrier, the first bumps being made of a conductive material. The carrier is then singulated into a plurality of semiconductor devices, wherein each semiconductor device includes at least one semiconductor chip and one first bump.