Substrate Dicing Patents (Class 438/113)
  • Publication number: 20130217185
    Abstract: A recess is formed into a first side of a wafer such that a thinned center portion of the wafer is formed, and such that the central portion is surrounded by a thicker peripheral edge support portion. The second side of the wafer remains substantially entirely planar. After formation of the thinned wafer, vertical power devices are formed into the first side of the central portion of the wafer. Formation of the devices involves forming a plurality of diffusion regions into the first side of the thinned central portion. Metal electrodes are formed on the first and second sides, the peripheral portion is cut from the wafer, and the thin central portion is diced to form separate power devices. In one example, a first commercial entity manufactures the thinned wafers, and a second commercial entity obtains the thinned wafers and performs subsequent processing to form the vertical power devices.
    Type: Application
    Filed: February 20, 2012
    Publication date: August 22, 2013
    Applicant: IXYS Corporation
    Inventors: Elmar Wisotzki, Peter Ingram
  • Publication number: 20130217186
    Abstract: A method of manufacturing a semiconductor device, includes: providing an adhesive layer on a support body; providing a semiconductor element on the adhesive layer; providing a resin layer on the adhesive layer, the semiconductor element being provided on the adhesive layer, and forming a substrate on the adhesive layer, the substrate including the semiconductor element and the resin layer; and removing the substrate from the adhesive layer, wherein an adhesive force of the adhesive layer in a direction in which the substrate is removed is less than an adhesive force of the adhesive layer in a planar direction in which the substrate is formed.
    Type: Application
    Filed: January 23, 2013
    Publication date: August 22, 2013
    Applicant: FUJITSU LIMITED
    Inventor: FUJITSU LIMITED
  • Patent number: 8513759
    Abstract: A photodiode array for near infrared rays that includes photodiodes having a uniform size and a uniform shape, has high selectivity for the wavelength of received light between the photodiodes, and has high sensitivity with the aid of a high-quality semiconducting crystal containing a large amount of nitrogen, a method for manufacturing the photodiode array, and an optical measurement system are provided. The steps of forming a mask layer 2 having a plurality of openings on a first-conductive-type or semi-insulating semiconductor substrate 1, the openings being arranged in one dimension or two dimensions, and selectively growing a plurality of semiconductor layers 3a, 3b, and 3c including an absorption layer 3b in the openings are included.
    Type: Grant
    Filed: October 18, 2010
    Date of Patent: August 20, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Yasuhiro Iguchi, Hiroshi Inada, Youichi Nagai
  • Patent number: 8513060
    Abstract: A method for forming a sealing body without cracks in manufacture of a semiconductor device having an external terminal formed through the use of an electrolysis plating method. A front surface of a semiconductor wafer is placed over a front surface of a first support heated to a first temperature. An adhesive sheet is then bonded to a back surface of the semiconductor wafer, after which the semiconductor wafer is subjected to heat treatment at a second temperature higher than the first temperature. After the semiconductor wafer and the adhesive sheet are cut along cutting regions, a plurality of semiconductor chips each having an adhesive patch bonded thereto are obtained. A mother substrate is placed over a front surface of a second support heated to a third temperature and the semiconductor chips are fixed to an upper surface of the mother substrate via the adhesive patch.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: August 20, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Hiroaki Narita
  • Patent number: 8507322
    Abstract: Provided is a method for manufacturing a semiconductor device, which prevents waste generation from being caused peeling of films and prevents failure of peeling from being caused by waste due to peeling of films. A first semiconductor substrate is used which has a structure in which a peeling layer is not formed in a section subjected to a first dividing treatment, so that the peeling layer is not exposed at the end surface of a second semiconductor substrate when the second semiconductor substrate is cut out of the first semiconductor substrate. In addition, a supporting material is provided on a layer to be peeled of the second semiconductor substrate before the second semiconductor substrate is subjected to a second dividing treatment.
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: August 13, 2013
    Inventors: Akihiro Chida, Yoshiaki Oikawa, Chiho Kawanabe
  • Patent number: 8507321
    Abstract: An embodiment of the invention provides a chip package which includes: a carrier substrate; a semiconductor substrate having an upper surface and a lower surface, disposed overlying the carrier substrate; a device region or sensing region located on the upper surface of the semiconductor substrate; a conducting pad located on the upper surface of the semiconductor substrate; a conducting layer electrically connected to the conducting pad and extending from the upper surface of the semiconductor substrate to a sidewall of the semiconductor substrate; and an insulating layer located between the conducting layer and the semiconductor substrate.
    Type: Grant
    Filed: May 11, 2011
    Date of Patent: August 13, 2013
    Inventors: Chao-Yen Lin, Yi-Hang Lin
  • Patent number: 8507302
    Abstract: Techniques for fabricating metal devices, such as vertical light-emitting diode (VLED) devices, power devices, laser diodes, and vertical cavity surface emitting laser devices, are provided. Devices produced accordingly may benefit from greater yields and enhanced performance over conventional metal devices, such as higher brightness of the light-emitting diode and increased thermal conductivity. Moreover, the invention discloses techniques in the fabrication arts that are applicable to GaN-based electronic devices in cases where there is a high heat dissipation rate of the metal devices that have an original non- (or low) thermally conductive and/or non- (or low) electrically conductive carrier substrate that has been removed.
    Type: Grant
    Filed: October 11, 2006
    Date of Patent: August 13, 2013
    Assignee: SemiLEDs Optoelectronics Co., Ltd.
    Inventors: Chen-Fu Chu, Hao-Chun Cheng, Trung Tri Doan, Feng-Hsu Fan
  • Patent number: 8507320
    Abstract: One aspect is a method including providing a carrier having a first conducting layer, a first insulating layer over the first conducting layer, and at least one through-connection from a first face of the first insulating layer to a second face of the first insulating layer; attaching at least two semiconductor chips to the carrier; applying a second insulating layer over the carrier; opening the second insulating layer until the carrier is exposed; depositing a metal layer over the opened second insulating layer; and separating the at least two semiconductor chips after depositing the metal layer.
    Type: Grant
    Filed: March 18, 2008
    Date of Patent: August 13, 2013
    Assignee: Infineon Technologies AG
    Inventors: Ralf Otremba, Henrik Ewe, Klaus Schiess, Manfred Mengel
  • Publication number: 20130200429
    Abstract: A method of growth and transfer of epitaxial structures from semiconductor crystalline substrate(s) to an assembly substrate. Using this method, the assembly substrate encloses one or more semiconductor materials and defines a wafer size that is equal to or larger than the semiconductor crystalline substrate for further wafer processing. The process also provides a unique platform for heterogeneous integration of diverse material systems and device technologies onto one single substrate.
    Type: Application
    Filed: December 21, 2012
    Publication date: August 8, 2013
    Inventor: Eric Ting-Shan Pan
  • Publication number: 20130200502
    Abstract: A method of manufacturing a semiconductor device includes providing a transfer foil. A plurality of semiconductor chips is placed on and adhered to the transfer foil. The plurality of semiconductor chips adhered to the transfer foil is placed over a multi-device carrier. Heat is applied to laminate the transfer foil over the multi-device carrier, thereby accommodating the plurality of semiconductor chips between the laminated transfer foil and the multi-device carrier.
    Type: Application
    Filed: February 8, 2012
    Publication date: August 8, 2013
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Ivan Nikitin, Stefan Landau, Joachim Mahler, Alexander Heinrich, Ralf Wombacher
  • Publication number: 20130200534
    Abstract: Described herein is a sealant laminated composite for collectively sealing a semiconductor device's mounting surface of a substrate on which semiconductor devices are mounted or a semiconductor device's forming surface of a wafer on which semiconductor devices are formed. The composite can include a support wafer and an uncured resin layer constituted of an uncured thermosetting resin formed on one side of the support wafer. In certain aspects, the sealant laminated composite is very versatile, even when a large diameter or thin substrate or wafer is sealed.
    Type: Application
    Filed: January 24, 2013
    Publication date: August 8, 2013
    Applicant: SHIN-ETSU CHEMICAL CO., LTD.
    Inventor: SHIN-ETSU CHEMICAL CO., LTD.
  • Publication number: 20130200504
    Abstract: An electronic component module includes a double-sided mounting board having a front surface and a back surface; components mounted on the front surface and the back surface of the double-sided mounting board; an insulating resin sealing the components mounted on the front surface and the back surface; and a lead frame bonded to the back surface of the double-sided mounting board. The back surface of the double-sided mounting board is sealed with the insulating resin such that the lead frame is not covered by the insulating resin, and the thickness of the insulating resin sealing the components mounted on the back surface of the double-sided mounting board is less than or equal to the thickness of the lead frame.
    Type: Application
    Filed: February 4, 2013
    Publication date: August 8, 2013
    Applicant: MITSUMI ELECTRIC CO., LTD.
    Inventors: Takayuki OTSUKA, Fujio FURUKAWA, Ryuichi WADA, Makoto KITAZUME, Toshiki KOMIYAMA
  • Patent number: 8502380
    Abstract: A chip package and a fabrication method thereof are provided. The chip package includes a semiconductor substrate containing a semiconductor component and a conductive pad thereon. A through hole penetrates the semiconductor substrate from a backside thereof to expose the conductive pad. A redistribution layer is below the backside of the semiconductor substrate and electrically connected to the conductive pad in the through hole. A conductive trace layer is below the redistribution layer and extended along a sidewall of the semiconductor substrate to electrically contact with an edge of the redistribution layer.
    Type: Grant
    Filed: October 6, 2010
    Date of Patent: August 6, 2013
    Assignee: Xintec Inc.
    Inventor: Chien-Hung Liu
  • Patent number: 8501541
    Abstract: A semiconductor device is made by disposing a plurality of semiconductor die on a carrier and creating a gap between each of the semiconductor die. A first insulating material is deposited in the gap. A portion of the first insulating material is removed. A conductive layer is formed over the semiconductor die. A conductive lining is conformally formed on the remaining portion of the first insulating material to form conductive via within the gap. The conductive vias can be tapered or vertical. The conductive via is electrically connected to a contact pad on the semiconductor die. A second insulating material is deposited in the gap over the conductive lining. A portion of the conductive via may extend outside the first and second insulating materials. The semiconductor die are singulated through the gap. The semiconductor die can be stacked and interconnected through the conductive vias.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: August 6, 2013
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Reza A. Pagaila, Linda Pei Ee Chua, Byung Tai Do
  • Patent number: 8502261
    Abstract: Side-mountable semiconductor light emitting device packages include an electrically insulating substrate having a front face and a back face and a side face extending therebetween. The side face is configured for mounting on an underlying surface. An electrically conductive contact is provided proximate an edge of the substrate on the back face of the substrate and/or on a recessed region on the side face of the substrate. The contact is positioned to be positioned proximate an electrical connection region of the underlying surface when the semiconductor light emitting device package is side mounted on the underlying surface. A conductive trace extends along the front face of the substrate and is electrically connected to the contact. A semiconductor light emitting device is mounted on the front face of the substrate and electrically connected to the conductive trace.
    Type: Grant
    Filed: March 2, 2011
    Date of Patent: August 6, 2013
    Assignee: Cree, Inc.
    Inventor: Ban P. Loh
  • Patent number: 8501542
    Abstract: A dual-face package has an LSI chip sealed with a mold resin, and electrodes for external connections on both of the front face and the back face. The LSI chip is bonded onto the die pad of a leadframe whose outer lead portions are exposed as back-face electrodes at at least the back face. The LSI chip and a plurality of inner lead portions of the leadframe are connected by wiring. At least some of the plurality of inner lead portions have front-face electrodes integrally formed by working a portion of the leadframe. Head faces of the front-face electrodes, or bump electrodes connected to the respective head faces of the front-face electrodes serve as electrodes for external connections to another substrate, element, or the like.
    Type: Grant
    Filed: March 5, 2012
    Date of Patent: August 6, 2013
    Assignee: Oki Semiconductor Co., Ltd
    Inventors: Masamichi Ishihara, Harufumi Kobayashi
  • Patent number: 8501543
    Abstract: A method and structure provides a Direct Write Wafer Level Chip Scale Package (DWWLCSP) that utilizes permanent layers/coatings and direct write techniques to pattern these layers/coatings, thereby avoiding the use of photoimagable materials and photo-etching processes.
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: August 6, 2013
    Assignee: Amkor Technology, Inc.
    Inventors: Christopher John Berry, Ronald Patrick Huemoeller, David Jon Hiner
  • Publication number: 20130196470
    Abstract: A chip package includes a substrate having a pad region, a device region, and a remained scribe region located at a periphery of the substrate; a signal and an EMI ground pads disposed on the pad region; a first and a second openings penetrating into the substrate to expose the signal and the EMI ground pads, respectively; a first and a second conducting layers located in the first and the second openings and electrically connecting the signal and the EMI ground pads, respectively, wherein the first conducting layer and the signal pad are separated from a periphery of the remained scribe region, and wherein a portion of the second conducting layer and/or the EMI ground pad extend(s) to a periphery of the remained scribe region; and a third conducting layer surrounding the periphery of the remained scribe region to electrically connect the second conducting layer and/or the EMI ground pad.
    Type: Application
    Filed: March 13, 2013
    Publication date: August 1, 2013
    Applicant: XINTEC INC.
    Inventor: XINTEC INC.
  • Patent number: 8497159
    Abstract: A method of manufacturing a leadless integrated circuit (IC) package comprising an IC chip mounted on a metal leadframe and a plurality of electrical contacts electrically coupled to the IC chip. The IC chip, the electrical contacts, and a portion of the metal leadframe are covered with an encapsulation compound, with portions of the electrical contacts exposed on a bottom surface of the encapsulation compound. The electrical contacts of the IC package having metal traces connecting bonding areas on a top surface thereof and contact areas on a bottom surface thereof, wherein at least some of the bonding areas are laterally disposed from the contact areas connected thereto.
    Type: Grant
    Filed: November 2, 2011
    Date of Patent: July 30, 2013
    Assignee: Kaixin, Inc.
    Inventor: Tung Lok Li
  • Patent number: 8497160
    Abstract: A solder-top enhanced semiconductor device is proposed for packaging. The solder-top device includes a device die with a top metal layer patterned into contact zones and contact enhancement zones. At least one contact zone is electrically connected to at least one contact enhancement zone. Atop each contact enhancement zone is a solder layer for an increased composite thickness thus lowered parasitic impedance. Where the top metal material can not form a uniform good electrical bond with the solder material, the device die further includes an intermediary layer sandwiched between and forming a uniform electrical bond with the top metal layer and the solder layer. A method for making the solder-top device includes lithographically patterning the top metal layer into the contact zones and the contact enhancement zones; then forming a solder layer atop each of the contact enhancement zones using a stencil process for an increased composite thickness.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: July 30, 2013
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventors: François Hébert, Anup Bhalla, Kai Liu, Ming Sun
  • Publication number: 20130187263
    Abstract: A method of fabricating a semiconductor stacked package is provided. A singulation process is performed on a wafer and a substrate, on which the wafer is stacked. A portion of the wafer on a cutting region is removed, to form a stress concentrated region on an edge of a chip of the wafer. The wafer and the substrate are then cut, and a stress is forced to be concentrated on the edge of the chip of the wafer. As a result, the edge of the chip is warpaged. Therefore, the stress is prevented from extending to the inside of the chip. A semiconductor stacked package is also provided.
    Type: Application
    Filed: January 10, 2013
    Publication date: July 25, 2013
    Applicant: XINTEC INC.
    Inventor: Xintec Inc.
  • Publication number: 20130187284
    Abstract: A low cost and high performance flip chip package is disclosed. By assembling the package using a substrate panel level process, a separate fabrication of a substrate is avoided, thus enabling the use of a coreless substrate. The coreless substrate may include multiple stacked layers of laminate dielectric films having conductive traces and vias. As a result, electrical connection routes may be provided directly from die contact pads to package contact pads without the use of conventional solder bumps, thus accommodating very high density semiconductor dies with small feature sizes. The disclosed flip chip package provides lower cost, higher electrical performance, and improved thermal dissipation compared to conventional fabricated substrates with solder bumped semiconductor dies.
    Type: Application
    Filed: January 24, 2012
    Publication date: July 25, 2013
    Applicant: BROADCOM CORPORATION
    Inventors: Mengzhi Pang, Ken Zhonghua Wu, Matthew Kaufmann
  • Publication number: 20130189814
    Abstract: a An improved semiconductor device package is manufactured by attaching semiconductor chips (130) on an insulating substrate (101) having contact pads (103). A mold is provided, which has a top portion (210) with metal protrusions (202) at locations matching the pad locations. The protrusions are shaped as truncated cones. The substrate and the chips are loaded onto the bottom mold portion (310); the mold is closed by clamping the top portion onto the bottom portion so that the protrusions approach the contact pads. Encapsulation compound is introduced into the cavity and the protrusions create apertures through the encapsulation compound towards the pad locations.
    Type: Application
    Filed: March 7, 2013
    Publication date: July 25, 2013
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Texas Instruments Incorporated
  • Publication number: 20130187258
    Abstract: A method includes bonding a first and a second package component on a top surface of a third package component, and dispensing a polymer. The polymer includes a first portion in a space between the first and the third package components, a second portion in a space between the second and the third package components, and a third portion in a gap between the first and the second package components. A curing step is then performed on the polymer. After the curing step, the third portion of the polymer is sawed to form a trench between the first and the second package components.
    Type: Application
    Filed: January 23, 2012
    Publication date: July 25, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Szu Wei Lu, Ying-Da Wang, Li-Chung Kuo, Jing-Cheng Lin
  • Patent number: 8492201
    Abstract: A semiconductor device is made by providing a first semiconductor wafer having semiconductor die. A gap is made between the semiconductor die. An insulating material is deposited in the gap. A portion of the insulating material is removed to form a first through hole via (THV). A conductive lining is conformally deposited in the first THV. A solder material is disposed above the conductive lining of the first THV. A second semiconductor wafer having semiconductor die is disposed over the first wafer. A second THV is formed in a gap between the die of the second wafer. A conductive lining is conformally deposited in the second THV. A solder material is disposed above the second THV. The second THV is aligned to the first THV. The solder material is reflowed to form the conductive vias within the gap. The gap is singulated to separate the semiconductor die.
    Type: Grant
    Filed: May 6, 2010
    Date of Patent: July 23, 2013
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Reza A. Pagaila, Linda Pei Ee Chua, Byung Tai Do
  • Patent number: 8492907
    Abstract: The present invention relates to a film for flip chip type semiconductor back surface to be formed on a back surface of a semiconductor element flip chip-connected onto an adherend, the film having a light transmittance at a wavelength of 532 nm or 1064 nm of 20% or less, and having a contrast between a marking part and a part other than the marking part after laser marking of 20% or more.
    Type: Grant
    Filed: July 19, 2011
    Date of Patent: July 23, 2013
    Assignee: Nitto Denko Corporation
    Inventors: Naohide Takamoto, Goji Shiga, Fumiteru Asai
  • Patent number: 8492202
    Abstract: In a structure of a semiconductor device, a Si chip and a metal leadframe are jointed by metallic bond via a porous joint layer made of high conductive metal, having a three-dimensional network structure and using Ag as a bonding material, and a film containing Zn oxide or Al oxide is formed on a surface of a semiconductor assembly contacting to a polymer resin. In this manner, by the joint with the joint layer having the porous structure mainly made of Ag, thermal stress load of the Si chip can be reduced, and fatigue life of the joint layer itself can be improved. Besides, since adhesion of the polymer resin to the film can be enhanced by the anchor effect, occurrence of cracks in a bonding portion can be prevented, so that a highly-reliable Pb-free semiconductor device can be provided.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: July 23, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Ryoichi Kajiwara, Shigehisa Motowaki, Kazutoshi Ito, Toshiaki Ishii, Katsuo Arai, Takuya Nakajo, Hidemasa Kagii
  • Publication number: 20130181225
    Abstract: A semiconductor device includes a metal substrate including a metal base plate, an insulating sheet located on the metal base plate, and a wiring pattern located on the insulating sheet, and a semiconductor element located on the metal substrate. The semiconductor element is sealed with a molding resin. The molding resin extends to side surfaces of the metal substrate. On the side surfaces of the metal substrate, the insulating sheet and the wiring pattern are not exposed from the molding resin, whereas the metal base plate includes a projecting portion exposed from the molding resin.
    Type: Application
    Filed: September 14, 2012
    Publication date: July 18, 2013
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Seiji OKA, Kazuhiro TADA, Hiroshi YOSHIDA
  • Publication number: 20130181341
    Abstract: A semiconductor package structure and a method for manufacturing the same are provided, in which a semiconductor die is disposed in a spacer structure for packaging, and a connection pad, a first metallic layer, an insulating layer, a wiring layer, a pin base, a conductive via and a metallic bump are formed on the semiconductor die, wherein the wiring layer can be formed as a single layer or multiple layers, and the connection pad is electrically connected with an outer pin. Moreover, the positioning structures are also formed to overcome the conventional misalignment problems caused by the thermal expansion and the cooling contraction. The alignment of the conductive via with the connection pad can be more accurately achieved, which ensures that the connection pad is reliably connected with the outer pin.
    Type: Application
    Filed: January 14, 2012
    Publication date: July 18, 2013
    Inventor: Wan-Ling Yu
  • Publication number: 20130181333
    Abstract: A method of manufacturing a semiconductor package structure is provided. A supporting plate and multiple padding patterns on an upper surface of the supporting plate define a containing cavity. Multiple leads electrically insulated from one another are formed on the padding patterns, extend from top surfaces of the padding patterns along side surfaces to the upper surface and are located inside the containing cavity. A chip is mounted inside the containing cavity, electrically connected to the leads. A molding compound is formed to encapsulate at least the chip, a portion of the leads and a portion of the supporting plate, fill the containing cavity and gaps among the padding patterns, and exposes a portion of the leads on the top surface. The supporting plate is removed to expose a back surface of each padding pattern, a bottom surface of the molding compound and a lower surface of each lead.
    Type: Application
    Filed: October 18, 2012
    Publication date: July 18, 2013
    Applicant: CHIPMOS TECHNOLOGIES INC.
    Inventor: ChipMOS Technologies Inc.
  • Publication number: 20130181343
    Abstract: A multi-chip package includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip has a first active surface. The second semiconductor chip has a second active surface facing the first active surface. The second active surface is electrically connected with the first active surfaceand the first active surface of the first semiconductor chip and the second active surface of the second semiconductor chip are bonded to each other without an adhesive.
    Type: Application
    Filed: October 17, 2012
    Publication date: July 18, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: SAMSUNG ELECTRONICS CO., LTD.
  • Patent number: 8487387
    Abstract: A device (20, 90) includes sensors (28, 30) that sense different physical stimuli. A pressure sensor (28) includes a reference element (44) and a sense element (52), and an inertial sensor (30) includes a movable element (54). Fabrication (110) entails forming (112) a first substrate structure (22, 92) having a cavity (36, 100), forming a second substrate structure (24) to include the sensors (28, 30), and coupling (128) the substrate structures so that the first sensor (28) is aligned with the cavity (36, 100) and the second sensor (30) is laterally spaced apart from the first sensor (28). Forming the second structure (24) includes forming (118) the sense element (52) from a material layer (124) of the second structure (24) and following coupling (128) of the substrate structures, concurrently forming (132) the reference element (44) and the movable element (54) in a wafer substrate (122) of the second structure (24).
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: July 16, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Yizhen Lin, Woo Tae Park, Mark E. Schlarmann, Hemant D. Desai
  • Patent number: 8486757
    Abstract: A method and apparatus of packaging a semiconductor device with a clip is disclosed. The clip defines a first contact region and a second contact region on a same face of the at least one clip. The chip defines a first face, and a second face opposite to the first face, the first contact region being attached to the first face of the chip and the second contact region being located within a same plane with the second face of the clip.
    Type: Grant
    Filed: November 25, 2009
    Date of Patent: July 16, 2013
    Assignee: Infineon Technologies AG
    Inventors: Boon Huat Lim, Chee Chian Lim, Yoke Chin Goh
  • Patent number: 8486761
    Abstract: A multi-chip light emitting device (LED) uses a low-cost carrier structure that facilitates the use of substrates that are optimized to support the devices that require a substrate. Depending upon the type of LED elements used, some of the LED elements may be mounted on the carrier structure, rather than on the more expensive ceramic substrate. In like manner, other devices, such as sensors and control elements, may be mounted on the carrier structure as well. Because the carrier and substrate structures are formed independent of the encapsulation and other after-formation processes, these structures can be tested prior to encapsulation, thereby avoiding the cost of these processes being applied to inoperative structures.
    Type: Grant
    Filed: October 21, 2010
    Date of Patent: July 16, 2013
    Assignee: Koninklijke Philips Electronics N.V.
    Inventor: Serge J. Bierhuizen
  • Patent number: 8486804
    Abstract: A semiconductor device including a first element including a photodiode and an amplifier circuit which amplifies output current of the photodiode, over a first insulating film; and a second element including a color filter and an overcoat layer over the color filter over a second insulating film is manufactured. The first element and the second element are attached to each other by bonding the first insulating film and the second insulating film with a bonding material. Further, the amplifier circuit is a current mirror circuit including a thin film transistor. Still further, a color film may be used instead of a color filter.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: July 16, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masahiro Katayama, Yoshiaki Oikawa, Atsushi Hirose, Masayuki Sakakura
  • Patent number: 8486763
    Abstract: A method for thinning and dicing a wafer of electronic circuits, wherein: a thinning step is carried out while the wafer is supported by a first film bonded at the periphery of a support frame; and a dicing step is carried out while the thinned wafer is supported by a second film bonded at the periphery of the same frame from the other surface of the wafer, the first film being unstuck only once the second one is in place.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: July 16, 2013
    Assignee: STMicroelectronics (Tours) SAS
    Inventors: Vincent Jarry, Marc Feron
  • Publication number: 20130178017
    Abstract: A method for manufacturing semiconductor chips from a semiconductor wafer, including the steps of: fastening, on a first support frame, a second support frame having outer dimensions smaller than the outer dimensions of the first frame and greater than the inner dimensions of the first frame; arranging the wafer on a surface of a film stretched on the second frame; carrying out wafer processing operations by using equipment capable of receiving the first frame; separating the second frame from the first frame and removing the first frame; and carrying out wafer processing operations by using equipment capable of receiving the second frame.
    Type: Application
    Filed: March 4, 2013
    Publication date: July 11, 2013
    Applicant: STMicroelectronics (Tours) SAS
    Inventor: STMicroelectronics (Tours) SAS
  • Publication number: 20130175686
    Abstract: A flip chip package structure is proposed in which a redistribution layer (RDL) is disposed on a surface of both a semiconductor chip and one or more lateral extensions of the semiconductor chip surface. The lateral extensions may be made using, e.g., a reconstituted wafer to implement a fanout region lateral to one or more sides of the semiconductor chip. One or more electrical connectors such as solder bumps or copper cylinders may be applied to the RDL, and an interposer such as a PCB interposer may be connected to the electrical connectors. In this way, a relatively tight semiconductor pad pitch may be accommodated and translated to an appropriate circuit board pitch without necessarily requiring a silicon or glass interposer.
    Type: Application
    Filed: January 10, 2012
    Publication date: July 11, 2013
    Applicant: INTEL MOBILE COMMUNICATIONS GMBH
    Inventors: Thorsten Meyer, Gerald Ofner, Bernd Waidhas
  • Publication number: 20130175694
    Abstract: A method includes forming a dielectric layer over a substrate, forming an interconnect structure over the dielectric layer, and bonding a die to the interconnect structure. The substrate is then removed, and the dielectric layer is patterned. Connectors are formed at a surface of the dielectric layer, wherein the connectors are electrically coupled to the die.
    Type: Application
    Filed: January 6, 2012
    Publication date: July 11, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ying-Ching Shih, Szu Wei Lu, Jing-Cheng Lin
  • Patent number: 8481342
    Abstract: A method for manufacturing a semiconductor device, includes: a step of etching a Si (111) substrate along a (111) plane of the Si (111) substrate to separate a Si (111) thin-film device having a separated surface along the (111) plane.
    Type: Grant
    Filed: March 24, 2010
    Date of Patent: July 9, 2013
    Assignee: Oki Data Corporation
    Inventors: Mitsuhiko Ogihara, Tomohiko Sagimori, Takahito Suzuki, Masataka Muto
  • Patent number: 8481368
    Abstract: The invention relates to a semiconductor package of a flip chip and a method for making the semiconductor package. The semiconductor chip comprises a metal-oxide-semiconductor field effect transistor. On a die paddle including a first base, a second base and a third base, half-etching or punching is performed on the top surfaces of the first base and the second base to obtain plurality of grooves that divide the top surface of the first base into a plurality of areas comprising multiple first connecting areas, and divide the top surface of the second base into a plurality of areas comprising at least a second connecting area. The semiconductor chip is connected to the die paddle at the first connecting areas and the second connecting area.
    Type: Grant
    Filed: April 21, 2011
    Date of Patent: July 9, 2013
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventors: Yan Xun Xue, Yueh-Se Ho, Hamza Yilmaz, Jun Lu
  • Publication number: 20130168849
    Abstract: A method for manufacturing a device package may include constructing a spacer element coupled with a surface of a semiconductor die unit, where the spacer element is configured to create a gap between the semiconductor die unit and a surface of a carrier, and encapsulating the semiconductor die unit within a mold compound, where the encapsulating includes introducing the mold compound into the gap.
    Type: Application
    Filed: December 30, 2011
    Publication date: July 4, 2013
    Applicant: DECA TECHNOLOGIES, INC.
    Inventor: Christopher M. Scanlan
  • Patent number: 8476097
    Abstract: A method for manufacturing a thin-film solar cell includes providing a first conducting layer on a substrate that has an area at least 0.75 m2. The first conducting layer is located in a deposition portion of the area. An ultraviolet laser beam is applied through a lens to the first conducting layer. Portions of the first conducting layer are scribed form a trench through the layer. The lens focuses the beam and has a focal length at least 100 mm. The focused beam includes an effective portion effective for the scribing and an ineffective portion ineffective for the scribing. The substrate sags and the first conducting layer remains in the effective portion of the focused beam across the area during the step of applying. One or more active layers are provided on the first conducting layer. A second conducting layer is provided on the one or more active layers.
    Type: Grant
    Filed: August 28, 2008
    Date of Patent: July 2, 2013
    Assignee: Oerlikon Solar AG, Trubbach
    Inventor: Jiri Springer
  • Publication number: 20130161795
    Abstract: A disclosed method of manufacturing a semiconductor device includes forming a groove on a first surface of a semiconductor wafer along an outer periphery of the semiconductor wafer, forming a semiconductor device on the first surface, forming an adhesive layer on the first surface to cover the semiconductor device, bonding a support substrate to the first surface by the adhesive layer, grinding after the adhering of the support substrate a second surface of the semiconductor wafer opposite to the first surface, and dicing after the grinding the semiconductor wafer into individual semiconductor chips.
    Type: Application
    Filed: October 12, 2012
    Publication date: June 27, 2013
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: FUJITSU SEMICONDUCTOR LIMITED
  • Publication number: 20130161833
    Abstract: A semiconductor device has a semiconductor wafer with a plurality of semiconductor die. Contact pads are formed on a surface of the semiconductor die. The semiconductor die are separated to form a peripheral region around the semiconductor die. An encapsulant or insulating material is deposited in the peripheral region around the semiconductor die. An interconnect structure is formed over the semiconductor die and insulating material. The interconnect structure has an I/O density less than an I/O density of the contact pads on the semiconductor die. A substrate has an I/O density consistent with the I/O density of the interconnect structure. The semiconductor die is mounted to the substrate with the interconnect structure electrically connecting the contact pads of the semiconductor die to the first conductive layer of the substrate. A plurality of semiconductor die each with the interconnect structure can be mounted over the substrate.
    Type: Application
    Filed: December 23, 2011
    Publication date: June 27, 2013
    Applicant: STATS CHipPAC, Ltd.
    Inventor: Rajendra D. Pendse
  • Patent number: 8470643
    Abstract: Conductive core balls are joined to joint pads formed on an upper substrate. Core balls are joined to joint pads formed on an extending part of an upper-substrate substrate material. The joint pads formed on the extending part of the upper-substrate substrate material are joined to the joint pads formed on an extending part of a lower-substrate substrate material via the core balls. The joint pads formed in an area corresponding to the upper substrate of the upper-substrate substrate material are connected to the joint pads formed in an area corresponding to a lower substrate of the lower-substrate substrate material via the core balls and the conductive core balls. The upper-substrate substrate material is fixed to the lower-substrate substrate material by a mold resin supplied therebetween. The extending parts of the upper-substrate substrate material and the lower-substrate substrate material are removed, and the semiconductor packages are individualized.
    Type: Grant
    Filed: June 23, 2011
    Date of Patent: June 25, 2013
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Koichi Tanaka
  • Patent number: 8470642
    Abstract: Methods and devices for multi-chip stacks are shown. A method is shown that assembles multiple chips into stacks by stacking wafers prior to dicing into individual chips. Methods shown provide removal of defective chips and their replacement during the assembly process to improve manufacturing yield.
    Type: Grant
    Filed: July 9, 2010
    Date of Patent: June 25, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Paul A. Farrar
  • Patent number: 8470640
    Abstract: A method of fabricating a semiconductor die and a low profile semiconductor package are disclosed. The semiconductor package may include at least first and second stacked semiconductor die mounted to a substrate. The first and/or second semiconductor die may be fabricated with localized cavities through a bottom surface of the semiconductor die, along a side edge of the semiconductor die. The one or more localized cavities in a side take up less than the entire side. Thus, the localized cavities allow low height stacking of semiconductor die while providing each die with a high degree of structural integrity to prevent cracking or breaking of the die edge during fabrication.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: June 25, 2013
    Assignee: SanDisk Technologies Inc.
    Inventors: Hem Takiar, Shrikar Bhagath, Cheemen Yu, Chih-Chin Liao
  • Publication number: 20130157414
    Abstract: Consistent with an example embodiment, there is a semiconductor device comprised of a combination of device die. The semiconductor device comprises a package substrate having groups of pad landings. A first device die is anchored to the package substrate, the first device die having been wire-bonded to a first group of pad landings. At least one subsequent device die is anchored to the first device die. The at least one subsequent device die has an underside profile with recesses defined therein, the recesses of a size are defined to accommodate wires bonded to the first device die; the at least one subsequent device is wire bonded to a second group of pad landings.
    Type: Application
    Filed: September 26, 2012
    Publication date: June 20, 2013
    Applicant: NXP B. V.
    Inventor: NXP B. V.
  • Publication number: 20130154062
    Abstract: A die having a ledge along a sidewall, and a method of forming the die, is provided. A method of packaging the die is also provided. A substrate, such as a processed wafer, is diced by forming a first notch having a first width, and then forming a second notch within the first notch such that the second notch has a second width less than the first width. The second notch extends through the substrate, thereby dicing the substrate. The difference in widths between the first width and the second width results in a ledge along the sidewalls of the dice. The dice may be placed on a substrate, e.g., an interposer, and underfill placed between the dice and the substrate. The ledge prevents or reduces the distance the underfill is drawn up between adjacent dice. A molding compound may be formed over the substrate.
    Type: Application
    Filed: December 16, 2011
    Publication date: June 20, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Ying-Da Wang, Li-Chung Kuo, Szu Wei Lu