Abstract: A method of manufacture of a package-on-package system includes: providing a package substrate; attaching a semiconductor die to the package substrate; forming an encapsulant around the semiconductor die to have a bottom exposed surface coplanar with a bottom surface of the package substrate and to have a top exposed surface with through openings extending therefrom through the bottom exposed surface; and creating through vias by applying solder into the through openings, the through vias coplanar with the bottom exposed surface of the encapsulant and coplanar with the top exposed surface of the encapsulant.

Abstract: A method for manufacturing a holder of an LED package structure includes steps: providing first and second electrical portions; providing a mold including an upper die and a bottom die, the bottom die defining a receiving groove in a top surface thereof, the upper die including a core component and a wall around and spaced from the core component; putting the first and second electrical portions in the receiving groove of the bottom die, mounting the upper die on the bottom die; injecting liquid molding material into the receiving groove of the bottom die through a sprue between the wall and the core component; solidifying the liquid molding material and removing the upper die and the bottom die to obtain the holder which includes the first and second electrical portions and the solidified liquid molding material.

Abstract: A method and apparatus are described for fabricating a low-pin-count chip package (701) including a die pad (706) for receiving an integrated circuit device and a plurality of connection leads (702) having recessed lead ends (704) at the outer peripheral region of each contact lead. After forming the package body (202) over the integrated circuit device, unplated portions (104) of the exposed bottom surface of the selectively plated lead frame are partially etched to form recessed lead ends (302) at the outer peripheral region of each contact lead, and the recessed lead ends are subsequently re-plated (402) to provide wettable recessed lead ends at the outer peripheral region of each contact lead.

Abstract: A method of mounting an electronic component allows bumps to land onto electrodes via thermosetting flux formed of first thermosetting resin containing a first active ingredient, and brings a resin reinforcing member formed of second thermosetting resin containing a second active ingredient into contact with the electronic component at reinforcement sections, and then heats the substrate to form solder junction sections that bond the bumps to the electrodes. At the same time, the method forms resin reinforcement sections that reinforce the solder junction sections from the surroundings. A mixing ratio of the second active ingredient in the resin reinforcing member is set greater than a mixing ratio of the first active ingredient in the thermosetting flux.

Abstract: A semiconductor component having wetable leadframe lead surfaces and a method of manufacture. A leadframe having leadframe leads is embedded in a mold compound. A portion of at least one leadframe lead is exposed and an electrically conductive material is formed on the exposed portion. The mold compound is separated to form singulated semiconductor components.

Abstract: A method for packaging one or more power semiconductor devices is provided. A lead frame comprising one or more base die paddles, multiple lead terminals, and a tie bar assembly is constructed. The lead terminals extend to a predetermined elevation from the base die paddles. The base die paddles are connected to the lead terminals by the tie bar assembly. The tie bar assembly mechanically couples the base die paddles to each other and to the lead terminals. The tie bar assembly is selectively configured to isolate the lead terminals from the base die paddles and to enable creation of multiple selective connections between one or more of the lead terminals and one or more power semiconductor devices mounted on the base die paddles, thereby enabling flexible packaging of one or more isolated and/or non-isolated power semiconductor devices and increasing their power handling capacity.

Abstract: A method of packaging includes placing a package component over a release film, wherein solder balls on a surface of the package component are in physical contact with the release film. Next, A molding compound filled between the release film and the package component is cured, wherein during the step of curing, the solder balls remain in physical contact with the release film.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a lead having a lead overhang at an obtuse angle to a lead top side and having a lead ridge protruding from a lead non-horizontal side, the lead overhang having a lead overhang-undercut side at an acute angle to a lead overhang non-horizontal side; forming a lead conductive cap completely covering the lead overhang non-horizontal side and the lead top side; forming a package paddle adjacent the lead; mounting an integrated circuit over the package paddle; and forming an encapsulation over the integrated circuit, the package paddle, and the lead.

Abstract: A method for manufacturing light-emitting diode devices. Multiple metal frames are provided. The metal frames are adjacent to each other and are arranged on a same plane. Each metal frame includes a first connection pin and a second connection pin. A light-emitting diode chip is disposed on and electrically connected to each metal frame. The metal frames are respectively bent, enabling the adjacent metal frames to separate from each other. A moldboard formed with a plurality of mold cavities is provided. The bent metal frames are respectively disposed in the mold cavities, locating each light-emitting diode chip in each mold cavity. The mold cavities are respectively filled with package gel. The package gel filled in each mold cavity covers each light-emitting diode chip. The package gel is solidified. The mold cavities are separated from the package gel. The metal frames are separated from each other, forming the light-emitting diode devices.

Abstract: In the power semiconductor module, a wiring metal plate electrically connects between power semiconductor elements joined to the circuit pattern, and between the power semiconductor elements and the circuit pattern. Cylindrical main terminals are joined, substantially perpendicularly, to the wiring metal plate and the circuit pattern, respectively. A cylindrical control terminal is joined, substantially perpendicularly, to one of the power semiconductor elements.

Abstract: An integrated circuit is attached to a package substrate. The integrated circuit is electrically connected to the package substrate using a plurality of bond wires connected between a plurality of bond posts and a plurality of bond pads. A first plurality of the bond pads are along a first side of the integrated circuit and coupled to a first plurality of the bond posts with a first plurality of the bond wires. A second plurality of the bond pads are along a second side of the integrated circuit and coupled to a second plurality of the bond posts with a second plurality of the bond wires. Mold compound is injected through a plurality of openings in the package substrate. A first opening is between the first plurality of bond posts and the first side. A second opening is between the second plurality of bond posts and the second side.

Abstract: In one embodiment, an integrated circuit package includes a lead frame with a die paddle and several leads. Portions of the lead frame not having an external electrical connection may be thinned such that they may be encapsulated by an electrically insulating packaging material on the back of the lead frame. Portions of the lead frame having external electrical connections may have a thickness such that they are exposed through the packaging material. The lead frame may be covered by an electrically insulating cover to protect components on the lead frame from erroneous electrical contact or electro-static discharge (ESD) damage.

Abstract: A manufacturing method of a package structure is provided. A metal substrate is provided. The metal substrate has a first surface where a first seed layer is formed. A patterned insulating layer is formed on the first seed layer and exposes a portion of the first seed layer. A patterned circuit layer is formed on the exposed portion of the first seed layer and covers a portion of the patterned insulating layer. A chip-bonding process is performed to electrically connect a chip to the patterned circuit layer. An encapsulant encapsulating the chip and the patterned circuit layer and covering a portion of the pattered insulating layer is formed. The metal substrate and the first seed layer are removed to expose a bottom surface of the patterned insulating layer and a lower surface of the patterned circuit layer. Solder balls are formed on the lower surface of the patterned circuit layer.

Abstract: To increase the manufacturing yield of semiconductor devices by improving a joint failure of a bump electrode. In a semiconductor device in which a plurality of boding pads 4 formed on a front surface of a semiconductor chip 3 and a plurality of leads 2 are connected via a plurality of bump electrodes 5, respectively, the upper surface of the leads 2 is formed into a semi-glossy surface having a roughness a maximum height (Ry) of which is in a range greater than 0 ?m and not greater than 20 ?m (0 ?m<maximum height (Ry)?20 ?m), not into a planar surface (maximum height (Ry)=0).

Abstract: A manufacturing method of a package structure is provided. A seed layer is formed on a upper surface of a metal substrate. A patterned dry film layer is formed on a lower surface of the metal substrate and the seed layer. A portion of the seed layer is exposed by the patterned dry film layer. The patterned dry film layer is used as an electroplating mask to electroplate a circuit layer on the portion of the seed layer exposed by the patterned dry film layer. A chip is bonded to and electrically connected to the circuit layer. A molding compound is formed on the metal substrate. The molding compound encapsulates the chip, the circuit layer and the portion of the seed layer. A portion of the metal substrate and a portion of the seed layer are removed so as to expose a portion of the molding compound.

Abstract: In various embodiments, a semiconductor component may include a semiconductor layer having a front side and a back side; at least one electronic element formed at least partially in the semiconductor layer; at least one via formed in the semiconductor layer and leading from the front side to the back side of the semiconductor layer; a front side metallization layer disposed over the front side of the semiconductor layer and electrically connecting the at least one electronic element to the at least one via; a cap disposed over the front side of the semiconductor layer and mechanically coupled to the semiconductor layer, the cap being configured as a front side carrier of the semiconductor component; a back side metallization layer disposed over the back side of the semiconductor layer and electrically connected to the at least one via.

Abstract: A fabrication method for a resin encapsulated semiconductor device includes the steps of: (1) die-bonding a semiconductor device to a first electrical connection metallic terminal of a wiring substrate; (2) electrically connecting an electrode of the semiconductor device and a second electrical connection metallic terminal of the wiring substrate via an electrical connector; (3) surface treating such an assembly by applying a solution to a surface of the assembly and baking the applied solution; and (4) transfer-molding an insulating encapsulating resin onto the surface-treated assembly.

Abstract: In order to securely ground an exterior shield and reduce burden imposed on a dicing blade and the exterior shield, a method of producing a semiconductor module comprises a hole-forming step of forming a hole 30 extending from a top surface of a sealing resin layer 3 to a ground wiring 111 (112) provided at a collective substrate 100, a film-forming step of forming an electrically conductive film made of an electrically conductive material so as to cover at least the top surface of the sealing resin layer 3, an internal surface of the hole 20, and the ground wiring 111 (112), and a separation step of separating from each other a plurality of individual module sections which the individual module section comprises.

Abstract: A microelectronic assembly may include a microelectronic element having a plurality of element contacts at a face thereof, and a compliant dielectric element having a Young's modulus of less than about two gigapascal (GPa) and substrate contacts at a first surface joined to the element contacts. The substrate contacts may be electrically connected with terminals at a second surface of the compliant dielectric element that opposes the first surface, through conductive vias in the compliant dielectric element. A rigid underfill may be between the face of the microelectronic element and the first surface of the compliant dielectric element. The terminals may be usable for bonding the microelectronic assembly to corresponding contacts of a component external to the microelectronic assembly.

Abstract: A package structure having an MEMS element is provided, which includes: a protection layer having openings formed therein; conductors formed in the openings, respectively; conductive pads formed on the protection layer and the conductors; a MEMS chip disposed on the conductive pads; and an encapsulant formed on the protection layer for encapsulating the MEMS chip. By disposing the MEMS chip directly on the protection layer to dispense with the need for a carrier, such as a wafer or a circuit board that would undesirably add to the thickness, the present invention reduces the overall thickness of the package to thereby achieve miniaturization.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a package carrier; mounting an integrated circuit device to the package carrier; mounting an embeddable conductive structure, having a non-horizontal portion between a lower portion and an elevated portion and a hole, to the integrated circuit device with the lower portion over the integrated circuit device; mounting an interposer to the lower portion and below the elevated portion; and forming an encapsulation having a recess exposing the interposer and the elevated portion.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a terminal having a top with a depression; applying a dielectric material in the depression, the dielectric material having a gap formed therein and exposing a portion of the top therefrom; forming a trace within the gap and in direct contact with the top, the trace extending laterally over an upper surface of the dielectric material; and connecting an integrated circuit to the terminal through the trace.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming an isolated contact having a contact protrusion, the contact protrusion having a lower protrusion surface, an upper protrusion surface, and a protrusion sidewall; forming a die paddle, adjacent to the isolated contact, having a die paddle protrusion, the die paddle protrusion having a lower die protrusion surface, an upper die protrusion surface, and a die protrusion sidewall; depositing a contact pad on the contact protrusion; depositing a die paddle pad on the die paddle protrusion; coupling an integrated circuit die to the contact protrusion; and molding an encapsulation on the integrated circuit die.

Abstract: A manufacturing method of a circuit structure is provided. A metal layer having an upper surface is provided. A surface passivation layer is formed on the metal layer. The surface passivation layer exposes a portion of the upper surface of the metal layer, and a material of the metal layer is different from a material of the surface passivation layer. The metal layer and the surface passivation layer are dipped into a modifier, and the modifier is selectively absorbed and attached to the surface passivation layer, so as to form a covering layer. The covering layer has a plurality of nanoparticles and covers the surface passivation layer.

Abstract: Some exemplary embodiments of high voltage cascoded III-nitride semiconductor package utilizing clips on a package support surface have been disclosed. One exemplary embodiment comprises a III-nitride transistor attached to a package support surface and having an anode of a diode stacked over a source of the III-nitride transistor, a first conductive clip coupled to a gate of the III-nitride transistor and the anode of the diode, and a second conductive clip coupled to a drain of the III-nitride transistor. The conductive clips are connected to the package support surface and expose respective flat portions that are surface mountable. In this manner, reduced package footprint, improved surge current capability, and higher performance may be achieved compared to conventional wire bonded packages. Furthermore, since a low cost printed circuit board (PCB) may be utilized for the package support surface, expensive leadless fabrication processes may be avoided for cost effective manufacturing.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a die paddle having an internal portion with a trench along a perimeter of the die paddle; forming an interconnect having a concave indentation and an upper portion, the upper portion, opposite the concave indentation, aligned horizontally to the internal portion; attaching an integrated circuit device on the die paddle, the trench between the integrated circuit device and the perimeter; attaching an electrical connector to the integrated circuit device and to the upper portion; and applying an encapsulation over the integrated circuit device, the electrical connector, the die paddle, and the interconnect, the concave indentation exposed below the encapsulation.

Abstract: A manufacturing method of a circuit structure is provided. A metal layer having an upper surface is provided. A surface passivation layer is formed on the metal layer. The surface passivation layer exposes a portion of the upper surface of the metal layer, and a material of the metal layer is different from a material of the surface passivation layer. A covering layer is formed on the surface passivation layer, and the covering layer covers the surface passivation layer.

Abstract: Device and method for an electronic device package is disclosed. The electronic device package includes a first pad, a second pad and an encapsulation surrounding the first and second pad, wherein the encapsulation includes a first opening underneath the first pad and a second opening underneath the second pad. A first bump is arranged in the first opening and a second bump is arranged in the second opening, wherein the encapsulation mechanically locks the first bump to the first pad and the second bump to the second pad.

Abstract: A method includes: forming a photoresist pattern to form each of a semiconductor element mounting section on which a semiconductor element is mounted, semiconductor element electrode connection terminals for connection with electrodes of the semiconductor element, and a first outer frame section on a first surface of a metal plate; forming a photoresist pattern to form each of external connection terminals, a second outer frame section, and grooves in at least a part of the second outer frame section on a second surface of the metal plate; etching a metal plate exposing section, in which the metal plate of the second surface is exposed, to form holes that do not pass through the metal plate exposing section and grooves that run from an inside to an outside of the second outer frame section; coating a pre-mold resin on the holes and the grooves, and heating the pre-mold resin under pressure using a flat-bed press to form a resin layer; and etching the first surface to form the semiconductor element mounting se

Abstract: A method of making a semiconductor chip assembly includes providing a metal plate, providing a ceramic block in the metal plate, providing an insulative material in the metal plate, wherein the metal plate includes a base and a terminal, then providing a conductive layer on the base and the ceramic block, providing a conductive trace that includes a pad, the terminal and a selected portion of the conductive layer, then mounting a semiconductor device on the ceramic block, wherein a heat spreader includes the base and the ceramic block, electrically connecting the semiconductor device to the conductive trace and thermally connecting the semiconductor device to the heat spreader.

Abstract: A method of manufacture of a semiconductor packaging system includes: providing a substrate; mounting a semiconductor chip to the substrate; mounting a pillar ball having a ball height electrically connected to the substrate; mounting an interposer above the semiconductor chip and electrically connected to the pillar ball; and wherein: mounting the interposer or mounting the substrate includes connecting the pillar ball to a pillar base having a base height substantially less than the ball height of the pillar ball and the pillar base having vertical sides not covered by the pillar ball.

Abstract: An integrated circuit package on package system includes: providing a lead having a wire-bonded die with a bond wire connected thereto; mounting a fan-in interposer over the wire-bonded die and the bond wire; connecting the fan-in interposer to the lead with the bond wires; and encapsulating the wire-bonded die, bond wires, and the fan-in interposer with an encapsulation leaving a portion of the fan-in interposer exposed.

Abstract: Disclosed are systems and methods for improving the thermal performance of integrated circuit packages. Aspects of the present invention include improved thermal package structures and methods for producing the same through the application of one or more thermal spreaders in the package. In embodiments, a thermal spreader is incorporated in a semiconductor chip package between a semiconductor die and its die pad. By including a thermal spreader in an IC package, the package can handle higher levels of power while maintaining approximately the same temperature of the package or can reduce the temperature of the package when operating at the same power level, as compared to a package without a thermal spreader.

Abstract: A fabrication method of a semiconductor package structure includes: patterning a metal plate having first and second surfaces; forming a dielectric layer on the metal plate; forming a metal layer on the first surface and the dielectric layer; forming metal pads on the second surface, the metal layer having a die pad and traces each having a bond pad; mounting a semiconductor chip on the die pad, followed by connecting electrically the semiconductor chip to the bond pads through bonding wires; forming an encapsulant to cover the semiconductor chip and the metal layer; removing portions of the metal plate not covered by the metal pads so as to form metal pillars; and performing a singulation process. The fabrication method is characterized by disposing traces with bond pads close to the die pad to shorten the bonding wires and forming metal pillars protruding from the dielectric layer to avoid solder bridging.

Abstract: A package structure having an embedded electronic component includes: a carrier having a cavity penetrating therethrough; a semiconductor chip received in the cavity and having solder bumps disposed thereon; a dielectric layer formed on the carrier and the semiconductor chip so as to encapsulate the solder bumps; a wiring layer formed on the dielectric layer; an insulating protection layer formed on the dielectric layer and the wiring layer; and a solder material formed in the dielectric layer and the insulating protection layer for electrically connecting the wiring layer and the solder bumps, thereby shortening the signal transmission path between the semiconductor chip and the carrier to avoid signal losses.

Abstract: A semiconductor device entirely having a small height, which performs a fan-out operation for input/output signals and forms a short electrical path is provided. The semiconductor device includes a first semiconductor die having a first surface, a second surface opposed to the first surface, a third surface connecting the first and second surfaces to each other, a first bond pad disposed on the first surface, and a first through electrode passing between the first surface and second surface and electrically connected to the first bond pad. A first redistribution part is disposed under the second surface and includes a first redistribution layer electrically connected to the first through electrode. A second redistribution part is disposed over the first surface and includes a second redistribution layer electrically connected to the first bond pad.

Abstract: A package structure of a compound semiconductor device comprises a thin film substrate, a die, at least one metal wire and a transparent encapsulation material. The thin film substrate comprises a first conductive film, a second conductive film, and an insulating dielectric material. The die is mounted on the surface of the first conductive film, and is electrically connected to the first conductive film and the second conductive film through the metal wire. The transparent encapsulation material overlays the first conductive film, second conductive film, and die. The surfaces of the first conductive film and second conductive film which is opposite the transparent encapsulation material act as electrodes. The insulating dielectric material is between the first conductive film and second conductive film.

Abstract: Provided is a method of producing a semiconductor device having a structure wherein a semiconductor chip 3 is mounted on a wiring circuit substrate 2 and sealed with a resin. A wiring circuit substrate 2 having a connecting conductor portion that can be connected to an electrode of the chip is formed on a metal support layer 1 in a way such that the substrate can be separated from the metal support layer, the chip 3 is mounted on the wiring circuit substrate 2, a sheet-shaped resin composition T is placed on the chip and heated on the chip to seal the chip, and the metal support layer is separated and divided to obtain individual semiconductor devices.

Abstract: A power semiconductor device in which transfer molding resin seals: a metallic circuit substrate; a power semiconductor element joined to a wiring pattern; and a side surface of a cylindrical external terminal communication section provided on the wiring pattern and to which an external terminal can be inserted and connected. The cylindrical external terminal communication section is substantially perpendicular to a surface on which the wiring pattern is formed. An outer surface of a metal plate of the metallic circuit substrate and a top portion of the cylindrical external terminal communication section are exposed from the transfer molding resin. The transfer molding resin is not present within the cylindrical external terminal communication section.

Abstract: The method for producing a resin package according to the present invention includes a step of forming a copper oxide layer by oxidizing the surface of a lead frame in which at least the surface is made of copper, and a step of forming a resin package main unit by allowing a resin to adhere to the copper oxide layer on the lead frame surface by resin molding for package, and then removing a predetermined area of the copper oxide layer with an acidic solution.

Abstract: Methods and structures related to packaging a chip are disclosed. In one embodiment, a chip package structure includes: (i) a chip having a plurality of first and second contact pads thereon; (ii) a lead frame having a plurality of pins for external connection to the package structure, where the chip is disposed on the lead frame; (iii) a plurality of first bonding wires for connecting the first contact pads to the lead frame; and (iv) a plurality of second bonding wires for connecting the second contact pads to the plurality of pins on the lead frame.

Abstract: A method of packaging an electronic device includes providing a patterned dielectric layer with an area sized to receive a first die, and another area sized to receive a second die, placing the first and second dies within the first and second areas, encapsulating the dies with an encapsulating material that has a different composition from the dielectric layer, forming a first signal line between the dies, forming a second signal line to the first die, and forming an additional signal line to the first die. The dielectric layer is disposed between the first signal line and the encapsulating material, the electronic device transmits a signal in an approximate range of 1 GHz to 100 GHz along the second signal line, and a signal that does not exceed approximately 900 MHz along the additional signal line.

Abstract: The injection molding system comprises a substrate, an inner cover, a molding tool, and a bottom plate. The substrate is used to locate at least one semiconductor device under molding and the inner cover with at least one first injection via, cavity and runner placed over the substrate. In addition, the molding tool includes at least one second injecting via aligned with the runner and the bottom plate is placed under the substrate. Furthermore, a filling material is filled into the cavity and runner of the inner cover during molding. In order to avoid overflowing the filling material, the system further comprises an O-ring placed between the molding tool and the inner cover. The inner radius of the O-ring corresponds with the inner radius of the injection via and is aligned with it.

Abstract: A semiconductor die has first and second discrete semiconductor components mounted over a plurality of wettable contact pads formed on a carrier. Conductive pillars are formed over the wettable contact pads. A semiconductor die is mounted to the conductive pillars over the first discrete components. The conductive pillars provide vertical stand-off of the semiconductor die as headroom for the first discrete components. The second discrete components are disposed outside a footprint of the semiconductor die. Conductive TSV can be formed through the semiconductor die. An encapsulant is deposited over the semiconductor die and first and second discrete components. The wettable contact pads reduce die and discrete component shifting during encapsulation. A portion of a back surface of the semiconductor die is removed to reduce package thickness. An interconnect structure is formed over the encapsulant and semiconductor die. Third discrete semiconductor components can be mounted over the semiconductor die.

Abstract: The present invention provide a heat dissipation structure on the active surface of the die to increase the performance of the heat conduction in longitude direction of the semiconductor package device, so that the heat dissipating performance can be improved when the semiconductor package device is associated with the exterior heat dissipation mechanism.

Abstract: An integrated circuit assembly includes a panel including an semiconductor device at least partially surrounded by an encapsulant. A panel upper surface and a device active surface are substantially coplanar. The assembly further includes one or more interconnect layers overlying the panel upper surface. Each of the interconnect layers includes an insulating film having contacts formed therein an interconnect metallization formed thereon. A lower surface of the panel is substantially coplanar with either a backside of the device or a lower surface of a thermally and electrically conductive slab that has an upper surface in thermal contact with the device backside. The assembly may also include a set of panel vias. The panel vias are thermally and electrically conductive conduits extending through the panel between the interconnect layer and suitable for bonding with a land grid array (LGA) or other contact structure of an underlying circuit board.

Abstract: A semiconductor device has a thermally conductive layer with a plurality of openings formed over a temporary carrier. The thermally conductive layer includes electrically non-conductive material. A semiconductor die has a plurality of bumps formed over contact pads on the die. The semiconductor die is mounted over the thermally conductive layer so that the bumps are disposed at least partially within the openings in the thermally conductive layer. An encapsulant is deposited over the die and thermally conductive layer. The temporary carrier is removed to expose the bumps. A first interconnect structure is formed over the encapsulant, semiconductor die, and bumps. The bumps are electrically connected to the first interconnect structure. A heat sink or shielding layer can be formed over the semiconductor die. A second interconnect structure can be formed over the encapsulant and electrically connected to the first interconnect structure through conductive vias formed in the encapsulant.

Abstract: A method comprises forming semiconductor flip chip interconnects where the flip chip comprises a wafer and a substrate having electrical connecting pads and electrically conductive posts operatively associated with the pads and extending away from the pads to terminate in distal ends. Solder bumping the distal ends by injection molding solder onto the distal ends produces a solder bumped substrate. Another embodiment comprises providing the substrate having the posts on the pads with a mask having a plurality of through hole reservoirs and aligning the reservoirs in the mask to be substantially concentric with the distal ends. This is followed by injecting liquid solder into the reservoirs to provide a volume of liquid solder on the distal ends, cooling the liquid solder in the reservoirs to solidify the solder, removing the mask to expose the solidified solder after the cooling and thereby provide a solder bumped substrate.

Abstract: An apparatus and a method for packaging semiconductor devices. The apparatus includes a substrate strip component of a leadless three-dimensional stackable semiconductor package having mounting contacts on, for example, four peripheral edges. The substrate strip may either be fabricated for mounting a single electrical component (e.g., an integrated circuit die) or a plurality of substrate strips may be laid out in an X-Y matrix pattern which may later be singulated into individual package strip for leadless packages. Three-dimensional stacking is achieved by a bonding area on an uppermost portion of the sidewall. The sidewall of the strip is high enough to enclose an encapsulant covering a later mounted integrated circuit die and associated bonding wires.

Abstract: The present invention includes a temporary fixing step of temporarily fixing a semiconductor element on an adherend interposing an adhesive sheet therebetween, a wire-bonding step of bonding wires to the semiconductor element, and a step of sealing the semiconductor element with a sealing resin, and in which the loss elastic modulus of the adhesive sheet at 175° C. is 2000 Pa or more.