Abstract: There are disclosed herein various implementations of improved wafer level semiconductor packages. One exemplary implementation comprises forming a post-fabrication redistribution layer (post-Fab RDL) between first and second dielectric layers affixed over a surface of a wafer, and forming a window for receiving an electrical contact body in the second dielectric layer, the window exposing the post-Fab RDL. At least one of the first and second dielectric layers is a pre-formed dielectric layer, which may be affixed over the surface of the wafer using a lamination process. In one implementation, the window is formed using a direct laser ablation process.

Abstract: Improved fin field effect transistor (FinFET) devices and methods for the fabrication thereof are provided. In one aspect, a method for fabricating a field effect transistor device comprises the following steps. A substrate is provided having a silicon layer thereon. A fin lithography hardmask is patterned on the silicon layer. A dummy gate structure is placed over a central portion of the fin lithography hardmask. A filler layer is deposited around the dummy gate structure. The dummy gate structure is removed to reveal a trench in the filler layer, centered over the central portion of the fin lithography hardmask, that distinguishes a fin region of the device from source and drain regions of the device. The fin lithography hardmask in the fin region is used to etch a plurality of fins in the silicon layer. The trench is filled with a gate material to form a gate stack over the fins.

Abstract: A manufacturing method of a substrate for a semiconductor package includes a resist layer forming step to form a resist layer on a surface of a conductive substrate; an exposure step to expose the resist layer using a glass mask with a mask pattern including a transmission area, a light shielding area, and an intermediate transmission area, wherein transmittance of the intermediate transmission area is lower than that of the transmission area and is higher than that of the light shielding area; a development step to form a resist pattern including a hollow with a side shape including a slope part decreasing in hollow circumference as the hollow circumference approaches the substrate; and a plating step to plate on an exposed area to form a metal layer with a side shape including a slope part decreasing in circumference as the circumference approaches the substrate.

Abstract: Semiconductor packages and related methods. The semiconductor package includes a substrate, a semiconductor chip, a package body, a recess and a conductive layer. The substrate includes a grounding element. The semiconductor chip is disposed on the substrate and has a lateral surface and an upper surface. The package body encapsulates the lateral surface of the semiconductor chip. The recess is formed in the package body and exposes the upper surface of the semiconductor chip. The conductive layer covers an outer surface of the package body, the grounding element and the upper surface of the semiconductor chip exposed by the recess to provide both thermal dissipation and EMI shielding for the semiconductor chip.

Abstract: A semiconductor package including a package substrate; a semiconductor chip on the package substrate; a first via contact on the package substrate; a second via contact on the semiconductor chip; a metal wiring, which is arranged on the first via contact and the second via contact and interconnects the first via contact and the second via contact; a first encapsulating material which is arranged between the metal wiring and the package substrate and encapsulates the semiconductor chip, the first via contact, and the second via contact; and a second encapsulating material which encapsulates the first encapsulating material and the metal wiring.

Abstract: A package structure includes a metal sheet having perforations; a semiconductor chip having an active surface and an opposite inactive surface, wherein the active surface has electrode pads thereon, conductive bumps are disposed on the electrode pads, the semiconductor chip is combined with the metal sheet via the inactive surface thereof, a protective buffer layer is formed on the active surface to cover the conductive bumps, and the perforations are arranged around a periphery of the inactive surface of the semiconductor chip; an encapsulant formed on the metal sheet and in the perforations, for encapsulating the semiconductor chip and exposing the protective buffer layer; and a circuit fan-out layer formed on the encapsulant and the protective buffer layer and having conductive vias penetrating the protective buffer layer and electrically connecting to the conductive bumps. A method of fabricating the package structure and a package-on-package device including the package structure are also provided.

Abstract: In a method for producing a power semiconductor arrangement, an insulation carrier with a top side, a metallization, and a contact pin with a first end are provided. The metallization is attached to the top side and a target section of the metallization is determined. After the metallization is attached to the top side of the insulation carrier, the first end of the contact pin is pressed into the target section such that the first end is inserted in the target section. Thereby, an interference fit and an electrical connection are established between the first end of the contact pin and the target section of the metallization.

Abstract: The present technology is directed toward semiconductors packaged by electrically coupling a plurality of die to an upper and lower lead frame. The opposite edges of each corresponding set of leads in the upper lead frame are bent. The leads in the upper lead frame are electrically coupled between respective contacts on respective die and respective lower portion of the leads in the lower lead frame. The bent opposite edges of each corresponding set of leads of the upper lead frame support the upper lead frame before encapsulation, for achieving a desired position of the plurality of die between the leads of the upper and lower lead frames in the packaged semiconductor. After the encapsulated die are separated, the upper leads have an L-shape and electrically couple die contacts on upper side of the die to leads on the lower side of the die so that the package contacts are on the same side of the semiconductor package.

Abstract: A semiconductor package includes a first semiconductor chip, a second semiconductor chip and a sealing member. The first semiconductor chip includes a substrate having a first surface and a second surface opposite to the first surface and having an opening that extends in a predetermined depth from the second surface, and a plurality of through electrodes extending in a thickness direction from the first surface, end portions of the through electrodes being exposed through a bottom surface of the opening. The second semiconductor chip is received in the opening and mounted on the bottom surface of the opening. The sealing member covers the second semiconductor chip in the opening.

Abstract: A semiconductor device has an interposer mounted over a carrier. The interposer includes TSV formed either prior to or after mounting to the carrier. An opening is formed in the interposer. The interposer can have two-level stepped portions with a first vertical conduction path through a first stepped portion and second vertical conduction path through a second stepped portion. A first and second semiconductor die are mounted over the interposer. The second die is disposed within the opening of the interposer. A discrete semiconductor component can be mounted over the interposer. A conductive via can be formed through the second die or encapsulant. An encapsulant is deposited over the first and second die and interposer. A portion of the interposer can be removed to that the encapsulant forms around a side of the semiconductor device. An interconnect structure is formed over the interposer and second die.

Abstract: Terminals (2b, 2c) are divided into two along a common boundary, coatings (10, 11) most suitable for two conductive bonding materials (5, 6) to be used are exposed on the terminals (2b, 2c), the most suitable one of the coatings (10, 11) is selected, and the corresponding conductive bonding material (5, 6) is bonded onto the coating. Thus it is possible to improve the reliability of bonding and easily reduce a bonding resistance while suppressing a decrease in the reliability of a semiconductor element 3.

Abstract: The inventive concept provides semiconductor packages and methods of forming the same. The semiconductor package includes a buffer layer covering at least one sidewall of the semiconductor chip. The buffer layer is covered by a molding layer. Thus, reliability of the semiconductor package may be improved.

Abstract: A semiconductor package having an embedded die and solid vertical interconnections, such as stud bump interconnections, for increased integration in the direction of the z-axis (i.e., in a direction normal to the circuit side of the die). The semiconductor package can include a die mounted in a face-up configuration (similar to a wire bond package) or in a face-down or flip chip configuration.

Abstract: An improved semiconductor device package is manufactured by attaching semiconductor chips (130) on an insulating substrate (101) having contact pads (103). A mold is provided, which has a top portion (210) with metal protrusions (202) at locations matching the pad locations. The protrusions are shaped as truncated cones. The substrate and the chips are loaded onto the bottom mold portion (310); the mold is closed by clamping the top portion onto the bottom portion so that the protrusions approach the contact pads. Encapsulation compound is introduced into the cavity and the protrusions create apertures through the encapsulation compound towards the pad locations.

Abstract: A semiconductor package structure comprises a substrate, a die bonded to the substrate, and one or more stud bump structures connecting the die to the substrate, wherein each of the stud bump structures having a stud bump and a solder ball encapsulating the stud bump to enhance thermal dissipation and reduce high stress concentrations in the semiconductor package structure.

Abstract: A substrate and a method of making thereof are disclosed. The substrate comprises an electrically conductive leadframe, the leadframe having a plurality of lands on a first side of the leadframe with a first recessed portion between the lands, and a plurality of routing leads on an opposing second side of the leadframe with a second recessed portion between the routing leads. The substrate also comprises a first bonding compound filling the first recessed portion. In one embodiment, the substrate also comprises a support material attached to the first bonding compound for holding the leadframe together. In another embodiment, the substrate comprises a second bonding compound filling the second recessed portion.

Abstract: The reliability of a semiconductor device is enhanced. A first lead frame, a first semiconductor chip, a second lead frame, and a second semiconductor chip are stacked over an assembly jig in this order with solder in between and solder reflow processing is carried out to fabricate their assembly. Thereafter, this assembly is sandwiched between first and second molding dies to form an encapsulation resin portion. The upper surface of the second die is provided with steps. At a molding step, the second lead frame is clamped between the first and second dies at a position higher than the first lead frame; and a third lead frame is clamped between the first and second dies at a higher position. The assembly jig is provided with steps at the same positions as those of the steps in the upper surface of the second die in positions corresponding to those of the same.

Abstract: Various exemplary embodiments provide components, devices, and methods of semiconductor packaging. The disclosed packaging component can include a mold material disposed around a lead frame and at least an integrated circuit (IC), wherein the IC is electrically connected with one side of the lead frame. The opposite side of the lead frame including, for example, lead segments, can be exposed from the mold material. A variety of other components, devices, and packages can then be assembled, e.g., over the disclosed packaging component, through the exposed regions so as to improve packaging densities.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a leadframe having a mounting region; applying a mounting structure in the mounting region; mounting an integrated circuit die on the mounting structure; forming an encapsulation on the integrated circuit die and having an encapsulation cavity, the encapsulation cavity shaped by the mounting structure; forming a lead having a lead protrusion from the leadframe, the lead protrusion below a horizontal plane of the integrated circuit die; and removing the mounting structure for exposing the integrated circuit die.

Abstract: A package includes a first plated area, a second plated area, a die attached to the first plated area, and a bond coupling the die to the second plated area. The package further includes a molding encapsulating the die, the bond, and the top surfaces of the first and second plated areas, such that the bottom surfaces of the first and second plated areas are exposed exterior to the package. Additional embodiments include a method of making the package.

Abstract: A power semiconductor package has an ultra thin chip with front side molding to reduce substrate resistance; a lead frame unit with grooves located on both side leads provides precise positioning for connecting numerous bridge-shaped metal clips to the front side of the side leads. The bridge-shaped metal clips are provided with bridge structure and half or fully etched through holes for relieving superfluous solder during manufacturing process.

Abstract: A method for manufacturing an optoelectronic apparatus includes attaching bottom surfaces of first and second packaged optoelectronic semiconductor devices (POSDs) to a carrier substrate (e.g., a tape) so that there is a space between the first and second POSDs. An opaque molding compound is molded around portions of the first and second POSDs attached to the carrier substrate, so that peripheral surfaces of the first POSD and the second POSD are surrounded by the opaque molding compound, the space between the first and second POSDs is filled with the opaque molding compound, and the first and second POSDs are attached to one another by the opaque molding compound. The carrier substrate is thereafter removed so that electrical contacts on the bottom surfaces of the first and second POSDs are exposed. A window for each of the POSDs is formed during the molding process or thereafter.

Abstract: A semiconductor device has a substrate, first passivation layer formed over the substrate, and integrated passive device formed over the substrate. The integrated passive device can include an inductor, capacitor, and resistor. A second passivation layer is formed over the integrated passive device. System components are mounted to the second passivation layer and electrically connect to the second conductive layer. A mold compound is formed over the integrated passive device. A coefficient of thermal expansion of the mold compound is approximately equal to a coefficient of thermal expansion of the system component. The substrate is removed. An opening is etched into the first passivation layer and solder bumps are deposited over the opening in the first passivation layer to electrically connect to the integrated passive device. A metal layer can be formed over the molding compound or first passivation layer for shielding.

Abstract: An electromagnetic component module includes: a molding resin provided so as to cover electronic components mounted on a substrate and a surface of the substrate; and a conductive shield formed so as to further cover the molding resin. The conductive shield includes a first filler and a second filler which are different from each other and the conductive shield is connected to ground wires exposed on lateral surfaces of the substrate. The average particle diameter of the first filler is ½ or less of the thickness of the ground wires and the second filler forms a metallic bond in the temperature range of 250 degrees Celsius or lower.

Abstract: A manufacturing method of a package structure is provided. A seed layer is formed on a upper surface of a metal substrate. A patterned dry film layer is formed on a lower surface of the metal substrate and the seed layer. A portion of the seed layer is exposed by the patterned dry film layer. The patterned dry film layer is used as an electroplating mask to electroplate a circuit layer on the portion of the seed layer exposed by the patterned dry film layer. A chip is bonded to and electrically connected to the circuit layer. A molding compound is formed on the metal substrate. The molding compound encapsulates the chip, the circuit layer and the portion of the seed layer. A portion of the metal substrate and a portion of the seed layer are removed so as to expose a portion of the molding compound.

Abstract: There is provided a resin dispensing apparatus for a light emitting device package and a method of manufacturing a light emitting device package using the same. The resin dispensing apparatus includes a resin dispensing part including a resin storage portion filled with a resin therein and a resin discharge portion combined with the resin storage portion and discharging the resin therefrom; a supporting part having a light emitting device package disposed on an upper surface thereof and electrically connected to the light emitting device package; a voltage applying part having both terminals respectively connected to the resin dispensing part and the supporting part to apply a voltage thereto; and a sensing part electrically connected to the resin dispensing part and the supporting part individually and sensing a contact between the resin dispensing part and the light emitting device package with an electrical signal.

Abstract: Disclosed is a granular resin composition for encapsulating a semiconductor used for a semiconductor device obtained by encapsulating a semiconductor element by compression molding, satisfying the following requirements (a) to (c) on condition that ion viscosity is measured with a dielectric analyzer under a measurement temperature of 175° C. and a measurement frequency of 100 10 Hz: (a) the time from the initiation of the measurement until a decrease of the ion viscosity to the lowest ion viscosity is 20 seconds or shorter; (b) the lowest ion viscosity value is not more than 6.5; and (c) the time interval between the time from the initiation of the measurement until a decrease of the ion viscosity to the lowest ion viscosity and the time from the initiation of the measurement until the ion viscosity reaching 90% of an ion viscosity value measured at 300 seconds is 10 seconds or longer.

Abstract: A circuit package is provided, the circuit package including: an electronic circuit; a metal block next to the electronic circuit; encapsulation material between the electronic circuit and the metal block; a first metal layer structure electrically contacted to at least one first contact on a first side of the electronic circuit; a second metal layer structure electrically contacted to at least one second contact on a second side of the electronic circuit, wherein the second side is opposite to the first side; wherein the metal block is electrically contacted to the first metal layer structure and to the second metal layer structure by means of an electrically conductive medium; and wherein the electrically conductive medium includes a material different from the material of the first and second metal layer structures or has a material structure different from the material of the first and second metal layer structures.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a conductive trace having a terminal end and a circuit end; forming a terminal on the terminal end; connecting an integrated circuit die directly on the circuit end of the conductive trace, the integrated circuit die laterally offset from the terminal, the active side of the integrated circuit die facing the circuit end; and forming an insulation layer on the terminal and the integrated circuit die, the integrated circuit die covered by the insulation layer.

Abstract: A semiconductor device has a carrier with a die attach area. A semiconductor die is mounted to the die attach area with a back surface opposite the carrier. A modular interconnect unit is mounted over the carrier and around or in a peripheral region around the semiconductor die such that the modular interconnect unit is offset from the back surface of the semiconductor die. An encapsulant is deposited over the carrier, semiconductor die, and modular interconnect unit. A first portion of the encapsulant is removed to expose the semiconductor die and a second portion is removed to expose the modular interconnect unit. The carrier is removed. An interconnect structure is formed over the semiconductor die and modular interconnect unit. The modular interconnect unit includes a vertical interconnect structures or bumps through the semiconductor device. The modular interconnect unit forms part of an interlocking pattern around the semiconductor die.

Abstract: A semiconductor device has a semiconductor die with an encapsulant deposited over the semiconductor die. A first insulating layer having high tensile strength and elongation is formed over the semiconductor die and encapsulant. A first portion of the first insulating layer is removed by a first laser direct ablation to form a plurality of openings in the first insulating layer. The openings extend partially through the first insulating layer or into the encapsulant. A second portion of the first insulating layer is removed by a second laser direct ablation to form a plurality of trenches in the first insulating layer. A conductive layer is formed in the openings and trenches of the first insulating layer. A second insulating layer is formed over the conductive layer. A portion of the second insulating layer is removed by a third laser direct ablation. Bumps are formed over the conductive layer.

Abstract: Stacked microelectronic devices and methods for manufacturing such devices are disclosed herein. In one embodiment, a stacked microelectronic device assembly can include a first known good packaged microelectronic device including a first interposer substrate. A first die and a first through-casing interconnects are electrically coupled to the first interposer substrate. A first casing at least partially encapsulates the first device such that a portion of each first interconnect is accessible at a top portion of the first casing. A second known good packaged microelectronic device is coupled to the first device in a stacked configuration. The second device can include a second interposer substrate having a plurality of second interposer pads and a second die electrically coupled to the second interposer substrate. The exposed portions of the first interconnects are electrically coupled to corresponding second interposer pads.

Abstract: A semiconductor device has a carrier with a die attach area. A semiconductor die is mounted to the die attach area with a back surface opposite the carrier. A modular interconnect unit is mounted over the carrier and around or in a peripheral region around the semiconductor die such that the modular interconnect unit is offset from the back surface of the semiconductor die. An encapsulant is deposited over the carrier, semiconductor die, and modular interconnect unit. A first portion of the encapsulant is removed to expose the semiconductor die and a second portion is removed to expose the modular interconnect unit. The carrier is removed. An interconnect structure is formed over the semiconductor die and modular interconnect unit. The modular interconnect unit includes a vertical interconnect structures or bumps through the semiconductor device. The modular interconnect unit forms part of an interlocking pattern around the semiconductor die.

Abstract: Integration of sensor chips with integrated circuit (IC) chips. At least a first sensor chip including a first sensor is affixed to a first side of an interposer to hermitically seal the first sensor within a first cavity. An IC chip is affixed to a second side of the interposer opposite the first sensor, the IC chip is electrically coupled to the first sensor by a through via in the interposer. In embodiments, the first sensor includes a MEMS device and the IC chip comprises a circuit to amplify a signal from the MEMS device. The interposer may be made of glass, with the first sensor chip and the IC chip flip-chip bonded to the interposer by compression or solder. Lateral interconnect traces provide I/O between the devices on the interposer and/or a PCB upon which the interpose is affixed.

Abstract: An exposed die overmolded flip chip package includes a substrate. A die is flip chip mounted to an upper surface of the substrate. The package further includes a mold cap filling a apace between an active surface of the die and the upper surface of the substrate. The mold cap includes a principal surface, sidewalls extending from the upper surface of the substrate to the principal surfaces, an annular surface coplanar with the inactive surface of the die and extending outward from a peripheral edge of the inactive surface of the die, and protruding surfaces extending between the principal surface and the annular surface. The mold cap does not cover the inactive surface of the die such that heat transfer from the die to the ambient environment is maximized and the package thickness is minimized.

Abstract: In one embodiment, a method of forming a semiconductor package includes placing a first die and a second die over a carrier. At least one of the first and the second dies are covered with an encapsulation material to form an encapsulant having a top surface and an opposite bottom surface. The encapsulant is thinned from the bottom surface to expose a first surface of the first die without exposing the second die. The exposed first surface of the first die is selectively etched to expose a second surface of the first die. A back side conductive layer is formed so as to contact the first surface. The second die is separated from the back side conductive layer by a first portion of the encapsulant.

Abstract: An apparatus and process for self-aligning components for forming an embedded die package is disclosed. The process includes providing a planar printed wire board (PWB) substrate having registration pads and a component having contact pads and spaced alignment pads, wherein the alignment pads each have a solder cap, placing the component on the substrate such that the alignment pads are in coarse alignment with the registration pads, applying heat to the alignment and registration pads to reflow the solder caps to precisely align the pads; and reducing the temperature below the reflow temperature. The process further includes applying a backside outer layer lamination, forming first vias, forming redistribution conductors on an opposite surface of the substrate connecting to the vias, and applying a front side outer layer lamination over the opposite surface of the substrate, all at temperatures below the reflow temperature.

Abstract: A method for manufacturing a device package may include constructing a spacer element coupled with a surface of a semiconductor die unit, where the spacer element is configured to create a gap between the semiconductor die unit and a surface of a carrier, and encapsulating the semiconductor die unit within a mold compound, where the encapsulating includes introducing the mold compound into the gap.

Abstract: A manufacturing method of a semiconductor element substrate including: forming a first photoresist pattern on a first surface of a metallic plate, to form a semiconductor element mounting part, a semiconductor element electrode connection terminal, a wiring, an outer frame part, and a slit; forming a second photoresist pattern on the second surface of the metallic plate; forming the slit by half etching to connect the metallic chip with a four corners of the outer frame part; forming a plurality of concaved parts on the second surface of the metallic plate; forming a resin layer by injecting a resin to the plurality of concaved parts; and etching the first surface of the metallic plate and forming the semiconductor element electrode connection terminal and the outer frame.

Abstract: An integrated circuit package system is provided including an integrated circuit package system including an integrated circuit and a lead frame. The lead frame has a multi-surface die attach pad and the integrated circuit is mounted to the multi-surface die attach pad.

Abstract: An integrated circuit 15 is placed onto a lead frame 101 having lead fingers 109 of substantially constant thickness along their length. Wires are formed from the lead fingers 109 to corresponding electrical contacts the integrated circuit. Following the wire bonding process, the thickness of the tips of the lead fingers 109 is reduced by a laser process, to form tips of reduced thickness desirable for a subsequent moulding operation. Thus, at the time of the wire bonding the tips of the fingers 109 need not have a gap beneath them, so that more secure wire bonds to the lead fingers 109 can be formed.

Abstract: In one embodiment, a method of forming a semiconductor package includes applying a film layer having through openings over a carrier and attaching a back side of a semiconductor chip to the film layer. The semiconductor chip has contacts on a front side. The method includes using a first common deposition and patterning step to form a conductive material within the openings. The conductive material contacts the contacts of the semiconductor chip. A reconfigured wafer is formed by encapsulating the semiconductor chip, the film layer, and the conductive material in an encapsulant using a second common deposition and patterning step. The reconfigured wafer is singulated to form a plurality of packages.

Abstract: The present invention include a semiconductor device and a method therefor, the method includes disposing a sheet-shaped resin at a side opposite to the chip mounting portion mounting semiconductor chips to be mounted on the chip mounting portion, and forming a resin sealing portion between the sheet-shaped resin and the chip mounting portion, to seal the semiconductor chips. According to an aspect of the present invention, it is possible to provide a semiconductor device and a fabrication method therefor, by which it is possible to reduce the size of the package and to prevent the generation of an unfilled portion in a resin sealing portion or a filler-removed portion or to prevent the exposure of wire from the resin sealing portion.

Abstract: A process for increasing the adhesion of a polymeric material to a metal surface, the process comprising contacting the metal surface with an adhesion promoting composition comprising: 1) an oxidizer; 2) an inorganic acid; 3) a corrosion inhibitor; and 4) an organic phosphonate; and thereafter b) bonding the polymeric material to the metal surface. The organic phosphonate aids in stabilizing the oxidizer and organic components present in the bath and prevents decomposition of the components, thereby increasing the working life of the bath, especially when used with copper alloys having a high iron content.

Abstract: Disclosed are a semiconductor device capable of efficiently radiating heat of a semiconductor die and a method of fabricating the same. The semiconductor device efficiently radiates the heat by preventing an encapsulant from reaching the semiconductor die by an encapsulant dam so that an upper surface of the semiconductor die is exposed out of the encapsulant. In addition, the semiconductor device is configured to expose a pre-solder ball or a conductive pattern of a substrate through a via of the encapsulant. Therefore, electrical connection between the pre-solder ball and a solder ball of another semiconductor device stacked thereon is easily achieved.

Abstract: Provided are a semiconductor package of a semiconductor chip, a semiconductor module, an electronic system, and methods of manufacturing the same. The method includes mounting a semiconductor chip on a package substrate, forming a molding member on the semiconductor chip, forming via holes penetrating the molding member to expose a portion of a top surface of the semiconductor chip, the via holes being arranged in a lattice shape in a plan view, and forming thermally conductive via plugs in the via holes.

Abstract: An LED package with an extended top electrode and an extended bottom electrode is made from a single metal sheet, one manufacturing process embodiment includes: preparing a piece of single metal sheet, forming a first metal and a coplanar second metal, mounting an LED on an inner end of the first metal, wire-bonding top electrode to an inner end of the second metal, encapsulating at least the LED and the bonding wire with a protection glue, bending an outer end of the first metal upward twice 90 degrees to form a top flat as an extended top electrode of the package, and bending an outer end of the second metal downward twice 90 degrees to form a bottom flat as an extended bottom electrode of the package.

Abstract: The described embodiments of mechanisms of forming connectors for package on package enable smaller connectors with finer pitch, which allow smaller package size and additional connections. The conductive elements on one package are partially embedded in the molding compound of the package to bond with contacts or metal pads on another package. By embedding the conductive elements, the conductive elements may be made smaller and there are is gaps between the conductive elements and the molding compound. A pitch of the connectors can be determined by adding a space margin to a maximum width of the connectors. Various types of contacts on the other package can be bonded to the conductive elements.

Abstract: Provided is an underfill material which enables a semiconductor chip to be mounted at a low pressure, and a method for manufacturing a semiconductor device by using the underfill material. The method comprises: a semiconductor chip mounting step configured to mount a semiconductor chip having a solder bump on a substrate via an underfill film including a film forming resin having a weight average molecular weight of not more than 30000 g/mol and a molecular weight distribution of not more than 2.0, an epoxy resin, and an epoxy curing agent; and a reflow step configured to solder-bond the semiconductor chip and the substrate by a reflow furnace. The film forming resin of the underfill material has a weight average molecular weight of not more than 30000 g/mol and a molecular weight distribution of not more than 2.0, and accordingly, the viscosity at the time of heat melting can be reduced, and a semiconductor chip can be mounted at a low pressure.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; mounting a base integrated circuit over the base substrate; attaching a lead to the base integrated circuit and the base substrate, the lead having a lead attachment portion over the base integrated circuit; and forming a base encapsulation over the lead, the base encapsulation having a cavity exposing the lead attachment portion.