Abstract: An integrated electronic device includes a substrate, passive components, pads for external connection, and three-dimensional wiring. The passive components includes a multi-stage coil inductor provided on the substrate. The multi-stage coil inductor has a plurality of coils disposed in several layers. Mutually adjacent coil wires are spaced-apart from each other. The three-dimensional wiring includes a first wiring portion which extends on the substrate, a second wiring portion which extends off the substrate but along the substrate, and a third wiring portion connecting with the first wiring portion and the second wiring portion.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a package paddle; forming a lead adjacent the package paddle, the lead having a hole in a lead body top side and a lead ridge protruding from a lead non-horizontal side; mounting an integrated circuit over the package paddle; connecting an electrical connector to the lead and the integrated circuit; and forming a fill layer within the hole.

Abstract: A semiconductor device is made by mounting a prefabricated heat spreader frame over a temporary substrate. The heat spreader frame includes vertical bodies over a flat plate. A semiconductor die is mounted to the heat spreader frame for thermal dissipation. An encapsulant is deposited around the vertical bodies and semiconductor die while leaving contact pads on the semiconductor die exposed. The encapsulant can be deposited using a wafer level direct/top gate molding process or wafer level film assist molding process. An interconnect structure is formed over the semiconductor die. The interconnect structure includes a first conductive layer formed over the semiconductor die, an insulating layer formed over the first conductive layer, and a second conductive layer formed over the first conductive layer and insulating layer. The temporary substrate is removed, dicing tape is applied to the heat spreader frame, and the semiconductor die is singulated.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a peripheral lead having a peripheral lead bottom side, a peripheral lead top side, a peripheral lead non-horizontal side, and a peripheral lead horizontal ridge protruding from the peripheral lead non-horizontal side; forming a first top distribution layer on the peripheral lead top side; connecting an integrated circuit to the first top distribution layer; and applying an insulation layer directly on a distribution layer bottom extent of the first top distribution layer and a peripheral lead ridge lower side of the peripheral lead horizontal ridge with a cavity in the portion of the insulation layer directly below the integrated circuit.

Abstract: A manufacturing method of package carrier is provided. A first copper foil layer, a second copper foil layer on the first foil layer, a third copper foil layer and a fourth foil layer on the third foil layer are provided. The second copper foil layer is partially bonded the fourth copper foil layer by an adhesive gel so as to form a substrate of which the peripheral region is glued and the effective region is not glued. Therefore, the thinner substrate can be used in the following steps, such as patterning process or plating process. In addition, the substrate can be extended be the package carrier structure with odd-numbered layer or even-numbered layer.

Abstract: A semiconductor device is made by forming an interconnect structure over a substrate. A semiconductor die is mounted to the interconnect structure. The semiconductor die is electrically connected to the interconnect structure. A ground pad is formed over the interconnect structure. An encapsulant is formed over the semiconductor die and interconnect structure. A shielding cage can be formed over the semiconductor die prior to forming the encapsulant. A shielding layer is formed over the encapsulant after forming the interconnect structure to isolate the semiconductor die with respect to inter-device interference. The shielding layer conforms to a geometry of the encapsulant and electrically connects to the ground pad. The shielding layer can be electrically connected to ground through a conductive pillar. A backside interconnect structure is formed over the interconnect structure, opposite the semiconductor die.

Abstract: A semiconductor device has a substrate having a plurality of metal traces. A die is electrically attached to a first surface of the substrate. A first plurality of segmented metal traces is formed around a perimeter of the first surface of the substrate, wherein an end section of the first plurality of segmented metal traces is exposed. A mold compound is used for encapsulating the semiconductor device. A first metal plating is formed on a top terminal end section of the first plurality of segmented metal traces. The first metal plating is spread to at least one of the mold compound or the exposed end sections of the first plurality of segmented metal traces. A conductive coating is applied to the mold compound, the exposed end sections of the first plurality of segmented metal traces and to the first metal plating.

Abstract: Composite with a first part composed of a thermoset material and with a second part composed of a thermoplastic material, and with an adhesion-promoter layer located between these, where the first part has been bonded by way of the adhesion-promoter layer to the second part, and where the adhesion-promoter layer comprises pyrolytically deposited semiconductor oxides and/or pyrolytically deposited metal oxides.

Abstract: An integrated circuit package system including: forming a die pad, wherein the die pad has a tiebar at a corner; forming a lead wherein the lead is connected to the tiebar; connecting an integrated circuit die to the die pad; and forming an encapsulation, having an edge, over the integrated circuit die with the lead extending from and beyond the edge.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming an outer contact pad having an outer pad top side; mounting an integrated circuit above the outer pad top side; forming an encapsulation having an encapsulation top side and an encapsulation bottom side, the encapsulation over the integrated circuit with the encapsulation bottom side coplanar with the outer pad top side; and forming a vertical interconnect through the encapsulation, the vertical interconnect having an interconnect bottom side directly on the outer pad top side and an interconnect top side exposed from the encapsulation.

Abstract: A polymeric composition comprising a first polymer chosen from a poly(arylene ether) polymer including polymer repeat units of the following structure: —(O—Ar1—O—Ar2—O—)m—(—O—Ar3—O—Ar4—O)n- where Ar1, Ar2, Ar3, and Ar4 are identical or different aryl radicals, m is 0 to 1, n is 1 m; a polysulfone, a polyimide, a poly(etherketone), a polyurea, a polyurethane, and combinations thereof and a second polymer comprising a per(phenylethynyl) arene polymer derivative. Cured films containing the polymer can exhibit at least one of the following properties: Tg from 160° C. to 180° C., a dielectric constant below 2.7 with frequency independence, and a maximum moisture absorption of less than 0.17 wt %. Accordingly, the polymer is especially useful, for example, in interlayer dielectrics and in die-attach adhesives.

Abstract: A leadframe strip comprises a plurality of units arranged in a line. Each unit provides two component positions, each having a chip support substrate. The chip support substrates of the two component positions are mechanically linked by at least one support bar. The two component positions of a unit are molded at essentially the same time to produce a plastic housing for a package in each component position. The central portion of the first support bars remains outside of the plastic housing of the two packages.

Abstract: An electronic device in which a metal wire (119) is bonded to an electronic component (111) contained in a case (110) by wire bonding and a bonding surface (121, 122) to which the metal wire (119) is bonded is covered with a synthetic resin (130) is manufactured by injecting an amount of synthetic resin (130) into the case (110) such that at least a portion of the metal wire (119) is exposed from a top surface of the synthetic resin (130); and leaving the case (110) to which the synthetic resin (130) is injected under reduced pressure so as to raise a liquid surface of the synthetic resin (130) due to the reduced pressure, and covering the metal wire (119) exposed from the top surface of the synthetic resin (130) with the synthetic resin (30, 130).

Abstract: A package assembly including a semiconductor die electrically coupled to a substrate by an interconnected joint structure. The semiconductor die includes a bump overlying a semiconductor substrate, and a molding compound layer overlying the semiconductor substrate and being in physical contact with a first portion of the bump. The substrate includes a no-flow underfill layer on a conductive region. A second portion of the bump is in physical contact with the no-flow underfill layer to form the interconnected joint structure.

Abstract: A system and method for packaging semiconductor dies is provided. An embodiment comprises a first package with a first contact and a second contact. A post-contact material is formed on the first contact in order to adjust the height of a joint between the contact pad a conductive bump. In another embodiment a conductive pillar is utilized to control the height of the joint between the contact pad and external connections.

Abstract: A fabrication method of a semiconductor package includes the steps of: providing a carrier having a concave portion and a releasing layer formed on a surface thereof; disposing a chip on the releasing layer in the concave portion; forming an encapsulant on the chip and the releasing layer; removing the releasing layer and the carrier; and forming a circuit structure on the encapsulant and the chip. The design of the concave portion facilitates alignment of the chip to prevent it from displacement, thereby improving the product reliability. A semiconductor package fabricated by the fabrication method is also provided.

Abstract: A semiconductor device has a die pad, a heat dissipating plate in the form of a frame arranged between the die pad and leads so as to surround the die pad, members that connect the die pad and the inner edge of the heat dissipating plate, and a suspension lead linked to the outer extension of the heat dissipating plate. A semiconductor chip larger than the die pad is mounted over the die pad and the members. Top surfaces of the die pad and the members in opposition to the back surface of the chip are bonded to the back surface of the chip with silver paste. Heat is conducted from the back surface of the chip to the heat dissipating plate via the silver paste, the die pad, and the members, and dissipated to the outside of the semiconductor device via the leads.

Abstract: An insulating member of the invention can include an epoxy resin, a first inorganic filler diffused in the epoxy resin and having an average particle diameter of 1 to 99 nm, and a second inorganic filler diffused in the epoxy resin and having an average particle diameter of 0.1 to 100 ?m. The first and second inorganic fillers can be independent of each other, and can be selected from a group including Al2O3, SiO2, BN, AlN, and Si3N4, and the blending ratios of the first and second inorganic fillers in the insulating member can be 0.1 to 7% by weight and 80 to 95% by weight respectively. A metal base substrate can be formed by forming a metal foil and a metal base on either surface of the insulating member.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a leadframe strip system, having a stress relief slot and a leadframe unit, the stress relief slot is at a frame corner of the leadframe strip system and spans adjacent sides of the leadframe unit, the leadframe unit includes a paddle, a tie bar therefrom, and a lead finger; connecting an integrated circuit and the lead finger; forming an encapsulation covering the integrated circuit; and singulating the integrated circuit in the encapsulation from the leadframe strip system with a package corner of the encapsulation free of micro-cracks with an inspection of the package corner at least 50× view.

Abstract: An integrated circuit assembly is fabricated on a metal substrate strip in an array format that has raised circuitry pattern formed by photolithographic and metal etching processes. The circuitry pattern is formed on one side of the metal substrate only. The raised circuitry's etch depth extends partially through the metal substrate. Die attachment can be performed using a non-conductive material applied directly onto and around the raised circuitry features directly under the die. After wirebond and molding processes, the molded metal substrate strip assembly is processed through a metal etching process to remove the metal substrate portion that is exposed beyond the mold cap. A solder mask coating can be applied to protect the metal circuitry and to define the package pad opening to form Land-Grid-Array (LGA) packages. Solder balls can also be attached to form Ball-Grid-Array (BGA) packages.

Abstract: A substrate structure, a semiconductor package and a manufacturing method of semiconductor package are provided. The substrate structure comprises a conductive structure, an electrical component, a package body and a ring-shaped conductive structure. The conductive structure comprises a first conductive layer and a second conductive layer. The first conductive layer has a lower surface. The second conductive layer and the electrical component are formed on the lower surface of the first conductive layer. The package body encapsulates the conductive structure and the electrical component and has an upper surface. The ring-shaped conductive structure surrounds the conductive structure and the electrical component and is disposed at the edge of the upper surface of the package body to expose the conductive structure.

Abstract: A package stack device includes a first package structure having a plurality of first metal posts and a first electronic element, a second package structure having a plurality of second metal posts and a second electronic element, and an encapsulant formed between the first and second package structures to encapsulate the first electronic element. By connecting the second metal posts to the first metal posts, respectively, the second package structure is stacked on the first package structure with the support of the metal posts. Further, the gap between the two package structures is filled with the encapsulant to avoid warpage of the substrates.

Abstract: An integrated circuit device including: a first die, a first die bonding pad formed on the first die, a gold bump electrode formed on the first bonding pad, and a copper wire having a first end portion stitch bonded to the gold bump electrode; and a method of forming the integrated circuit device.

Abstract: A method of manufacture of a thin package system with external terminals includes: providing a leadframe; providing a template for defining an external bond finger; forming external bond fingers in the template on the leadframe; forming land pad terminals by a first multi-layer plating; providing a die; attaching the die to the land pad terminals above the leadframe with an adhesive on the leadframe; covering an encapsulant over at least portions of the die and the external bond fingers; and removing the leadframe leaving a surface of the adhesive coplanar with a surface of the encapsulant.

Abstract: The invention relates to a semiconductor package of a flip chip and a method for making the semiconductor package. The semiconductor chip comprises a metal-oxide-semiconductor field effect transistor. On a die paddle including a first base, a second base and a third base, half-etching or punching is performed on the top surfaces of the first base and the second base to obtain plurality of grooves that divide the top surface of the first base into a plurality of areas comprising multiple first connecting areas, and divide the top surface of the second base into a plurality of areas comprising at least a second connecting area. The semiconductor chip is connected to the die paddle at the first connecting areas and the second connecting area.

Abstract: A semiconductor device permitting the reduction of cost is disclosed. In a semiconductor package wherein electrode pads of a semiconductor chip and corresponding inner leads are electrically coupled with each other through a plurality of bonding wires, sensing wires (second and fourth bonding wires) are made thinner than other bonding wires (first and third bonding wires) coupled to inner leads same as those with the sensing wires coupled thereto, thereby reducing the cost of gold wires to attain the reduction in cost of the semiconductor package.

Abstract: The invention provides a molded interposer package and a method for fabricating the same. The molded interposer package includes a plurality of metal studs. A molding material encapsulates the metal studs leaving the bottom surfaces of the metal studs exposed. A first chip is disposed on the molding material, connecting to the top surfaces of the metal studs. A plurality of solder balls connects and contacts to the bottom surfaces of the metal studs.

Abstract: A bar formed from a reconstituted wafer and containing one or more conductive material filled voids is used to electrically and physically connect the top and bottom packages in a package-on-package (PoP) package. The bar is disposed in the fan out area of the lower package forming the PoP package.

Abstract: A method for making a housing for an optoelectronic component is disclosed. The housing has a plastic base body that has a front side with an assembly region for at least one radiation emitting or radiation detecting body. The plastic base body is formed from at least one first plastic component and at least one second plastic component. The second plastic component is disposed on the front side of the plastic base body, and is formed from a material that differs from the first plastic component in at least one optical property, and forms an optically functional region of the plastic base body.

Abstract: A semiconductor device has an interposer with a die attach area interior to the interposer and cover attach area outside the die attach area. A channel is formed into a surface of the interposer within the cover attach area. A dam material is formed over the surface of the interposer within the cover attach area between the channel and edge of the interposer. A semiconductor die is mounted to the die attach area of the interposer. An adhesive material is deposited in the cover attach area away from the channel and dam material. A cover, such as a heat spreader or shielding layer, is mounted to the die and interposer within the cover attach area. The cover presses the adhesive material into the channel and against the dam material to control outward flow of the adhesive material. Alternatively, ACF can be formed over the interposer to mount the cover.

Abstract: An exposed die overmolded flip chip package includes a substrate. A die is flip chip mounted to an upper surface of the substrate. The package further includes a mold cap filling a space between an active surface of the die and the upper surface of the substrate. The mold cap includes a principal surface, sidewalls extending from the upper surface of the substrate to the principal surface, an annular surface coplanar with the inactive surface of the die and extending outward from a peripheral edge of the inactive surface of the die, and protruding surfaces extending between the principal surface and the annular surface. The mold cap does not cover the inactive surface of the die such that heat transfer from the die to the ambient environment is maximized and the package thickness is minimized.

Abstract: A semiconductor device has a semiconductor wafer with a plurality of semiconductor die. Contact pads are formed on a surface of the semiconductor die. The semiconductor die are separated to form a peripheral region around the semiconductor die. An encapsulant or insulating material is deposited in the peripheral region around the semiconductor die. An interconnect structure is formed over the semiconductor die and insulating material. The interconnect structure has an I/O density less than an I/O density of the contact pads on the semiconductor die. A substrate has an I/O density consistent with the I/O density of the interconnect structure. The semiconductor die is mounted to the substrate with the interconnect structure electrically connecting the contact pads of the semiconductor die to the first conductive layer of the substrate. A plurality of semiconductor die each with the interconnect structure can be mounted over the substrate.

Abstract: Integrating a semiconductor component with a substrate through a low loss interconnection formed through adaptive patterning includes forming a cavity in the substrate, placing the semiconductor component therein, filling a gap between the semiconductor component and substrate with a fill of same or similar dielectric constant as that of the substrate and adaptively patterning a low loss interconnection on the fill and extending between the contacts of the semiconductor component and the electrical traces on the substrate. The contacts and leads are located and adjoined using an adaptive patterning technique that places and forms a low loss radio frequency transmission line that compensates for any misalignment between the semiconductor component contacts and the substrate leads.

Abstract: A resin-sealed semiconductor device includes a power element (1), a control element (4), a first lead frame (3) having a first die pad (3A) which holds the power element (1), a second lead frame (5) having a second die pad (5A) which holds the control element (4), and a housing (6) made of a resin material and sealing the power element, the first die pad, the control element, and the second die pad. A lower surface of the second die pad is higher than an upper surface of the first element, and at least part of the first die pad and at least part of the second die pad overlap each other when viewed from the top. One of the first leads and one of the second leads are directly joined together by a joint portion (23) and electrically coupled together in the housing.

Abstract: A method of forming an electronic assembly includes attaching a backside metal layer the bottomside of a semiconductor die. An area of the backside metal layer matches an area of the bottomside of the die. A die pad and leads are encapsulated within the molding material. The leads include an exposed portion that includes a bonding portion. A gap exposes the backside metal layer along a bottom surface of the package. Bond wires couple the pads on the topside of the die to the leads and the bonding portions. Packaged semiconductor device is soldered to a printed circuit board (PCB). The backside metal layer and the bonding portions of the leads are soldered substrate pads on said PCB.

Abstract: A semiconductor package includes: a dielectric layer having opposing first and second surfaces and side surfaces; a copper wiring layer disposed on the first surface of the dielectric layer and having extension pads; a surface processing layer disposed on the wiring layer; a semiconductor chip disposed on the wiring layer and electrically connected to the surface processing layer; and an encapsulant disposed on the first surface of the dielectric layer for encapsulating the semiconductor chip, the wiring layer and the surface processing layer while exposing the second surface of the dielectric layer. Further, vias are disposed between the side surfaces of the dielectric layer and the encapsulant such that the extension pads are exposed from the vias so as for solder balls to be disposed thereon. Due to improved electrical connection between the copper and solder materials, the electrical connection quality of the package is improved.

Abstract: A display device and a method for manufacturing the same, for discharging static electricity generated in the manufacturing process of a display device using a mechanical shutter and thus preventing the mechanical shutter from being deformed by the static electricity are provided. The display device includes a TFT substrate having thin film transistors thereon respectively provided with a plurality of mechanical shutters located in a matrix and also having terminals thereon for supplying a signal to the thin film transistors from outside; and a counter substrate joined with the TFT substrate. Along at least one of an edge of the TFT substrate and an edge of the counter substrate, an injection opening for injecting an insulating liquid into an area between the TFT substrate and the counter substrate and a ground electrode for covering at least a part of an inner surface of the injection opening are provided.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming an isolated contact having a contact protrusion; forming a die paddle, adjacent to the isolated contact, having a die paddle contour; depositing a contact pad on the contact protrusion; coupling an integrated circuit die to the contact protrusion; molding an encapsulation on the integrated circuit die; and depositing an organic filler on and between the isolated contact and the die paddle, the contact protrusion extended past the organic filler.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing routable traces including a first routable trace with a top plate and a second routable trace; mounting an integrated circuit partially over a second routable trace; forming an encapsulation over and around the first routable trace and the integrated circuit; forming a hole through the encapsulation to the top plate; and forming a protective coat directly on the encapsulation with the first routable trace between and in contact with the protective coat and the encapsulation.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a lead; forming an interior conductive layer having an interior top side and an interior bottom side, the interior bottom side directly on the lead; mounting an integrated circuit over the lead, the integrated circuit having an inactive side and an active side; forming an encapsulation directly on the inactive side and the interior top side; and forming an insulation layer directly on the active side and a portion of the interior bottom side.

Abstract: A method of fabricating a semiconductor package. In one embodiment the method includes forming a mold cavity about a portion of a first major surface of a leadframe, including about a mold lock opening extending through the leadframe between the first major surface and a second major surface. A spacer is inserted to fill at least a portion of the mold lock opening. The mold cavity is filled with an encapsulating material including filling a portion of the mold lock opening not occupied by the spacer.

Abstract: A method of assembling a magnetoresistive random access memory (MRAM) device includes providing a substrate having an opening. A tape is applied to a surface of the substrate and a first magnetic shield is placed onto the tape and within the substrate opening. An adhesive is applied between the first magnetic shield and the substrate to attach the first magnetic shield to the substrate. An MRAM die is attached to the first magnetic shield and bond pads of the MRAM die are connected to pads on the substrate with wires. A second magnetic shield is attached to a top surface of the MRAM die. An encapsulating material is dispensed onto the substrate, the MRAM die, the second magnetic shield and part of the first magnetic shield, cured, and then the tape is removed. Solder balls then may be attached to the substrate.

Abstract: A semiconductor device includes a first carrier having a first resin disposed over the first carrier. A fabric is disposed over the first resin. A second resin is formed over the first resin and around the fabric to form an asymmetrical pre-impregnated (PPG) substrate. The first carrier is removed. A second carrier is provided and a first conductive layer is formed over the second carrier. A portion of the first conductive layer is removed. The first conductive layer is transferred from the second carrier to the first resin. The first conductive layer is oriented asymmetrically such that the first conductive layer is offset with respect to the fabric to minimize warpage. The second carrier is removed. A via is formed through the second resin and fabric to expose the first conductive layer. A second conductive layer formed in the via over the first conductive layer.

Abstract: A semiconductor module comprises components in one wafer level package. The module comprises an integrated circuit (IC) chip embedded within a package molding compound. The package comprises a molding compound package layer coupled to an interface layer for integrating an antenna structure and a bonding interconnect structure to the IC chip. The bonding interconnect structure comprises three dimensional interconnects. The antenna structure and bonding interconnect structure are coupled to the IC chip and integrated within the interface layer in the same wafer fabrication process.

Abstract: A semiconductor device includes a substrate having a first side and a second side, the second side having a mounting location for at least one semiconductor element, and the first side having a plurality of locations electrically connected to locations on the second side. A plurality of electrically conductive interconnects are provided at the locations, each having a first end attached at the location and a second end spaced from the substrate, and an encapsulant partially encapsulates the plurality of interconnects and has a surface lying in a first plane. The second ends are located on the side of the first plane opposite from the substrate first side, an annular space in the encapsulant surrounds each of the plurality of electrically conductive interconnects, and the annular space has a bottom located between the first plane and the substrate first side. Also a method for making such a semiconductor device.

Abstract: Embodiments of the present disclosure provide an apparatus including a semiconductor die having a plurality of integrated circuit devices, a pad structure electrically coupled to at least one integrated circuit device of the plurality of integrated circuit devices via an interconnect layer, an electrically insulative layer disposed on the interconnect layer, a first shielding structure disposed in the electrically insulative layer and electrically coupled to the pad structure, an under-ball metallization (UBM) structure electrically coupled to the first shielding structure, and a solder bump electrically coupled to the UBM structure, the solder bump comprising a solder bump material capable of emitting alpha particles, wherein the first shielding structure is positioned between the solder bump and the plurality of integrated circuit devices to shield the plurality of integrated circuit devices from the alpha particles. Other embodiments may be described and/or claimed.

Abstract: An integrated circuit assembly is fabricated on a metal substrate strip in an array format that has raised circuitry pattern formed by photolithographic and metal etching processes. The circuitry pattern is formed on one side of the metal substrate only. The raised circuitry's etch depth extends partially through the metal substrate. Die attachment can be performed using a non-conductive material applied directly onto and around the raised circuitry features directly under the die. After wirebond and molding processes, the molded metal substrate strip assembly is processed through a metal etching process to remove the metal substrate portion that is exposed beyond the mold cap. A solder mask coating can be applied to protect the metal circuitry and to define the package pad opening to form Land-Grid-Array (LGA) packages. Solder balls can also be attached to form Ball-Grid-Array (BGA) packages.

Abstract: This invention discloses a semiconductor package with adhesive material pre-printed on the lead frame and chip, and the manufacturing method. The adhesive material is applied onto the chip carrier and the pin of the lead frame and also on the front electrode of the semiconductor chip via pre-printing. The back of the semiconductor chip is adhered on the chip carrier, and the front electrode of the semiconductor chip and the pin are connected respectively with a metal connector. The size, shape and thickness of the adhesive material are applied according to different application requirements according to size and shapes of the contact zone of the semiconductor chip and the metal connector. Particularly, the adhesive zones are formed by pre-printing the adhesive material thus significantly enhance the quality and performance of semiconductor products, and improves the productivity.

Abstract: An integrated circuit (IC) device includes a polymer substrate having a topside surface and a bottomside surface opposite the topside surface, a plurality of through-holes that extend from the topside surface to the bottomside surface, and a plurality of bottom metal pads on the bottomside surface positioned over the plurality of through-holes. At least one IC die having an active topside including a plurality of bond pads and a second side is affixed to the topside surface. Bonding features are coupled to the plurality of bond pads for coupling respective ones of the plurality of bond pads to the plurality bottom metal pads. The bonding features extend into the through-holes to contact the bottom metal pads.

Abstract: A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure.