Abstract: A substrate for mounting a device comprises: an insulating resin layer; a plurality of projected electrodes that are connected electrically to a wiring layer provided on one major surface of the insulating resin layer, and that project toward the insulating resin layer from the wiring layer; and a counter electrode provided at a position corresponding to each of the plurality of projected electrodes on the other major surface of the insulating resin layer. Among the projected electrodes, a projected length of part of the projected electrodes is smaller than that of the other projected electrodes; and the projected electrode and the counter electrode corresponding thereto are capacitively-coupled, and the projected electrode and the counter electrode are connected electrically.

Abstract: A multilayer substrate includes an insulating base member having a plurality of resin films, an electric element embedded in the insulating base member, and a spacer. The resin films are made of a thermoplastic resin and stacked and attached to each other. At least one resin film has a through hole for inserting the electric element. The one resin film further has a plurality of protruding members. One protruding member opposes to another one protruding member so that the one and the another one contact and sandwich the electric element. The spacer is arranged between the one resin film and an adjacent resin film and is disposed at a base portion of one of the protruding members.

Abstract: A method for manufacturing a hollowed printed circuit board includes steps of: providing an electrically conductive layer; laminating a first dielectric layer having a first through opening defined therein on a first surface of the electrically conductive layer; forming a protecting layer on the first surface of the electrically conductive layer in the first opening; creating an electrically conductive pattern in the conductive layer; removing the protecting layer; and laminating a second dielectric layer having a second through opening defined therein on an opposite second surface of the electrically conductive layer in a manner that the first through opening is aligned with the second through opening, thereby a portion of the electrically conductive layer is exposed to exterior through the first through opening and the second through opening.

Abstract: A method, system and program product for bonding two circuitry-including semiconductor substrates, and a related stage, are disclosed. In one embodiment, a method of bonding two circuitry-including substrates includes: providing a first stage for holding a first circuitry-including substrate and a second stage for holding a second circuitry-including substrate; identifying an alignment mark on each substrate; determining a location and a topography of each alignment mark using laser diffraction; creating an alignment model for each substrate based on the location and topography the alignment mark thereon; and bonding the first and second circuitry-including substrates together while aligning the first and second substrate based on the alignment model.

Abstract: A wiring electronic component of the present invention is incorporated into an electronic device package in which a circuit element including a semiconductor chip is disposed and in which the circuit element is connected to a wiring pattern on the back face and also connected, via vertical wiring, to external electrodes located on the front face opposite the wiring pattern. The wiring electronic component is composed of an electrically conductive support portion, which serves as an electroforming mother die, and a plurality of vertical wiring portions formed through electroforming such that they are integrally connected to the support portion.

Abstract: In a semiconductor device, a substrate includes a plurality of line conductors which penetrate the substrate from a top surface to a bottom surface of the substrate. A semiconductor chip is secured in a hole of the substrate. A first insulating layer is formed on the top surfaces of the substrate and the semiconductor chip. A first wiring layer is formed on the first insulating layer and electrically connected via through holes of the first insulating layer to the semiconductor chip and some line conductors exposed to one of the through holes. A second insulating layer is formed on the bottom surfaces of the substrate and the semiconductor chip. A second wiring layer is formed on the second insulating layer and electrically connected via a through hole of the second insulating layer to some line conductors exposed to the through hole.

Abstract: Various methods are described where the semiconductor die and the lead frame (or the BGA or LGA substrate) are spaced apart to reduce stress. In one scenario, an air gap is formed between the semiconductor die and the lead frame by depositing a perimeter (made, for example, using polymer) either on the semiconductor die or the lead frame. In another scenario, an anisotropic conducting film (ACF) is formed with an air gap between the semiconductor die and the lead frame (or the BGA or LGA substrate). The air gap relieves stress on the semiconductor die. Further, a lead frame-based isolator package and a BGA (or LGA) isolator package are described. A window-frame ACF-based isolation method for magnetic coupling in a lead-frame package and BGA (or LGA) package is also described.

Abstract: A light-emitting diode system (1) comprising at least one light-emitting diode component (2), in which a light-emitting diode chip is arranged in a light-emitting diode housing (21) on a heat sink (22) which can be thermally connected at the rear side (25) of the light-emitting diode housing (21). A carrier plate (3) having a front side (34) and a rear side (31) and a hole for receiving the light-emitting diode component (2) is provided. The light-emitting diode component (2) projects into the hole from the rear side (31) of the carrier plate (3). An electrically insulating thermal connection layer (5) is applied at the rear side (31) of the carrier plate (3), said thermal connection layer being thermally conductively connected to the heat sink (22). A method for producing a light-emitting diode system is also described.

Abstract: An electronic device includes the electronic element, the interposer substrate, on one surface of which the electronic element is mounted, and the interconnection substrate, on one surface of which the interposer substrate is mounted. One portion of the connection parts is an electrical connection part that electrically interconnects the interposer substrate and the interconnection substrate. The remaining portion is a dummy connection part that produces no functional deficiency even when the dummy connection part does not electrically interconnect the interposer substrate with the interconnection substrate. The dummy connection part includes at least one of the connection parts that at least partially overlap with the electronic element in a plan projection and are preferably arranged along an outer rim of the plan projection of the electronic element.

Abstract: A small and thin surface-mount type optical semiconductor device having high air tightness, which can be manufactured at a reduced cost includes: a base 2 formed of a glass substrate; a recess 5 formed on a first main surface 3 of the base; a through hole 7 extending from a bottom portion 4 of the recess to a second main surface 6 of the base; an inner wall conductive film formed on an inner wall surface of the through hole; a wiring pattern 9 made of a conductive film formed around an opening of the through hole on the bottom portion of the recess so as to be connected electrically to the inner wall conductive film; an optical semiconductor element 8 bonded to the wiring pattern via a conductive bonding material 14; a terminal portion 10 made of a conductive film formed around an opening of the through hole on the second main surface such that it is connected electrically to the inner wall conductive film; and a metal portion 13 bonded to the inner wall conductive film to clog the through hole.

Abstract: The present invention is a method of mounting a plurality of components on a substrate.

Abstract: A manufacturing method of a semiconductor device is provided, which includes a process in which a transistor is formed over a first substrate; a process in which a first insulating layer is formed over the transistor; a process in which a first conductive layer connected to a source or a drain of the transistor is formed; a process in which a second substrate provided with an second insulating layer is arranged so that the first insulating layer is attached to the second insulating layer; a process in which the second insulating layer is separated from the second substrate; and a process in which a third substrate provided with a second conductive layer which functions as an antenna is arranged so that the first conductive layer is electrically connected to the second conductive layer.

Abstract: A ball grid array package system comprising: forming a package base including: fabricating a heat spreader having an access port, attaching an integrated circuit die to the heat spreader, mounting a substrate around the integrated circuit die, and coupling an electrical interconnect between the integrated circuit die and the substrate; and coupling a second integrated circuit package to the substrate through the access port.

Abstract: A testing method for a silicon interposer employs a test probe and an electrically conductive glass handler. The silicon interposer includes multiple interconnects that extend between the opposed major surfaces of the interposer, namely from a test side of the interposer to a conductive glass handler side of the interposer. On the glass handler side, the interposer includes a layer of patterned insulative resist with open regions at some interconnects on the glass handler side and remaining resist regions at other interconnects on the glass handler side. The interposer may include a conductive adhesive layer that couples together interconnects at the open regions on the glass handler side. In this manner, a probe may send a test signal from a first interconnect at one location on the test side of the interposer, through the first interconnect, through the conductive adhesive, through a second interconnect to another probe on the test side of the interposer.

Abstract: A semiconductor device of the invention includes a semiconductor substrate having a first insulating section formed on one surface thereof. A first conductive section is disposed on the one surface of the semiconductor substrate. A second insulating section is superimposed over the first insulating section and covers the first conductive section. A second conductive section is superimposed over the second insulating section. A third insulating section is disposed over the second insulating section and covers the second conductive section. These first conductive section, second insulating section, second conductive section, third insulating section, and terminal altogether constitute a structure. A third opening is formed between adjacent structures. The third opening is formed passing through the third and second insulating sections to expose the first insulating section.

Abstract: A method of manufacturing a semiconductor package, including at least a step A that forms a first transforming portion by irradiating a laser beam on at least a portion of a first substrate; a step B that joins together the first substrate and a second substrate in which a functional element is disposed; a step C that removes the first transforming portion that is disposed on the first substrate by etching; and a step D that forms a conductive portion in the first substrate by filling a conductive material in a portion where the first transforming portion has been removed.

Abstract: A method of fabricating a semiconductor plastic package can include: providing a core board, which includes at least one pad, and which has a coefficient of thermal expansion of 9 ppm/° C. or lower; stacking a build-up insulation layer over the core board; forming an opening by removing a portion of the build-up insulation layer such that the pad is exposed to the exterior; and placing a semiconductor chip in the opening and electrically connecting the semiconductor chip with the pad. This method can be utilized to provide higher reliability in the connection between the semiconductor chip and the circuit board.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a through silicon via die having an interconnect through a silicon substrate; depositing a re-distribution layer on the through silicon via die and connected to the interconnects; mounting a structure over the through silicon via die; connecting the structure to the interconnect of the through silicon via die with a direct interconnect; and encapsulating the through silicon via die and partially encapsulating the structure with an encapsulation.

Abstract: An aspect of the present invention features a method for manufacturing a substrate having a cavity. The method can comprises: (a) forming an upper layer circuit on an upper seed layer; (b) laminating a dry film on a portion of the upper seed layer where a cavity is to be formed; (c) fabricating an upper outer layer by forming an insulation layer on top of the upper seed layer and on top and sides of the upper layer circuit; (d) stacking the upper outer layer on one side of a core layer where an internal circuit is formed; (e) removing the upper seed layer; and (f) forming the cavity by removing the dry film. The method for manufacturing a substrate with a cavity according to the present invention can reduce the total thickness of the substrate while the thickness of an insulation layer remains the same, by forming the insulation layer on sides of an external circuit.

Abstract: A semiconductor device has a chip, a first bump electrode, a conductive wire and a second bump electrode. The chip has at least one contact pad, and the first bump electrode is formed on the contact pad. The conductive wire is disposed on an active surface of the chip and electrically connected to the first bump electrode. The second bump electrode is formed on the conductive wire, and the second bump electrode is not disposed over any contact pad of the chip. In addition, a method for packaging a chip and an IC package are also disclosed.

Abstract: The semiconductor package includes a dielectric layer, a trace layer, a conductive layer, a die and an underfill layer. The dielectric layer has first side and an opposing dielectric layer second side. Multiple vias extend through the dielectric layer from the dielectric layer first side to the dielectric layer second side. Multiple solder balls are disposed at the dielectric layer second side. Each of the solder balls is electrically coupled to a different one of the vias. The die is electrically coupled to the solder balls. The conductive layer is disposed between the dielectric layer second side and the die. The conductive layer defines a window there through for allowing the solder balls to electrically couple to the vias without contacting the conductive layer, i.e., no physical or electrical contact. The underfill layer is formed between the die and the conductive layer, while the trace layer is formed at the dielectric layer first side.

Abstract: A flash-memory device has a printed-circuit board assembly (PCBA) with a PCB with a flash-memory chip and a controller chip. The controller chip includes an input/output interface circuit to an external computer over a Secure-Digital (SD) interface, and a processing unit to read blocks of data from the flash-memory chip. The PCBA is encased inside an upper case and a lower case, with SD contact pads on the PCB that fit through contact openings in the upper case. Supporting end ribs under each of the SD contact pads and middle ribs support the PCB at a slanted angle to the centerline of the device. The PCB slants upward at the far end to allow more thickness for the chips mounted to the bottom surface of the PCB, and slants downward at the insertion end to position the SD contact pads near the centerline.

Abstract: A rerouting element for a semiconductor device includes a dielectric film that carries conductive vias, conductive elements, and contact pads. The conductive vias are positioned at locations that correspond to the locations of bond pads of a semiconductor device with which the rerouting element is to be used. The conductive elements, which communicate with corresponding conductive vias, reroute the bond pad locations to corresponding contact pad locations adjacent to one peripheral edge or two adjacent peripheral edges of the rerouted semiconductor device. The rerouting element is particularly useful for rerouting centrally located bond pads of a semiconductor device, as well as for rerouting the peripheral locations of bond pads of a semiconductor device to one or two adjacent peripheral edges thereof. Methods for designing and using the rerouting element are also disclosed, as are semiconductor device assemblies including one or more rerouting elements.

Abstract: Embodiments of the present invention relate to a method of stiffening a semiconductor coreless package substrate to improve rigidity and resistance against warpage. An embodiment of the method comprises disposing a sacrificial mask on a plurality of contact pads on a second level interconnect (package-to-board interconnect) side of a coreless package substrate, forming a molded stiffener around the sacrificial mask without increasing the effective thickness of the substrate, and removing the sacrificial mask to form a plurality of cavities in the molded stiffener corresponding to the contact pads. Embodiments also include plating the surface of the contact pads and the sidewalls of the cavities in the molded cavities with an electrically conductive material.

Abstract: Disclosed herein is a method of positioning and placing an integrated circuit on a printed circuit board. The integrated circuit comprises first geometrical elements. The first geometrical elements are of one or more predefined shapes and are located on one or more predefined surfaces of the integrated circuit. The printed circuit board comprises second geometrical elements. The second geometrical elements are shaped to accommodate the first geometrical elements. The first geometrical elements are designed to fit into the second geometrical elements. The first geometrical elements are positioned and placed over the second geometrical elements. The first geometrical elements come in contact with the second geometrical elements at two or more points. The positioning and placement of the first geometrical elements over the second geometrical elements limits displacement of connections of the integrated circuit from the printed circuit board.

Abstract: A BGA package is disclosed including a base IC structure having a base substrate, with an opening running length-wise there through. A first semiconductor chip is mounted face-down on the base substrate so the bond pads thereof are accessible through the opening. The package also includes a secondary IC structure including a secondary substrate, having an opening running there through, and a second semiconductor chip. The second chip is mounted face-down on the secondary substrate so that the bond pads thereof are accessible through the opening in the secondary substrate. An encapsulant fills the opening in the secondary substrate and forms a substantially planar surface over the underside of the secondary substrate. The substantially planar surface is mounted to the first chip of the base IC structure through an adhesive. Wires connect a conductive portion of the secondary IC structure to a conductive portion of the base IC structure.

Abstract: Disclosed is a component built-in wiring board, including a first insulating layer; a second insulating layer positioned in a laminated state on the first insulating layer; a semiconductor element buried in the second insulating layer, having a semiconductor chip with terminal pads and having surface mounting terminals arrayed in a grid shape connected electrically with the terminal pads; an electric/electronic component further buried in the second insulating layer; a wiring pattern sandwiched between the first insulating layer and the second insulating layer, including a first mounting land for the semiconductor element and a second mounting land for the electric/electronic component; a first connecting member connecting electrically the surface mounting terminal of the semiconductor element with the first mounting land; and a second connecting member connecting electrically the terminals of the electric/electronic component with the second mounting land, made of a same material as a material of the first c

Abstract: A structure and a method for forming the same. The structure includes (i) a carrier substrate which includes substrate pads, (ii) a chip physically attached to the carrier substrate, and (iii) a first frame physically attached to the carrier substrate. A CTE (coefficient of thermal expansion) of the first frame is substantially lower than a CTE of the carrier substrate.

Abstract: In an electronic component mounting structure, a semiconductor element (an electronic component) provided with an electrode pad and a board provide with an electrode pad corresponding to the electrode pad are connected via a conductive material portion. On a surface of the board, there is formed solder resist having an opening regulating an area of the electrode pad. The conductive material portion is formed to protrude from a surface of the solder resist. An elastic coefficient of the conductive material portion is lower than that of the solder resist. A solder bump and the conductive material portion are connected via a metal layer. The conductive material portion is formed to have an area larger than that of the opening of the solder resist. An edge of the conductive material portion is adhered to a portion of the surface of the solder resist. Thus, in a case of mounting an electronic component on a board by flip-chip connection, a reliability of connection can be secured.

Abstract: The present invention discloses an electronic device package and a method of the package. In particular, an electronic device package and a method of the package suitable for a bumpless electronic device package with enhanced electrical performance and heat-dissipation efficiency are disclosed. The method comprises: providing a substrate having a plurality of vias and a plurality of electronic devices; forming a gluing layer on a surface of the substrate and fixing the electronic devices on the gluing layer, wherein the electronic devices have I/O units aligned with the vias respectively; forming a plurality of fixing layers in the gaps between the electronic devices; trenching a plurality of openings aligned with the vias respectively in the fixing layer; forming a plurality of metallic conductive units in the vias, the openings and part of the surface of the substrate; and forming a passivation layer over the other surface of the substrate.

Abstract: Embodiments of the present invention relate to the use of stamping to form features on a lead frame of a semiconductor device package. In one embodiment, portions of the lead frame such as pins are moved out of the horizontal plane of a diepad by stamping. In certain embodiments, indentations or a complex cross-sectional profile, such as chamfered, may be imparted to portions of the pins and/or diepad by stamping. The complexity offered by such a stamped cross-sectional profile serves to enhance mechanical interlocking of the lead frame within the plastic molding of the package body. Other techniques such as selective electroplating and/or formation of a brown oxide guard band to limit spreading of adhesive material during die attach, may be employed alone or in combination to facilitate fabrication of a package having such stamped features.

Abstract: A process is provided for manufacturing micromechanical devices formed by joining two parts together by direct bonding. One of the parts (12) is made of silicon and the other one is made of a material chosen between silicon and a semiconductor ceramic or oxidic material. The joint between the two parts forms a cavity (14) containing the functional elements of the device (11), possible auxiliary elements and a getter material deposit (13).

Abstract: A method and apparatus for increasing the immunity of new generation microprocessors from electrostatic discharge events involve shielding the microprocessors at the die level. A gasket of a lossy material is provided on the substrate upon which the microprocessor is mounted. The gasket surrounds the microprocessor to protect it from electrostatic discharge pulses. A heat spreader is arranged in heat conducting relation with the microprocessor and atop at least a portion of the gasket adjacent the die. The material is a static dissipative material having a volume resistivity of greater than 102 ohm cm and a shielding effectiveness to protect the microprocessor from at least 4 kV of electrostatic discharge pulse at the computer system level in which the microprocessor is to be used.

Abstract: An electronic apparatus includes metal wiring plates placed together in the same plane to provide a wiring circuit, electronic devices mounted to the wiring plates through a solder, a case having a base portion and columnar portions extending from the base portion. The wiring plates are fixed to the columnar portions such that the wiring circuit is spaced from the base portion. The wiring plates have an enough thickness to resist a large current for operating the electronic devices and to release heat generated by the electronic devices. The wiring circuit is spaced from the base portion of the case so that the heat generated by the electronic devices is released in the space efficiently. The electronic devices are soldered to the wiring plates at once in a thermal reflow process.

Abstract: A semiconductor module and a method for producing the same is disclosed. In one embodiment, the semiconductor module has adjacent regions on a common wiring substrate in a common plastic housing composition. The regions are thermally decoupled by a thermal barrier. Semiconductor chips whose evolution of heat loss differs are arranged in these thermally separate regions, the thermal barrier ensuring that the function of the more thermally sensitive semiconductor chip is not impaired by the heat-loss-generating semiconductor chip.

Abstract: A method for making micro-electromechanical system devices includes: (a) forming a sacrificial layer on a device wafer; (b) forming a plurality of loop-shaped through-holes in the sacrificial layer so as to form the sacrificial layer into a plurality of enclosed portions; (c) forming a plurality of cover caps on the sacrificial layer such that the cover caps respectively enclose the enclosed portions of the sacrificial layer; (d) forming a device through-hole in each of active units of the device wafer so as to form an active part suspended in each of the active units; and (e) removing the enclosed portions of the sacrificial layer through the device through-holes in the active units of the device wafer.

Abstract: Provided are semiconductor packages comprising at least one thin-film capacitor attached to a printed wiring board core through build-up layers, wherein a first electrode of the thin-film capacitor comprises a thin nickel foil, a second electrode comprises a copper electrode, and a copper layer is formed on the nickel foil. The interconnections between the thin-film capacitor and the semiconductor device provide a low inductance path to transfer charge to and from the semiconductor device. Also provided are methods for fabricating such semiconductor packages.

Abstract: Methods relating to the reconstruction of semiconductor wafers for wafer-level processing are disclosed. Selected semiconductor dice having alignment cavities formed in a surface thereof are placed in contact with liquid, gel or other flowable alignment droplets in a similar pattern protruding from a substrate to position the dice through surface tension interaction. The alignment droplets are then solidified to maintain the positioning and an underfill is disposed between the dice and the fixture to strengthen and maintain the reconstructed wafer. A fixture plate may be used in combination with the underfill to add additional strength and simplify handling. The reconstructed wafer may be subjected to wafer-level processing, wafer-level testing and burn-in being particularly facilitated using the reconstructed wafer. Alignment droplets composed of sacrificial material may be removed from the reconstructed wafer and the resulting void filled to form interconnects or contacts on the resulting dice.

Abstract: A method and system for fabricating a interconnect substrate for a multi-component package is disclosed. The multi-component package includes at least one die and a package substrate. The method and system include providing an insulating base and providing at least one conductive layer. The at least one conductive layer provides interconnects for at least one discrete component. The interconnect substrate is configured to be mounted on the at least one die and to have the at least one discrete component mounted on the interconnect substrate.

Abstract: A method for producing an electronic component with an electronic circuit and electrical contacts, disposed at least on a first surface of the electronic component, for the electrical bonding of the electronic circuit includes at least one flexible elevation of an insulating material disposed on the first surface, at least one electrical contact disposed on the flexible elevation, and a conduction path disposed on the surface or in the interior of the flexible elevation between the electrical contact and the electronic circuit.

Abstract: An LTCC (low temperature cofired ceramic) structure which has conductors to which leads are to be bonded for connection to external circuitry. The conductors include additives to promote adhesion to the ceramic layer. The presence of these additives degrade bonding performance. For better bondability of the leads, a pure conductor metal layer, devoid of the additives is placed on the conductors in areas where leads are to be bonded. This pure conductor metal layer may be cofired with the stack of ceramic layers or may be post fired after stack firing.

Abstract: The present invention realizes a semiconductor device of high reliability which allows metal terminals which have a uniform height, are flat and smooth to be formed under low load and at low costs and to be mounted with low damage. The electrodes 5 and the insulating film 6 are both formed of materials having the property that they are solid and do not exhibit the adhesiveness at room temperature and exhibit the adhesiveness at a temperature not lower than a first temperature and cure at a temperature not lower than a second temperature higher than the first temperature. The surfaces of the electrodes 5 and the insulating film 6 of a semiconductor chip 1a are planarized in continuously flat with a hard cutting tool, as of diamond or others.

Abstract: On a surface of a resin base material (11), a first resin coating film (19) having a larger thickness and a larger area than a second resin coating film (20) formed on the other surface of the resin base material (11) is continuously formed. The second resin coating film (20) is formed so as to be separated into a plurality of portions.

Abstract: The present invention realizes a semiconductor device of high reliability which allows metal terminals which have a uniform height, are flat and smooth to be formed under low load and at low costs and to be mounted with low damage. The electrodes 5 and the insulating film 6 are both formed of materials having the property that they are solid and do not exhibit the adhesiveness at room temperature and exhibit the adhesiveness at a temperature not lower than a first temperature and cure at a temperature not lower than a second temperature higher than the first temperature. The surfaces of the electrodes 5 and the insulating film 6 of a semiconductor chip 1a are planarized in continuously flat with a hard cutting tool, as of diamond or others.

Abstract: Provided is a semiconductor memory module allowing a filling member formed between a module substrate and memory chips mounted on the module substrate to completely fill the space between the module substrate and the memory chips. According to embodiments of the present invention, the semiconductor memory module includes a module substrate having at least one memory chip mounted on the substrate such that its edges are oblique to major and minor axes bisecting the module substrate. The oblique orientation allows for an improved opening between memory chips formed on the substrate so that the filling member may be properly formed between the module substrate and the memory chips to prevent voids where the filling member is not formed.

Abstract: A semiconductor package of this invention achieves higher wiring densities and increases the degree of freedom of the wiring design. The semiconductor package includes a first substrate having first and second faces, and first wiring provided on the first face of the first substrate. The semiconductor package also includes a second substrate having first and second faces, and second wiring provided on the first face of the second substrate. The semiconductor package also includes a semiconductor chip connected to the first and second wiring. The first face of the first substrate faces the first face of the second substrate, and the first and second wiring intersect one another in three dimensions in an isolated state.

Abstract: An electronic device and method is disclosed. In one embodiment, a method includes providing an electrically insulating substrate. A first electrically conductive layer is applied over the electrically insulating substrate. A first semiconductor chip is placed over the first electrically conductive layer. An electrically insulating layer is applied over the first electrically conductive layer. A second electrically conductive layer is applied over the electrically insulating layer. A through connection is formed in the electrically insulating layer to couple the second electrically conductive layer to the first electrically conductive layer.

Abstract: Disclosed herein is a semiconductor device including: a semiconductor circuit element configured to process an electrical signal having a predetermined frequency; and a transmission line configured to be connected to the semiconductor circuit element via a wire and transmit the electrical signal. An impedance matching pattern having a symmetric shape with respect to a direction of the transmission line is provided in the transmission line.

Abstract: Apparatus and methods for forming semiconductor assemblies. An interposer includes a perimeter wall surrounding at least a portion of an upper surface thereof to form a recess. An array of electrical connection pads is located within the recess. A semiconductor die can be flip chip attached to the interposer by at least partial insertion of the semiconductor die within the recess with discrete conductive elements between bond pads of the semiconductor die and electrical connection pads of the interposer. The electrical connection pads communicate with a number of other electrical contact pads accessible elsewhere on the interposer, preferably on a lower surface thereof. A low viscosity underfill encapsulant is disposed between the semiconductor die and the interposer and around the discrete conductive elements by permitting the same to flow into the space between the die and the perimeter wall.

Abstract: Methods and assemblies relate to bezel packaging of a sealed glass assembly, such as a frit-sealed OLED device. The bezel packaging includes a shock absorbent intermediate layer of low modulus of elasticity material applied between the sealed glass assembly and the bezel. A bonding agent, which may include the low modulus of elasticity material and/or a separate bonding material, affixes the sealed glass assembly to the bezel. Bezel modifications may be made to stabilize the bezel. Exemplary bezel modifications include reinforced bezel side walls and supporting straps attached between bezel walls. The bezel design may include a gap between the edges of the sealed glass assembly and the bezel walls, so as to avoid direct contact therewith. The gap may be filled at least in part with low modulus of elasticity organic adhesive to provide additional shock absorbency. The low modulus of elasticity material may include foam, ceramic fiber cloth and/or a low modulus of elasticity polymeric organic coating.