Insulative Housing Or Support Patents (Class 438/125)
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Publication number: 20120171788Abstract: It is an object of the present invention to provide a highly sophisticated functional IC card that can ensure security by preventing forgery such as changing a picture of a face, and display other images as well as the picture of a face. An IC card comprising a display device and a plurality of thin film integrated circuits; wherein driving of the display device is controlled by the plurality of thin film integrated circuits; a semiconductor element used for the plurality of thin film integrated circuits and the display device is formed by using a polycrystalline semiconductor film; the plurality of thin film integrated circuits are laminated; the display device and the plurality of thin film integrated circuits are equipped for the same printed wiring board; and the IC card has a thickness of from 0.05 mm to 1 mm.Type: ApplicationFiled: March 8, 2012Publication date: July 5, 2012Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Toru TAKAYAMA, Junya MARUYAMA, Yuugo GOTO, Yumiko OHNO, Mai AKIBA
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Publication number: 20120161312Abstract: Electronic assemblies and their manufacture are described. One assembly includes a substrate and a die on a first side of the substrate. A plurality of non-solder metal bumps are positioned on a second side of the substrate. The assembly also includes a board to which the non-solder metal bumps are coupled. The assembly also includes solder positioned between the board and the substrate, wherein the board is electrically coupled to the substrate through the solder and the bumps. Other embodiments are described and claimed.Type: ApplicationFiled: December 23, 2010Publication date: June 28, 2012Inventors: Md Altaf HOSSAIN, Scott A. GILBERT
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Patent number: 8207020Abstract: There is provided a semiconductor device whose cost is low and whose case is restrained from breaking. In the semiconductor device having a semiconductor sensor chip, a signal processing circuit for processing signals output from the semiconductor sensor chip and a hollow case for mounting the semiconductor sensor chip and the signal processing circuit therein, the case is constructed by bonding a concave bottom member whose one end is opened with a plate-like lid member that covers the opening of the bottom member. Then, the bottom and lid members are both made of a semiconductor material and are bonded by means of anode bonding or metal bonding for example.Type: GrantFiled: April 4, 2011Date of Patent: June 26, 2012Assignee: Lapis Semiconductor Co., Ltd.Inventors: Yoshihiko Ino, Takeharu Suzuki
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Patent number: 8207022Abstract: An exposed die overmolded flip chip package includes a substrate. A die is flip chip mounted to an upper surface of the substrate. The package further includes a mold cap filling a space between an active surface of the die and the upper surface of the substrate. The mold cap includes a principal surface, sidewalls extending from the upper surface of the substrate to the principal surface, an annular surface coplanar with the inactive surface of the die and extending outward from a peripheral edge of the inactive surface of the die, and protruding surfaces extending between the principal surface and the annular surface. The mold cap does not cover the inactive surface of the die such that heat transfer from the die to the ambient environment is maximized and the package thickness is minimized.Type: GrantFiled: January 27, 2011Date of Patent: June 26, 2012Assignee: Amkor Technology, Inc.Inventors: Robert Francis Darveaux, Michael Barrow, Miguel Angel Jimarez, Jae Dong Kim, Dae Keun Park, Ki Wook Lee, Ju Hoon Yoon
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Publication number: 20120155048Abstract: There are provided steps of providing a dielectric layer and a wiring layer on a surface of a support to form an intermediate body, removing the support from the intermediate body to obtain a wiring board, and carrying out a roughening treatment over a surface of the support before the intermediate body forming step.Type: ApplicationFiled: February 24, 2012Publication date: June 21, 2012Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventor: Kentaro KANEKO
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Publication number: 20120146208Abstract: A semiconductor module according to one embodiment includes a semiconductor chip, an insulating substrate, a case, an electrode, a busbar and a busbar support body. The semiconductor chip is mounted on the insulating substrate. The insulating substrate is housed inside the case. The electrode is disposed in the case and is electrically connected to the semiconductor chip. The electrode is supported on an electrode support section of the case. The busbar is bonded to the electrode and is led out of the case. The busbar support body holds the busbar and is mounted on the case.Type: ApplicationFiled: December 7, 2011Publication date: June 14, 2012Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventor: Jiro SHINKAI
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Publication number: 20120146246Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a package substrate having an outer pad at a substrate top side; forming a resist layer directly on the substrate top side, the resist layer having a resist top side with a channel array adjacent the outer pad exposed from the resist layer; mounting an integrated circuit having an active side facing the resist top side, the integrated circuit having a non-horizontal side adjacent the outer pad; and forming a dielectric between the active side and the resist top side, the dielectric having a fillet extended from the non-horizontal side to the substrate top side inside an inner extent of the channel array.Type: ApplicationFiled: December 9, 2010Publication date: June 14, 2012Inventors: WonJun Ko, DeokKyung Yang, Yeongbeom Ko
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Patent number: 8198141Abstract: An intermediate structure for semiconductor devices includes a wiring board, a plurality of semiconductor chips mounted on the wiring board, and a sealing body for collectively sealing the plurality of semiconductor chips and having a region with a different thickness.Type: GrantFiled: December 14, 2009Date of Patent: June 12, 2012Assignee: Elpida Memory, Inc.Inventors: Youkou Ito, Takashi Ohba
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Patent number: 8198713Abstract: One embodiment provides a semiconductor wafer structure including a semiconductor wafer and a spacer layer. The semiconductor wafer includes active areas. The spacer layer is configured to provide spacing between the semiconductor dice in a stacked die package and the spacer layer is disposed on one side of the semiconductor wafer.Type: GrantFiled: July 13, 2007Date of Patent: June 12, 2012Assignee: Infineon Technologies AGInventor: Erich Hufgard
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Patent number: 8198140Abstract: A wiring substrate for mounting semiconductors is provided with an insulation film, wires formed in the insulation film, and a plurality of electrode pads that electrically connect to the wires through vias. The electrode pads are provided to have their surfaces exposed to both of the front surface and the rear surface of the insulation film, and at least a part of the side surface of the electrode pads is buried in the insulation film. The insulation film is formed by forming electrode pads on the respective two metallic plates, thereafter, laminating an insulation layer and wires on the respective metallic plates to cover the electrode pad, and adhering the insulation layers to each other for integration, and thereafter, removing the metallic plates.Type: GrantFiled: September 15, 2010Date of Patent: June 12, 2012Assignees: NEC Corporation, Renesas Electronics CorporationInventors: Hideya Murai, Tadanori Shimoto, Takuo Funaya, Katsumi Kikuchi, Shintaro Yamamichi, Kazuhiro Baba, Hirokazu Honda, Keiichiro Kata, Kouji Matsui, Shinichi Miyazaki
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Publication number: 20120139116Abstract: A structure includes a hybrid substrate for supporting a semiconductive device that includes a bumpless build-up layer in which the semiconductive device is embedded and a laminated-core structure. The bumpless build-up layer and the laminated-core structure are rendered an integral apparatus by a reinforcement plating that connects to a plated through hole in the laminated-core structure and to a subsequent bond pad of the bumpless build-up layer structure.Type: ApplicationFiled: December 7, 2010Publication date: June 7, 2012Inventors: Mathew J. Manusharow, Mark S. Hlad, Ravi K. Nalla
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Patent number: 8193633Abstract: Provided is a heat conductive sheet obtained by dispersing an inorganic filler in a thermosetting resin, in which the inorganic filler contains secondary aggregation particles formed by isotropically aggregating scaly boron nitride primary particles having an average length of 15 ?m or less, and the inorganic filler contains more than 20 vol % of the secondary aggregation particles each having a particle diameter of 50 ?m or more. The heat conductive sheet is advantageous in terms of productivity and cost and excellent in heat conductivity and electrical insulating properties.Type: GrantFiled: September 12, 2008Date of Patent: June 5, 2012Assignee: Mitsubishi Electric CorporationInventors: Kenji Mimura, Hideki Takigawa, Hiroki Shiota, Kazuhiro Tada, Takashi Nishimura, Hiromi Ito, Seiki Hiramatsu, Atsuko Fujino, Kei Yamamoto, Motoki Masaki
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Patent number: 8193043Abstract: An exemplary semiconductor die package of the invention has a metal-oxide substrate disposed between a first surface of a semiconductor die and a heat-sinking component, with a conductive die clip or one or more electrical interconnect traces disposed between the metal-oxide substrate and the first surface of the semiconductor die. The heat-sinking component may comprise a heat sink, or an adaptor plate to which a heat sink may be coupled. The conductive die clip or electrical trace(s) provides electrical connection(s) to the first surface of the semiconductor die, while the metal-oxide substrate electrically insulates the die from the heat-sinking component, and provides a path of high thermal conductivity between the die and the heat-sinking component. The second surface of the semiconductor die may be left free to connect to a circuit board, or a leadframe or interconnect substrate may be attached to it.Type: GrantFiled: September 15, 2010Date of Patent: June 5, 2012Assignee: Fairchild Semiconductor CorporationInventors: Oseob Jeon, Chung-Lin Wu, Eddy Tjhia, Bigildis C. Dosdos
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Patent number: 8193033Abstract: The semiconductor device 100 comprises a first semiconductor element 113 provided on a face on one side of a flat plate shaped interconnect component 101, an insulating resin 119 covering a face of a side where the first semiconductor element 113 of the interconnect component 101 is provided and a side face of the first semiconductor element 113, and a second semiconductor element 111 provided on a face on the other side of the interconnect component 101. The interconnect component 101 has a constitution where an interconnect layer 103, a silicon layer 105 and an insulating film 107 are sequentially formed. The interconnect layer 103 has a constitution where the interconnect layer 103 has a flat plate shaped insulating component and a conductive component extending through the insulating component. The first semiconductor element 113 is electrically connected with the second semiconductor element 111 through the conductive component.Type: GrantFiled: July 9, 2008Date of Patent: June 5, 2012Assignee: Renesas Electronics CorporationInventor: Yoichiro Kurita
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Patent number: 8193042Abstract: The present invention provides an electronic assembly 400 and a method for its manufacture 800, 900, 1000 1200, 1400, 1500, and 1700. The assembly 400 uses no solder. Components 406 or component packages 402, 802, 804, 806 with I/O leads 412 are placed 800 onto a planar substrate 808. The assembly is encapsulated 900 with electrically insulating material 908 with vias 420, 1002 formed or drilled 1000 through the substrate 808 to the components' leads 412. Then the assembly is plated 1200 and the encapsulation and drilling process 1500 repeated to build up desired layers 422, 1502, 1702. The planar substrate 808 may be a flexible substrate 2016 allowing bending of an assembly 2000 to fit into various enclosures.Type: GrantFiled: October 19, 2009Date of Patent: June 5, 2012Assignee: Occam Portfolio LLCInventor: Joseph C. Fjelstad
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Publication number: 20120132463Abstract: Embodiments of the present invention provide a printed wiring board in which solder bumps of a mounted semiconductor chip are less prone to be ruptured. The printed wiring board includes a dielectric layer having a main surface and a connecting pad embedded in the dielectric layer. The connecting pad is shaped like a brimmed hat. That is, the connecting pad includes a plate portion whose diameter is larger than that of a contact portion. The main surface of the contact portion is exposed at the main surface of the dielectric layer. Diameter of the contact portion is substantially the same as diameter of an under bump metal at the semiconductor chip side, when mechanical stress is applied, the stress disperses evenly to both of the connecting pad and the under bump metal, and thus rupture is less prone to occur.Type: ApplicationFiled: February 3, 2012Publication date: May 31, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Hiroyuki Mori, Kazushige Kawasaki
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Patent number: 8188574Abstract: A microelectronic element, e.g., a semiconductor chip having a silicon-on-insulator layer (“SOI layer”) separated from a bulk monocrystalline silicon layer by a buried oxide (BOX) layer in which a crack stop extends in first lateral directions at least generally parallel to the edges of the chip to define a ring-like barrier separating an active portion of the chip inside the barrier with a peripheral portion of the chip. The crack stop can include a first crack stop ring contacting a silicon portion of the chip above the BOX layer; the first crack stop ring may extend continuously in the first lateral directions to surround the active portion of the chip. A guard ring (“GR”) including a GR contact ring can extend downwardly through the SOI layer and the BOX layer to conductively contact the bulk monocrystalline silicon region, the GR contact ring extending at least generally parallel to the first crack stop ring to surround the active portion of the chip.Type: GrantFiled: February 12, 2010Date of Patent: May 29, 2012Assignee: International Business Machines CorporationInventors: Matthew S. Angyal, Mahender Kumar, Effendi Leobandung, Jay W. Strane
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Patent number: 8183086Abstract: Semiconductor devices and methods of making thereof are provided. In one aspect, for example, a method for making a semiconductor device can include polishing a working surface of a diamond layer to a substantially flat surface, depositing a buffer layer on the working surface of the diamond layer, and depositing a semiconductor layer on the buffer layer. In one specific aspect, the c-axis of the buffer layer is oriented perpendicular to the working surface of the diamond layer.Type: GrantFiled: May 5, 2010Date of Patent: May 22, 2012Inventor: Chien-Min Sung
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Patent number: 8183092Abstract: A stacked semiconductor structure and fabrication method thereof are provided. The method includes mounting and connecting electrically a semiconductor chip to a first substrate, mounting on the first substrate a plurality of supporting members corresponding in position to a periphery of the semiconductor chip, mounting a second substrate having a first surface partially covered with a tape and a second surface opposite to the first surface on the supporting members via the second surface, connecting electrically the first and second substrates by bonding wires, forming on the first substrate an encapsulant for encapsulating the semiconductor chip, the supporting members, the second substrate, the bonding wires, and the tape with an exposed top surface, and removing the tape to expose the first surface of the second substrate and allow an electronic component to be mounted thereon. The present invention prevents reflow-induced contamination, spares a special mold, and eliminates flash.Type: GrantFiled: July 2, 2010Date of Patent: May 22, 2012Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chien-Ping Huang, Chih-Ming Huang, Han-Ping Pu, Yu-Po Wang, Cheng-Hsu Hsiao
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Patent number: 8183088Abstract: Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.Type: GrantFiled: June 25, 2010Date of Patent: May 22, 2012Assignee: Fairchild Semiconductor CorporationInventors: Oseob Jeon, Yoonhwa Choi, Boon Huan Gooi, Maria Cristina B. Estacio, Rajeev Joshi, Chung-Lin Wu, Venkat Iyer, Byoung-Ok Lee
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Patent number: 8178371Abstract: A method for assembling an optically pumped solid-state laser having an extended cavity. The method includes the steps of providing a casing, mounting a TEC and a base plate in the casing, and mounting a plurality of laser components on the base plate using a UV and heat curing adhesive. Once the laser components are correctly positioned and aligned on the base plate, the adhesive is pre-cured using UV radiation. Final curing of the adhesive is obtained by subjecting the entire laser package to an ambient temperature of at least 100° C. The base plate is preferably selected to have a CTE similar to that of the laser components in order to facilitate the high temperature curing. A preferred material for the base plate is AlSiC.Type: GrantFiled: June 20, 2011Date of Patent: May 15, 2012Assignee: Cobolt ABInventors: Jonas Hellström, Gunnar Elgcrona, Kenneth Joelsson
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Patent number: 8174043Abstract: In a light-emitting apparatus using a silicone resin as a sealant of its light-emitting element, it is intended to prevent discoloration of its lead frame. A light-emitting element fixed to a lead frame is sealed with a sealed portion formed by a silicone resin. An average spin-spin relaxation time of the silicone resin is equal to or smaller than 100 microseconds at 25° C. at a resonance frequency of 25 MHz.Type: GrantFiled: August 21, 2009Date of Patent: May 8, 2012Assignee: Toyoda Gosei Co., Ltd.Inventor: Yuhki Ito
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Publication number: 20120108014Abstract: An object is to provide a highly reliable semiconductor device that has tolerance to external stress and electrostatic discharge. Another object is to prevent defective shapes and defective characteristics due to the external stress or an electrostatic discharge in the manufacturing process, and to manufacture a semiconductor device with high yield. Still another object is to manufacture a semiconductor device at low cost and with high productivity. With the use of a conductive shield, electrostatic breakdown (malfunctions of the circuit or damages of a semiconductor element) due to electrostatic discharge of the semiconductor integrated circuit is prevented. The conductive shield is formed so that at least the conductive shields on the top and bottom surfaces are electrically connected by a plating method. In addition, a semiconductor device can be formed at low cost with high productivity because a plating method is used for the formation of the conductive shield.Type: ApplicationFiled: November 3, 2011Publication date: May 3, 2012Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Yuugo GOTO, Teruyuki FUJII
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Patent number: 8169043Abstract: An optical sensor package structure includes a substrate, a metal plate, an optical sensing chip, a plurality of bonding wires and a lens module. The substrate includes a top surface, a bottom surface and a hole penetrating the top surface and the bottom surface. The metal plate covers the hole from the bottom surface of the substrate. The optical sensing chip is received in the hole and mounted on the metal plate. The bonding wires interconnect the optical sensing chip and the top surface of substrate. The lens module is covering on the hole and mounting on the top surface of the substrate to enclose the optical sensing chip and the bonding wires. Because the optical sensing chip is received in the hole of the substrate, the height of the optical sensor package structure can be reduced to adapt to a compact size electrical device.Type: GrantFiled: February 9, 2010Date of Patent: May 1, 2012Assignee: Cheng Uei Precision Industry Co., Ltd.Inventors: Yu-Hsiang Chen, Cheng-I Lu, Min-Nan Yeh, Chi-Hsiang Chang
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Patent number: 8168476Abstract: Packaged semiconductor devices and assemblies including interconnects and methods for forming such interconnects are disclosed herein. One embodiment of a packaged semiconductor assembly includes a die attached to a support layer. A plurality of interconnects are embedded in and project from the support layer, such that the support layer at least partially retains the interconnects in a predetermined array. An encapsulant is molded around each of the interconnects and encases at least a portion of the die, support layer and interconnects.Type: GrantFiled: September 3, 2010Date of Patent: May 1, 2012Assignee: Micron Technology, Inc.Inventors: Boon Suan Jeung, Chia Yong Poo, Eng Meow Koon
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Patent number: 8168477Abstract: This invention discloses an electronic package for containing a vertical semiconductor chip that includes a laminated board having a via connector and conductive traces distributed on multiple layers of the laminated board connected to the via connector. The semiconductor chip having at least one electrode connected to the conductive traces for electrically connected to the conductive traces at a different layer on the laminated board and the via connector dissipating heat generated from the vertical semiconductor. A ball grid array (BGA) connected to the via connector functioning as contact at a bottom surface of the package for mounting on electrical terminals disposed on a printed circuit board (PCB) wherein the laminated board having a thermal expansion coefficient in substantially a same range the PCB whereby the BGA having a reliable electrical contact with the electrical terminals.Type: GrantFiled: November 18, 2010Date of Patent: May 1, 2012Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Ming Sun, Yueh Se Ho
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Publication number: 20120098126Abstract: The joint reliability in flip chip bonding of a semiconductor device is enhanced. Prior to flip chip bonding, flux 9 is applied to the solder bumps 5a for flip chip bonding over a substrate and reflow/cleaning is carried out and then flip chip bonding is carried out. This makes is possible to thin the oxide film over the surfaces of the solder bumps 5a and make the oxide film uniform. As a result, it is possible to suppress the production of local solder protrusions to reduce the production of solder bridges during flip chip bonding and enhance the joint reliability in the flip chip bonding of the semiconductor device.Type: ApplicationFiled: October 14, 2011Publication date: April 26, 2012Inventors: Toshihiro IWASAKI, Takeumi KATO, Takanori OKITA, Yoshikazu SHIMOTE, Shinji BABA, Kazuyuki NAKAGAWA, Michitaka KIMURA
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Patent number: 8164178Abstract: A chip-type semiconductor ceramic electronic component including a ceramic body made of a semiconductor ceramic, first external electrodes formed on opposite end surfaces of the ceramic body, and second external electrodes extending to cover surfaces of the first external electrodes and part of side surfaces of the ceramic body. A curvature radius of a corner portion of the ceramic body is R (?m), a maximum thickness of a layer of the first external electrode layer, which is in contact with the ceramic body, measured from the end surface of the ceramic body is y (?m), and a minimum thickness of a layer of the second external electrode, which is in contact with the side surface of the ceramic body, measured from an apex of the corner portion of the ceramic body is x (?m), and 20?R?50, ?0.4 x+0.6?y?0.4 is satisfied when 0.5?x?1.1, and ?0.0076 x+0.16836?y?0.4 is satisfied when 1.1?x?9.0.Type: GrantFiled: July 28, 2010Date of Patent: April 24, 2012Assignee: Murata Manufacturing Co., Ltd.Inventors: Takayo Katsuki, Yoshiaki Abe
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Patent number: 8164174Abstract: A microstructure component, in particular an encapsulated micromechanical sensor element, including at least one microstructure patterned out from a silicon layer being encapsulated by a glass element. At least the region of the glass element covering the microstructure is furnished with an electrically conductive coating on its side facing the microstructure.Type: GrantFiled: October 10, 2001Date of Patent: April 24, 2012Assignee: Robert Bosch GmbHInventor: Franz Laermer
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Patent number: 8158462Abstract: A manufacture method of a light emitting device is provided. Firstly, at least one circuit board is provided. A plurality of light emitting packages, a first undetermined power input end and a second undetermined power input end are disposed at the circuit board. The light emitting packages are electrically connected to the first undetermined power input end and the second undetermined power input end. Each of the first undetermined power input end and the second undetermined power input end has at least two first pads. The first pads of each of the first undetermined power input end and the second undetermined power input end are electrically isolated from each other. Next, the first undetermined power input end is selected to be a power input region for inputting an external power signal. Then, the first pads of the second undetermined power input end are electrically connected to each other.Type: GrantFiled: December 10, 2010Date of Patent: April 17, 2012Assignee: AU Optronics Corp.Inventors: Yu-Chuan Lin, Shau-Yu Tsai
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Patent number: 8158461Abstract: A mechanism for continuously referencing signals over multiple layers in laminate packages provides a continuous path for signals from one layer to another while using the ideal voltage reference for all areas of the package and still avoiding discontinuities in the voltage reference. A reference plane adjustment engine analyzes a package design and identifies an ideal top plane for all areas of the package, including areas under particular chip die(s) and areas that are not under a chip die. The reference plane adjustment engine then modifies the package design to reposition ground planes, source voltage planes, signal planes, and vias between layers to maintain a continuous voltage reference regardless of the top layer. The reference plane adjustment engine provides the resulting mixed voltage plane package design to a design analysis engine. A package fabrication system fabricates the package.Type: GrantFiled: June 24, 2009Date of Patent: April 17, 2012Assignee: International Business Machines CorporationInventors: Francesco Preda, Lloyd A. Walls
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Patent number: 8158460Abstract: A leadframe for the assembly of a semiconductor chip has regions (112) with an original smooth surface of glossy appearance and regions (113, 114, 210) of a frosty appearance with rough surface contours. The regions of rough surface contours include two-dimensional arrays of spots (401) comprising a central area (402) below the original surface (400) and a piled ring (403) above the original surface. The piled ring (403) consists of the leadframe material in amorphous configuration.Type: GrantFiled: September 21, 2011Date of Patent: April 17, 2012Assignee: Texas Instruments IncorporatedInventor: Donald C Abbott
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Publication number: 20120086100Abstract: CMOS structures with a replacement substrate and methods of manufacture are disclosed herein. The method includes forming a device on a temporary substrate. The method further includes removing the temporary substrate. The method further includes bonding a permanent electrically insulative substrate to the device with a bonding structure.Type: ApplicationFiled: October 6, 2010Publication date: April 12, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Paul S. ANDRY, Edmund J. SPROGIS, Cornelia K. TSANG
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Publication number: 20120086116Abstract: An electronic component device includes a substrate, an electrode post made of a metal material, provide to stand on the substrate, and an electronic component whose connection electrode is connected to the electrode post, wherein the connection electrode of the electronic component and the electrode post are joined by an alloy layer including a metal which is different from the metal material of the electrode post.Type: ApplicationFiled: August 30, 2011Publication date: April 12, 2012Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventors: Yuichi TAGUCHI, Akinori Shiraishi, Mitsutoshi Higashi
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Patent number: 8154115Abstract: A package structure having an MEMS element includes: a chip having at least an MEMS element and a plurality of first conductive pads; a lid disposed on the chip to cover the MEMS element and having a plurality of second conductive pads formed thereon; a plurality of bonding wires electrically connecting the first and second conductive pads; a plurality of first bumps disposed on the second conductive pads, respectively; an encapsulant formed on the chip to encapsulate the lid, the bonding wires, the first and second conductive pads and the first bumps while exposing the top surfaces of the first bumps; and a plurality of circuits formed on the encapsulant and electrically connecting to the exposed first bumps, thereby avoiding the conventional drawback of electrical connection failure caused by position deviation of bonding wires due to mold flow of the encapsulant.Type: GrantFiled: February 10, 2011Date of Patent: April 10, 2012Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chang-Yueh Chan, Chien-Ping Huang, Chun-Chi Ke, Shih-Kuang Chiu
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Patent number: 8153472Abstract: An embedded chip package process is disclosed. A first substrate having a first patterned circuit layer is provided. A second substrate having a second patterned circuit layer is provided. A dielectric material layer is formed to cover the first patterned circuit layer. A compression process is performed to cover the second substrate over the dielectric material layer and the second patterned circuit layer is embed into the dielectric material layer. A curing process is performed to cure the dielectric material layer after the step of performing the compression process. At least a conductive plug through the dielectric material layer is formed to electrically connect the first patterned circuit layer to the second patterned circuit layer after the step of performing the curing process. The first substrate, the second substrate and a portion of the at least a conductive plug are removed after the step of forming the conductive through hole.Type: GrantFiled: December 6, 2010Date of Patent: April 10, 2012Assignee: Unimicron Technology Corp.Inventor: David C. H. Cheng
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Publication number: 20120083073Abstract: It is aimed at improving the reliability of a semiconductor device. In a POP having an upper package stacked on a lower package, an opening of a first solder resist film in a first region between a first group of lands arranged at the periphery of an front surface of a wiring substrate of the lower package and a second group of lands arranged in a central part is filled with a second solder resist film, and thereby the formation of a starting point of cracks in the opening becomes unlikely to suppress occurrence of cracks and improve the reliability of the POP.Type: ApplicationFiled: September 16, 2011Publication date: April 5, 2012Inventors: Yusuke TANUMA, Toshikazu Ishikawa
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Publication number: 20120083139Abstract: A memory module may include a module substrate having a side portion. The side portion may be adapted or configured to be inserted into a socket of a main board. A plurality of connection pads may be arranged along the side portion. The connection pads may have a step portion of a first height from a surface of the side portion and a contact portion of a second height that is greater than the first height from the surface of the side portion. At least one semiconductor package may be mounted on the module substrate and electrically connected to the connection pads.Type: ApplicationFiled: August 19, 2011Publication date: April 5, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jin-San Jung, Jung-Chan Cho, Hyun-Seok Choi
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Patent number: 8148199Abstract: A microelectronic assembly is provided which can include an element including a first dielectric layer and a second dielectric layer overlying the first dielectric layer, the second dielectric layer having an exposed surface defining an exposed major surface of the element. A plurality of substantially rigid metal posts can project beyond the exposed surface, the metal posts having ends remote from the exposed surface. The microelectronic assembly can include a microelectronic device which has bond pads and overlies the element. The microelectronic device can have a major surface which confronts the posts. Connections electrically connect the ends of the metal posts with the bond pads of the microelectronic device.Type: GrantFiled: April 9, 2009Date of Patent: April 3, 2012Assignee: Tessera, Inc.Inventor: Joseph Fjelstad
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Patent number: 8148205Abstract: A method of making a microelectronic connection component is disclosed. A plurality of portions of a conductive, etch-resistant material is provided on a surface of a metallic sheet. The sheet is etched from the surface to form posts extending generally parallel to one another aligned with the portions of the etch-resistant material. A microelectronic device is provided having one of a front face or a rear face overlying first ends of the posts. Second ends of the posts remote from the first ends face away from the microelectronic device as interconnection terminals for the connection component. At least some of the posts are electrically connected to the microelectronic device.Type: GrantFiled: September 30, 2010Date of Patent: April 3, 2012Assignee: Tessera, Inc.Inventor: Joseph Fjelstad
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Publication number: 20120074560Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a carrier; mounting an integrated circuit device having component connectors directly on the carrier; placing a restraint structure over the integrated circuit device for controlling warpage of the integrated circuit device during bonding of the component connectors to the carrier causing some of the component connectors to separate from the carrier; and bonding all of the component connectors to the carrier.Type: ApplicationFiled: September 24, 2010Publication date: March 29, 2012Inventors: Hin Hwa Goh, Xusheng Bao, Yung Kuan Hsiao, Kang Chen, Rui Huang
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Patent number: 8143100Abstract: A method for making a semiconductor multi-package module includes; providing a lower molded package including a lower substrate and a die, affixing an upper molded package including an upper substrate onto the upper surface of the lower package, and forming z-interconnects between the upper and lower substrates.Type: GrantFiled: August 31, 2007Date of Patent: March 27, 2012Assignee: ChipPAC, Inc.Inventor: Marcos Karnezos
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Patent number: 8143109Abstract: An exemplary method for fabricating a damascene interconnect structure includes the following. First, providing a substrate. Second, depositing a multilayer dielectric film on the substrate. Third, forming a patterned photoresist on the multilayer dielectric film. Fourth, etching the multilayer dielectric film to form a plurality of trenches, a portion of each of the trenches having an enlarged width at each of sidewalls thereof. Fifth, filling the trenches with conductive metal to form conductive lines such that air is trapped in extremities of the enlarged width portions of the trenches.Type: GrantFiled: December 13, 2010Date of Patent: March 27, 2012Assignee: Innolux Display Corp.Inventor: Shuo-Ting Yan
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Patent number: 8143108Abstract: A semiconductor device has a first substrate with a central region. A plurality of bumps is formed around a periphery of the central region of the first substrate. A first semiconductor die is mounted to the central region of the first substrate. A second semiconductor die is mounted to the first semiconductor die over the central region of the first substrate. A height of the first and second die is less than or equal to a height of the bumps. A second substrate has a thermal conduction channel. A surface of the second semiconductor die opposite the first die is mounted to the thermal conductive channel of the second substrate. A thermal interface layer is formed over the surface of the second die. The bumps are electrically connected to contact pads on the second substrate. A conductive plane is formed over a surface of the second substrate.Type: GrantFiled: December 10, 2010Date of Patent: March 27, 2012Assignee: STATS ChipPAC, Ltd.Inventor: Rajendra D. Pendse
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Publication number: 20120070940Abstract: A fixture assembly and method of forming a chip assembly is provided. The fixture assembly includes a first plate having an opening sized to accommodate a chip mounted on a laminate. The fixture assembly further includes a second plate mated to the first plate by at least one mechanical fastening mechanism. The fixture assembly further includes a space defined by facing surfaces of the first plate and the second plate and confined by a raised stepped portion of at least one of the first plate and the second plate. The space is coincident with the opening. The space is sized and shaped such that the laminate is confined within the space and directly abuts the stepped portion and the facing surfaces of the first plate and the second plate to be confined in X, Y and Z directions.Type: ApplicationFiled: September 22, 2010Publication date: March 22, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Thomas E. Lombardi, Donald Merte, Gregg B. Monjeau, David L. Questad, Son K. Tran
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Publication number: 20120068353Abstract: A semiconductor wafer contains a plurality of semiconductor die separated by saw streets. A dam material is formed over the saw streets around each of the semiconductor die. A plurality of openings is formed in the dam material. The openings in the dam material can be formed on each side or corners of the first semiconductor die. The semiconductor wafer is singulated through the dam material to separate the semiconductor die. The semiconductor die is mounted to a substrate. A mold underfill is deposited through a first opening in the dam material. A vacuum is drawn on a second opening in the dam material to cause the underfill material to cover an area between the first semiconductor die and substrate without voids. The number of second openings can be greater than the number of first openings. The first opening can be larger than the second opening.Type: ApplicationFiled: September 20, 2010Publication date: March 22, 2012Applicant: STATS ChipPAC, Ltd.Inventors: Rui Huang, Seng Guan Chow, Heap Hoe Kuang
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Patent number: 8138596Abstract: A microelectronic package (31) has a microelectronic device, which is encapsulated in a quantity of material (27), and a lead frame element (15) for enabling the microelectronic device to be electrically contacted from outside of the package (31). The lead frame element (15) comprises at least two elongated members (11) comprising electrically conductive material and a filling material (12) comprising electrically insulating material, wherein the members (11) are partially embedded in the filling material (12). The lead frame element (15) is manufactured by providing elongated members (11), positioning the members (11) according to a predetermined configuration, providing filling material (12) to spaces (13) which are present between the members (11), and possibly removing portions of the filling material (12) and the members (11) in order to expose the electrically conductive material of the members (11).Type: GrantFiled: April 11, 2008Date of Patent: March 20, 2012Assignee: NXP B.V.Inventor: Johannes W. Weekamp
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Patent number: 8129265Abstract: A system and method for forming post passivation discrete components, is described. High quality discrete components are formed on a layer of passivation, or on a thick layer of polymer over a passivation layer.Type: GrantFiled: February 18, 2005Date of Patent: March 6, 2012Assignee: Megica CorporationInventor: Mou-Shiung Lin
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Patent number: 8129229Abstract: A metal leadframe to be used in manufacturing a “flip-chip” type semiconductor package is treated to form a metal plated layer in an area to be contacted by a solder ball or bump on the chip. The leadframe is then process further to form an oxide or organometallic layer around the metal plated layer. Pretreating the leadframe in this manner prevents the solder from spreading out during reflow and maintains a good standoff distance between the chip and leadframe. During the molding process, the standoff between the chip and leadframe allows the molding compound to flow freely, preventing voids in the finished package.Type: GrantFiled: December 2, 2010Date of Patent: March 6, 2012Assignee: UTAC Thai LimitedInventors: Saravuth Sirinorakul, Somchai Nondhasitthichai
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Patent number: 8129225Abstract: A method includes providing an integral array of first carriers, arranging first semiconductor chips on the first carriers, and arranging an integral array of second carriers over the semiconductor chips.Type: GrantFiled: August 10, 2007Date of Patent: March 6, 2012Assignee: Infineon Technologies AGInventors: Stefan Landau, Alexander Koenigsberger, Joachim Mahler, Klaus Schiess