Abstract: A semiconductor package includes a workpiece with a conductive trace and a chip with a conductive pillar. The chip is attached to the workpiece and a solder joint region is formed between the conductive pillar and the conductive trace. The silver (Ag) content in the solder layer is between 0.5 and 1.8 weight percent.

Abstract: A vacuum hermetic organic packaging carrier is provided. The organic packaging carrier includes an organic substrate, a conductive circuit layer, and an inorganic hermetic insulation film. The organic substrate has a first surface. The conductive circuit layer is located on the first surface and exposes a portion of the first surface. The inorganic hermetic insulation film at least covers the exposed first surface to achieve an effect of completely hermetically sealing the organic packaging carrier.

Abstract: Aspects of the invention are directed to laser patterning apparatus capable of performing laser patterning on a thin film formed on a flexible substrate with a good yield and a laser patterning method thereof. The thin film formed on the flexible substrate can be patterned by laser using a laser patterning apparatus that can include a processing stage that has a reference processing surface on which the flexible substrate having the thin film formed thereon is disposed, a wrinkle removing device that is configured as a mechanism for stretching an outer periphery of a processing region of the flexible substrate so that tension is applied outward in the width direction and forward and backward in the transporting direction, and a laser scanner that scans a predetermined line of the thin film formed on the flexible substrate while emitting a laser beam thereto.

Abstract: A manufacturing method of a package structure is provided. In the manufacturing method, a metal substrate having a seed layer is provided. A patterned circuit layer is formed on a portion of the seed layer. A first patterned dry film layer is formed on the other portion of the seed layer. A surface treatment layer is electroplated on the patterned circuit layer with use of the first patterned dry film layer as an electroplating mask. The first patterned dry film layer is removed. A chip bonding process is performed to electrically connect a chip to the surface treatment layer. An encapsulant is formed on the metal substrate. The encapsulant encapsulates the chip, the surface treatment layer, and the patterned circuit layer. The metal substrate and the seed layer are removed to expose a bottom surface of the encapsulant and a lower surface of the patterned circuit layer.

Abstract: A method of molding a semiconductor package includes coating liquid molding resin or disposing solid molding resin on a top surface of a semiconductor chip arranged on a substrate. The solid molding resin may include powdered molding resin or sheet-type molding resin. In a case where liquid molding resin is coated on the top surface of the semiconductor chip, the substrate is mounted between a lower molding and an upper molding, and then melted molding resin is filled in a space between the lower molding and the upper molding. In a case where the solid molding resin is disposed on the top surface of the semiconductor chip, the substrate is mounted on a lower mold and then the solid molding resin is heated and melts into liquid molding resin having flowability. An upper mold is mounted on the lower mold, and melted molding resin is filled in a space between the lower molding and the upper molding.

Abstract: A module includes a substrate including a first copper surface and a semiconductor chip. The module includes a first sintered joint bonding the semiconductor chip directly to the first copper surface.

Abstract: A semiconductor device includes a support plate having a hole formed therein and a conductor formed on a wall surface of the hole, a semiconductor element; and a conductive post formed by a conductor having a first end portion at one end, and a second end portion at an other end. The second end portion of the conductive post is connected to the semiconductor element, and a side surface of the conductive post is fixed to the conductor on the wall surface of the hole deformed by pressing force of the conductive post on a side closer to the first end portion than the second end portion.

Abstract: An integrated circuit package includes a package module including one or more circuit interconnections formed in a carrier, wherein at least one top-side package contact is formed over the top-side of the package module and electrically connected to at least one circuit interconnection of the one or more circuit interconnections and wherein a cavity is formed at the top-side of the package module; a chip disposed in the cavity, the chip including at least one chip front side contact and at least one chip back side contact, wherein the at least one chip front side contact is electrically connected to at least one further circuit interconnection of the one or more circuit interconnections; an electrically conductive structure connecting the at least one top-side package contact to the chip back side contact; and a metallic layer formed over the electrically conductive structure and on the chip back side contact.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate with a projection formed along a perimeter of a first surface of the substrate; mounting an integrated circuit over the first surface; forming a protruding interconnect over the first surface between the projection and the integrated circuit; and forming an underfill between the integrated circuit and the projection with a uniform height, the uniform height of the underfill less than a height of the projection.

Abstract: A method includes applying a polymer-comprising material over a carrier, and forming a via over the carrier. The via is located inside the polymer-comprising material, and substantially penetrates through the polymer-comprising material. A first redistribution line is formed on a first side of the polymer-comprising material. A second redistribution line is formed on a second side of the polymer-comprising material opposite to the first side. The first redistribution line is electrically coupled to the second redistribution line through the via.

Abstract: The present invention provides a semiconductor device which is formed at low cost and has a great versatility, a manufacturing method thereof, and further a semiconductor device with an improved yield, and a manufacturing method thereof. A structure, which has a base including a plurality of depressions having different shapes or sizes, and a plurality of IC chips which are disposed in the depressions and which fit the depressions, is formed. A semiconductor device which selectively includes a function in accordance with an application, by using the base including the plurality of depressions and the IC chips which fit the depressions, can be manufactured at low cost.

Abstract: Various semiconductor chip package substrates with reinforcement and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes providing a package substrate that has a first side and a second side opposite to the first side. The first side has a central area adapted to receive a semiconductor chip. A solder reinforcement structure is formed on the first side of the package substrate outside of the central area to resist bending of the package substrate.

Abstract: The present invention relates to the field of electronic devices and their associated driver and/or controller integrated circuits and in particular to the mechanical packaging of electronic devices and to the packaging of electronic devices and their associated driver and/or controller integrated circuits.

Abstract: Disclosed is a light emitting device. The light emitting device comprises a light emitting semiconductor layer comprising a first conductive semiconductor layer, an active layer and a second conductive semiconductor layer, a first passivation layer on the light emitting semiconductor layer, and a second passivation layer on the first passivation layer and has an elastic modulus of 2.0 to 4.0 GPa.

Abstract: A support substrate includes a first surface and a second surface located above the level of the first surface. Chips are mounted on the first surface. A first insulating film is disposed over each chip. First conductive plugs are connected to the chip extending through each first insulating film. Filler material made of resin filling a space between chips. Wirings are disposed over the first insulating film and the filler material for interconnecting different chips. The second surface, an upper surface of the first insulating film and an upper surface of the filler material are located at the same level.

Abstract: Methods of forming pre-encapsulated frames comprise flowing a dielectric encapsulation material around at least one conductive trace. A cavity configured to receive at least one semiconductor device at least partially in the cavity is formed in the encapsulation material. A first connection area of the at least one trace is exposed within the cavity. At least another connection area of the at least one trace is exposed laterally adjacent to the cavity. The dielectric encapsulation material is hardened to form a pre-encapsulated frame.

Abstract: A semiconductor package for quickly discharging heat and a method for fabricating the same are disclosed. The semiconductor package includes a semiconductor package module having a first insulation member and at least one fluid passage passing through the insulation member. Circuit patterns are formed on a first face of the first insulation member. Semiconductor chips are then disposed on the first face and are electrically connected with the circuit patterns respectively. A second insulation member is formed so as to surround the side faces of the semiconductor chips, the first insulation member, and the circuit patterns. Finally, a through electrode is formed passing through the second insulation member of the semiconductor package module and electrically connecting to the circuit patterns.

Abstract: The occurrence of a resin seal failure is suppressed. A molding step is carried out using a lead frame in which there are formed multiple air vent portions for discharging gas in each cavity formed in the upper die of a molding die to outside the cavity. The air vent portions are formed at positions overlapping with the other corner portions, arranged inside a gate portion of the cavity. Each of the air vent portions is led out from the other corner portions of the cavity to outside a clamp area and is extended along sides of the cavity, respectively, in the clamp area.

Abstract: A structure of an integrated circuit module includes a wiring board, a plurality of integrated circuits and at least one terminating resistance circuit. The wiring board has a mounting region on at least one surface thereof. The plurality of integrated circuits are mounted in the mounting region of the wiring board and spaced from one another in a first direction. The at least one terminating resistance circuit is arranged between at least two adjacent integrated circuits, and coupled to an output of a last of the plurality of integrated circuits.

Abstract: In order to increase the probability that the component is disposed on the hydrophilic region, used is a substrate comprises a water-repellant region, a hydrophilic region, and a hydrophilic line, wherein the water-repellant region surrounds the hydrophilic region and the hydrophilic line, the hydrophilic region and the hydrophilic line are disposed along the +X direction in this order, the value of D1/D2 is not less than 0.1 and not more than 1.2, the value of D3 is not less than 5 micrometers, the value of D4 is less than the minimum length of the component.

Abstract: A structure and method for cold weld compression bonding using a metallic nano-structured gasket is provided. This structure and method allows a hermetic package to be formed at lower pressures and temperatures than are possible using bulk or conventional thin-film gasket materials.

Abstract: Hardness of bonding end portions of an external connection terminal to be bonded to circuit patterns of an insulating substrate which is not lower than 90 in Vickers hardness is disclosed. An ultrasonic welding tool is used. In the external connection terminal in which the bonding end portions are provided integrally with a bar, one of the bonding end portion located substantially in the lengthwise center of the bar is first bonded, and the other bonding end portions are bonded alternately in order toward either end. The hardness of the bonding end portions is increased so that strength of the ultrasonic welding portions is increased.

Abstract: It is aimed at improving the reliability of a semiconductor device. In a POP having an upper package stacked on a lower package, an opening of a first solder resist film in a first region between a first group of lands arranged at the periphery of an front surface of a wiring substrate of the lower package and a second group of lands arranged in a central part is filled with a second solder resist film, and thereby the formation of a starting point of cracks in the opening becomes unlikely to suppress occurrence of cracks and improve the reliability of the POP.

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a cavity in a carrier material, attaching a die in the cavity, wherein a backside of the die comprises a metal filled DBF, forming a dielectric material adjacent the die and on a bottom side of the carrier material, forming a coreless substrate by building up layers on the dielectric material, and removing the carrier material from the coreless substrate.

Abstract: A method for manufacturing a semiconductor package includes the steps of forming first circuit patterns on an upper surface of a carrier substrate. Bumps are formed in recesses defined on the upper surface of the carrier substrate. An insulation layer is formed on the upper surface of the carrier substrate to cover the first circuit patterns. Second circuit patterns are formed on an upper surface of the insulation layer so as to be electrically connected with the first circuit patterns. The carrier substrate is then separated from the insulation layer.

Abstract: A method of manufacturing a ball grid array, BGA, integrated circuit package, comprising forming a double sided printed circuit board, PCB, with blind vias interconnecting electrically the circuits on the opposed surfaces of the PCB, with at least one through-hole to allow fluid or gas to pass through the PCB, and an integrated circuit connected to the printed circuit on one side of the PCB; soldering a lid onto the said one side of the PCB to enclose the integrated circuit, whilst allowing thermally expanding gas or fluid to escape through the or each through-hole, whereby to form a package which is hermetically sealed except for the or each through-hole, and which has a cavity between the integrated circuit and the lid; applying a BGA to the side of the PCB opposed to the said one side, whereby to solder the balls of the BGA to respective portions of the printed circuit and to align one of the balls axially with each through-hole; and soldering the ball or balls into the through-hole, or into each respectiv

Abstract: A microelectronic package is provided. The microelectronic package includes a substrate having a plurality of solder bumps disposed on a top side of the substrate and a die disposed adjacent to the top side of the substrate. The die includes a plurality of glassy metal bumps disposed on a bottom side of the die wherein the plurality of glassy metal bumps are to melt the plurality of solder bumps to form a liquid solder layer. The liquid solder layer is to attach the die with the substrate.

Abstract: Various embodiments of semiconductor assemblies with multi-level substrates and associated methods of manufacturing are described below. In one embodiment, a substrate for carrying a semiconductor die includes a first routing level, a second routing level, and a conductive via between the first and second routing levels. The conductive via has a first end proximate the first routing level and a second end proximate the second routing level. The first routing level includes a terminal and a first trace between the terminal and the first end of the conductive via. The second routing level includes a second trace between the second end of the conductive via and a ball site. The terminal of the first routing level and the ball site of the second routing level are both accessible for electrical connections from the same side of the substrate.

Abstract: A semiconductor device has a carrier. A first semiconductor die is mounted to the carrier with an active surface of the first semiconductor die oriented toward the carrier. A dam structure is formed on the carrier and around the first semiconductor die by depositing dam material on the carrier with screen printing, electrolytic plating, electroless plating, or spray coating. An encapsulant is deposited over the carrier and around the first semiconductor die. The encapsulant has a coefficient of thermal expansion (CTE) that corresponds to a CTE of the dam material. The CTE of the dam material is equal to or less than the CTE of the encapsulant. The carrier is removed to expose the active surface of the first semiconductor die with the dam structure stiffening a periphery of the first semiconductor die. The semiconductor device is singulated through the dam structure.

Abstract: A resin sealing method of a semiconductor device includes: positioning semiconductor devices at predetermined positions of an adhesive layer formed on a support body and adhering the semiconductor devices thereto, sealing a part of each of the semiconductor devices with resin by curing a first seal resin in a fluidization state so as to fix the semiconductor devices adhered to the predetermined positions of the adhesive layer formed on the support body, setting the semiconductor devices fixed to the predetermined positions of the adhesive layer formed on the support body in a mold and sealing the exposure parts of the semiconductor devices exposed from the first seal resin with a second seal resin, and removing the support body and the adhesive layer from the semiconductor devices sealed with the resin.

Abstract: A flip chip interconnect of a die on a substrate is made by mating the interconnect bump onto a narrow interconnect pad on a lead or trace, rather than onto a capture pad. The width of the narrow interconnect pad is less than a base diameter of bumps on the die to be attached. Also, a flip chip package includes a die having solder bumps attached to interconnect pads in an active surface, and a substrate having narrow interconnect pads on electrically conductive traces in a die attach surface, in which the bumps are mated onto the narrow pads on the traces.

Abstract: A wired circuit board assembly sheet has a plurality of wired circuit boards, distinguishing marks for distinguishing defectiveness of the wired circuit boards, and a supporting sheet for supporting the plurality of wired circuit boards and the distinguishing marks. Each of the distinguishing marks has an indication portion for indicating a specified one of the wired circuit boards.

Abstract: The present invention provides a MEMS structure comprising confined sacrificial oxide layer and a bonded Si layer. Polysilicon stack is used to fill aligned oxide openings and MEMS vias on the sacrificial layer and the bonded Si layer respectively. To increase the design flexibility, some conductive polysilicon layer can be further deployed underneath the bonded Si layer to form the functional sensing electrodes or wiring interconnects. The MEMS structure can be further bonded to a metallic layer on top of the Si layer and the polysilicon stack.

Abstract: The present invention provides a SOI substrate that can realize a composite device formed of a MOS integrated circuit and a passive device and can reduce a size and a manufacturing cost of a semiconductor device. There is provided a fiber SOI substrate 5 comprising a fiber 1 with a polygonal cross section, and a semiconductor thin film 3 crystallized after film formation on at least one surface of the fiber 1, and a plurality of grooves 8 that extend in a linear direction of the fiber 1 and are arranged at intervals in a width direction are formed on a surface of the fiber 1.

Abstract: An electronic unit is produced including at least one electronic component at least partially embedded in an insulating material. A film assembly is provided with at least one conductive layer and a carrier layer. The conductive layer includes openings in the form of holes for receiving bumps, which are connected to contact surfaces of the at least one electronic component. The at least one component is placed on the film assembly such that the bumps engage with the openings of the conductive layer. The at least one component is partially embedded from the side opposite of the bumps into a dielectric layer. The carrier layer of the film assembly is removed such that the surface of the bumps is exposed. A metallization layer is then deposited on the side of the remaining conductive layer having the exposed bumps and so as to produce conductor tracks that overlap with the bumps.

Abstract: An assembly of substrate packages interconnected with flex cables and a method of fabrication of the substrate package. The assembly allows input/output (I/O) signals to be speedily transmitted between substrate packages via flex cable and without being routed through the motherboard. Embodiments relate to a substrate package providing separable inter-package flex cable connection. Hermetically-sealed guiding through holes are provided on the substrate package as a mechanical alignment feature to guide connection between flex cables and high speed I/O contact pads on the substrate package. Embodiments of the method of fabrication relate to simultaneously forming hermetically-sealed guiding through holes and I/O contact pads.

Abstract: A mounting substrate for a processor includes a die side and a land side with a processor footprint configured on the die side. The processor footprint is coupled to at least one processor interconnect and a microelectronic die is embedded in the mounting substrate. The microelectronic die is coupled to the processor interconnect and communication between a processor to be installed on the processor footprint is in a rate between 10 Gb/s and 1 Tb/s.

Abstract: A method for forming an integrated circuit includes transforming at least a portion of a first substrate layer to form a conductive region within the first substrate layer. An integrated circuit device is provided proximate an outer surface of the first substrate layer. The integrated circuit device transmits or receives electrical signals through the conductive region. A second substrate layer is disposed proximate to the outer surface of the first substrate layer to enclose the integrated circuit device in a hermetic environment.

Abstract: A conductor having a projecting portion is formed which forms a terminal portion. An uncured prepreg including a reinforcing material is closely attached to the conductor and the prepreg is cured to form an insulating film including the reinforcing material. When the prepreg is closely attached, the prepreg is stretched by the projecting portion, so that a region of the prepreg, which is closely attached to the conductor, can be thinner than the other region of the prepreg. Then, by reducing the thickness of the entire insulating film, an opening can be formed in the portion having a smaller thickness. The step of reducing the thickness can be performed by etching. Further, it is preferable not to remove the reinforcing material in this step. The strength of a terminal and an electronic device can be increased by leaving the reinforcing material at the opening.

Abstract: A method of making a stackable semiconductor assembly that includes a semiconductor device, a heat spreader, an adhesive, a terminal, a plated through-hole and build-up circuitry is disclosed. The heat spreader includes a bump, a base and a flange. The bump defines a cavity. The semiconductor device is mounted on the bump at the cavity, electrically connected to the build-up circuitry and thermally connected to the bump. The bump extends from the base into an opening in the adhesive, the base extends vertically from the bump opposite the cavity and the flange extends laterally from the bump at the cavity entrance. The build-up circuitry provides signal routing for the semiconductor device. The plated through-hole provides signal routing between the build-up circuitry and the terminal. The heat spreader provides heat dissipation for the semiconductor device.

Abstract: A method of manufacturing a hybrid integrated circuit device of the present invention includes the steps of preparing a lead frame which constituted by units each having a plurality of leads, and fixing a circuit substrate on each unit of the lead frame by fixing pads which are formed on the surface of the circuit substrate to the leads, where a space between a first pad which is formed at an end edge of the circuit substrate and a second pad which is adjacent to the first pad is set narrower than a space between the pads themselves.

Abstract: An electronic component has a substrate, a die bonding pad provided on an upper surface of the substrate, a semiconductor element bonded onto the die bonding pad by a die bonding resin, a conductive pattern disposed adjacent to the die bonding pad, and a coating member covering the conductive pattern. At least an outer peripheral portion of a surface of the die bonding pad is made of an inorganic material. The inorganic material of the outer peripheral portion is exposed. The die bonding pad and the conductive pattern are separated by an air gap such that the coating member does not come into contact with the die bonding pad.

Abstract: A 3D interposer (and method of making same) that includes a crystalline substrate handler having opposing first and second surfaces, with a cavity formed into the first surface. A layer of insulation material is formed on the surface of the handler that defines the cavity. The cavity is filled with a compliant dielectric material. A plurality of electrical interconnects is formed through the interposer. Each electrical interconnect includes a first hole formed through the crystalline substrate handler extending from the second surface to the cavity, a second hole formed through the compliant dielectric material so as to extend from and be aligned with the first hole, a layer of insulation material formed along a sidewall of the first hole, and conductive material extending through the first and second holes.

Abstract: A packaged microelectronic element includes a microelectronic element having a front surface and a plurality of first solid metal posts extending away from the front surface. A substrate has a major surface and a plurality of conductive elements exposed at the major surface and joined to the first solid metal posts. In particular examples, the conductive elements can be bond pads or can be second posts having top surfaces and edge surfaces extending at substantial angles away therefrom. Each first solid metal post includes a base region adjacent the microelectronic element and a tip region remote from the microelectronic element, the base region and tip region having respective concave circumferential surfaces. Each first solid metal post has a horizontal dimension which is a first function of vertical location in the base region and which is a second function of vertical location in the tip region.

Abstract: One embodiment of a semiconductor package described herein includes a substrate having a first through-hole extending therethrough; a conductive pattern overlying the substrate and extending over the first through-hole; a first semiconductor chip facing the conductive pattern such that at least a portion of the first semiconductor chip is disposed within the first through-hole; and a first external contact terminal within the first through-hole and electrically connecting the conductive pattern to the first semiconductor chip.

Abstract: The invention relates to a semiconductor arrangement and method for production thereof, wherein the semiconductor arrangement is provided with an integrated circuit arranged on a substrate. The integrated circuit is structured on the front face of the substrate and at least one capacitor is connected to the integrated circuit, wherein the at least one capacitor is designed as a monolithic deep structure in trenches. The trenches are arranged in at least one first group and at least one second group, the trenches of a group running essentially parallel to each other and the first and second group are at an angle to each other, essentially at right angles to each other.

Abstract: A method for manufacturing a printed wiring board includes forming an uncalcined layer containing a raw ceramic material on a first metal layer, firing the uncalcined layer formed on the first metal layer such that a high dielectric constant layer having a ceramic body calcined in a sheet form is formed on the first metal layer, forming a second metal layer on the high dielectric constant layer on the opposite side of the high dielectric constant layer with respect to the first metal layer such that a layered capacitor having the high dielectric constant layer and first and second layer electrodes sandwiching the high dielectric constant layer is formed, and disposing the layered capacitor in a main body.

Abstract: A chip is bonded onto a flat face of a first support through a first bonding layer with a terminal surface of the chip turned toward the flat face of the first support. A second support is bonded onto the chip through a second bonding layer. The first support is peeled from the chip to expose the terminal surface of the chip. An insulating layer from which the terminal surface of the chip is exposed is formed on the second support.

Abstract: A method for manufacturing an MEMS device is provided. The method includes steps of a) providing a first substrate having a concavity located thereon, b) providing a second substrate having a connecting area and an actuating area respectively located thereon, c) forming plural microstructures in the actuating area, d) mounting a conducting element in the connecting area and the actuating area, e) forming an insulating layer on the conducting element and f) connecting the first substrate to the connecting area to form the MEMS device. The concavity contains the plural microstructures.

Abstract: In a multilayered wiring board constituted by laminating to form pluralities of layers of wiring layers 105, 108, 110 and insulating layers 104, 106, 107, in the plurality of laminated insulating layers 104, 106, 107, the insulating layer 106 disposed at a laminating center in a laminating direction is made to constitute an insulating layer with a reinforcing member including a reinforcing member.