Abstract: A semiconductor package assembly is provided. The semiconductor package assembly includes a first semiconductor package. The first semiconductor package includes a first semiconductor die. A first redistribution layer (RDL) structure is coupled to the first semiconductor die and includes a first conductive trace. The semiconductor package assembly also includes a second semiconductor package bonded to the first semiconductor package. The second semiconductor package includes a second semiconductor die. An active surface of the second semiconductor die faces an active surface of the first semiconductor die. A second RDL structure is coupled to the second semiconductor die and includes a second conductive trace. The first conductive trace is in direct contact with the second conductive trace.

Abstract: Methods and systems for automatically generating robust metrology targets which can accommodate a variety of lithography processes and process perturbations. Individual steps of an overall lithography process are modeled into a single process sequence to simulate the physical substrate processing. That process sequence drives the creation of a three-dimensional device geometry as a whole, rather than “building” the device geometry element-by-element.

Abstract: There is provided a method for laminating a smooth thin resin layer on a substrate in manufacturing a liquid ejection head by a casting method. To achieve this, a resin layer having a sufficient thickness to fill a concave portion already existing on the substrate is applied and smoothed. Thereafter, a plurality of opening patterns (concave portions) are formed and then smoothed again to obtain a thin resin layer having a desired thickness.

Abstract: The modeling of a DSA step within a virtual fabrication process sequence for a semiconductor device structure is discussed. A 3D model is created by the virtual fabrication that represents and depicts the possible variation that can result from applying the DSA step as part of the larger fabrication sequence for the semiconductor device structure of interest. Embodiments capture the relevant behavior caused by polymer segregation into separate domains thereby allowing the modeling of the DSA step to take place with a speed appropriate for a virtual fabrication flow.

Abstract: The present disclosure relates to semiconductor manufacturing, in particular to a real-time method for qualifying the etch rate for plasma etch processes. A method for testing a semiconductor plasma etch chamber may include: depositing a film on a substrate of a wafer, the wafer including a center region and an edge region; depositing photoresist on top of the film in a pattern that isolates the center region from the edge region of the wafer; and performing an etch process on the wafer that includes at least three process steps. The three process steps may include: etching the film in any areas without photoresist covering the areas until a first clear endpoint signal is achieved; performing an in-situ ash to remove any photoresist; and etching the film in any areas exposed by the removal of the photoresist until a second clear endpoint is achieved.

Abstract: A system and method relate to calculating a first edge map associated with a reference video frame, generating a second edge map associated with an incoming video frame, generating an offset between the reference video frame and the video frame based on a first frequency domain representation of the first edge map and a second frequency domain representation of the second edge map, translating locations of a plurality of pixels of the incoming video frame according to the calculated offset to align the incoming video frame with respect to the reference video frame, and transmitting the aligned video frame to a downstream device.

Abstract: The present invention provides a method for analyzing defects by using heat distribution measurement, comprising: a sample loading unit for loading a sample to check whether or not there is a defect through heat distribution characteristics; a light source for radiating visible light onto the sample; a power supply unit for generating a driving signal in order to periodically heat the sample; a detection unit for detecting reflected light from the surface of the sample; and a signal generator for synchronizing the detection unit with the driving signal of the power supply unit.

Abstract: A pattern forming method includes forming a spin on dielectric film on a substrate, washing the spin on dielectric film by using a washing liquid, drying a surface of the spin on dielectric film after the washing, forming a photosensitive film on the dried coating type insulation film, emitting energy rays to a predetermined position of the photosensitive film in order to form a latent image on the photosensitive film, developing the photosensitive film in order to form a photosensitive film pattern which corresponds to the latent image, and processing the spin on dielectric film with the photosensitive film pattern serving as a mask.

Abstract: A method for examining a mask includes providing a position data set having error positions of the mask to be examined, providing a structure data set having the structure of the mask, and specifying structural features of the mask, the values of which are to be determined. At each error position, determining the values of the specified structural features of the structure by using a computing unit, determining a measuring task from specified decision criteria and from the determined values of the structural features of the structure by using the computing unit, and carrying out the determined measuring task in a manner controlled by the computing unit. In addition, a device, in particular a microscope, for carrying out the method is provided.

Abstract: In a vacuum vapor deposition method which is carried out at a vacuum vapor deposition apparatus including a plurality of linear-shaped vaporization sources, an equal-thickness surface is calculated with respect to each of a polarity of release holes. The equal-thickness surface indicates a surface where a deposition amount of vapor of a vaporization material released from the corresponding release hole is the same per unit time. Then, the vaporization containers are placed in such a manner that contact points of the equal-thickness surfaces all coincide with each other on a deposition surface of a substrate, each of the contact points being where the corresponding equal-thickness surface comes in contact with the surface of the substrate.

Abstract: Laser modules are provided having electrical connections that are resistant to damage caused by transient or higher order accelerations.

Abstract: Techniques relate to dynamic complex fault model generation for diagnostics simulation and pattern generation. Inline fabrication parametric data is received, and the inline fabrication parametric data is a collection of physical measurements made on a device under test during a manufacturing fabrication of the device under test. A fault model of defects is generated according to the inline fabrication parametric data, where the fault model is based on a physical design of the device under test combined with the inline fabrication parametric data for the device under test. Test patterns are generated based on the fault model and the inline fabrication parametric data, such that the test patterns are configured to test the device under test in order to obtain results that are based on the inline fabrication parametric data. A simulation is run of the device under test using the results and the inline fabrication parametric data.

Abstract: Disclosed are apparatus and methods for performing small angle x-ray scattering metrology. This system includes an x-ray source for generating x-rays and illumination optics for collecting and reflecting or refracting a portion of the generated x-rays towards a particular focus point on a semiconductor sample in the form of a plurality of incident beams at a plurality of different angles of incidence (AOIs). The system further includes a sensor for collecting output x-ray beams that are scattered from the sample in response to the incident beams on the sample at the different AOIs and a controller configured for controlling operation of the x-ray source and illumination optics and receiving the output x-rays beams and generating an image from such output x-rays.

Abstract: A method of forming an electrode pattern includes: forming, on a base material, a seed layer having a pattern corresponding to the electrode pattern; forming an organic material layer on the seed layer; producing an electrode layer transfer sheet by forming an electrode layer on the organic material layer via an electroplating process using the seed layer as a seed; disposing the electrode layer transfer sheet on a substrate on which the electrode pattern is to be formed such that the electrode layer is in contact with the substrate and pressure bonding the electrode layer to the substrate; and in a state in which the electrode layer is pressure bonded to the substrate, removing the base material along with the organic material layer and the seed layer to transfer the electrode layer to the substrate.

Abstract: A method for manufacturing a semiconductor device includes forming a plurality of mandrels on a dielectric layer, conformally depositing a spacer layer on the plurality of mandrels, removing a portion of the spacer layer from a top surface of at least one of the plurality of mandrels, removing the at least one of the plurality of mandrels to create at least one opening, and filling the at least opening with a cut fill material, wherein the cut fill material comprises the same material as a material of the spacer layer.

Abstract: A wafer processing method including the steps of storing information on the intervals and positions of metal patterns formed on part of division lines on a wafer into a storage unit of a cutting apparatus, detecting the division lines, forming a cut groove along each division line by using a cutting blade, imaging an area including the cut groove at any position where the metal patterns are not formed, by using an imaging unit included in the cutting apparatus, according to the information on the intervals and positions of the metal patterns previously stored, during the step of forming the cut grooves, and measuring the positional relation between the position of the cut groove and a preset cutting position. Accordingly, kerf check can be performed without being influenced by burrs produced from the metal patterns in cutting the wafer, so that the wafer can be cut with high accuracy.

Abstract: A computer-implemented method for identifying a first object-of-interest is provided. The first object-of-interest includes two identifiers and a sample portion. The method includes imaging the first object-of-interest including the two identifiers. The imaging generates a first set of image data. The method further includes determining a position of the first object-of-interest in the field-of-view of an optical sensor and determining the two identifiers from the first set of image data. The method includes identifying the first object-of-interest based on the two identifiers.

Abstract: A method of modeling the temperature profile of an IC transistor junction employs an efficient thermal simulation algorithm to implement a design tool for IC design applications. The junction area of a transistor is divided into an odd number of sub-sections of equal size. Each sub-section is modeled as an equivalent circular heat source having an area equal to that of a sub-section. Temperature profiles are determined for each of the equivalent circular heat sources, which are superimposed to provide a total thermal profile for the junction. The method is preferably employed with rectangular-shaped junction areas, and performed with a software-controlled microprocessor. The method may be integrated with an electronic circuit simulation program such as SPICE. The results of the modeling may be used to iteratively modify the component layout on an IC to improve its temperature performance and/or its component density.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes operations below. First, an epitaxial layer is formed on a substrate. Then, a trench is formed in the epitaxial layer. Then, a first dielectric layer and a shield layer are formed in the trench, in which the shield layer is embedded within the first dielectric layer. Then, a spacer layer is formed in the trench and on the first dielectric layer. Finally, a second dielectric layer and a gate are formed in the trench and on the spacer layer, and a source is formed in the epitaxial layer surrounding the trench, in which the gate is embedded within the second dielectric layer, and the source surrounds the gate.

Abstract: A semiconductor processing method is provided and includes the following steps. A first semiconductor process is performed for a wafer to obtain plural overlay datum (x, y), wherein x and y are respectively shift values in X-direction and Y-direction. Next, A re-correct process is performed by a computer, wherein the re-correct process comprises: (a) providing an overlay tolerance value (A, B) and an original out of specification value (OOS %), wherein A and B are respectively predetermined tolerance values in X-direction and Y-direction; (b) providing at least a k value (kx, ky); (c) modifying the overlay datum (x, y) according to the k value (kx, ky) to obtain at least a revised overlay datum (x?, y?); and (d) calculating a process parameter from the revised overlay datum (x?, y?). Lastly, a second semiconductor process is performed according to the process parameter . . . . The present invention further provides a lithography system.

Abstract: Methods and apparatus for providing measurements in p-n junctions and taking into account the lateral current for improved accuracy are disclosed. The lateral current may be controlled, allowing the spreading of the current to be reduced or substantially eliminated. Alternatively or additionally, the lateral current may be measured, allowing a more accurate normal current to be calculated by compensating for the measured spreading. In addition, the techniques utilized for controlling the lateral current and the techniques utilized for measuring the lateral current may also be implemented jointly.

Abstract: Laser modules are provided having electrical connections that are resistant to damage caused by transient or higher order accelerations.

Abstract: A method and system includes a bill of materials stored on a computer readable storage device, listing multiple components to be assembled. A mapping table is stored on a computer readable storage device having rows listing attributes of components of the bill of materials and a routing operation attribute identifying work centers or another unique attribute. A plurality of routing templates stored on a computer readable storage device, the routing templates identifying work centers and routing operations between work centers. A route generator utilizes the mapping table to map components from the bill of materials to a routing template and its operations.

Abstract: A system and method of compensating for local focus errors in a semiconductor process. The method includes providing a reticle and applying, at a first portion of the reticle, a step height based on an estimated local focus error for a first portion of a wafer corresponding to the first portion of the reticle. A multilayer coating is formed over the reticle and an absorber layer is formed over the multilayer coating. A photoresist is formed over the absorber layer. The photoresist is patterned, an etch is performed of the absorber layer and residual photoresist is removed.

Abstract: Shadow-grams are used for edge inspection and metrology of a stacked wafer. The system includes a light source that directs collimated light at an edge of the stacked wafer, a detector opposite the light source, and a controller connected to the detector. The stacked wafer can rotate with respect to the light source. The controller analyzes a shadow-gram image of the edge of the stacked wafer. Measurements of a silhouette of the stacked wafer in the shadow-gram image are compared to predetermined measurements. Multiple shadow-gram images at different points along the edge of the stacked wafer can be aggregated and analyzed.

Abstract: Semiconductor devices and back side illumination (BSI) sensor manufacturing methods are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes providing a workpiece and forming an integrated circuit on a front side of the workpiece. A grid of a conductive material is formed on a back side of the workpiece using a damascene process.

Abstract: An IC includes first and second designs of experiments (DOEs), each comprised of at least two fill cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). The first DOE contains fill cells configured to enable non-contact (NC) detection of tip-to-tip shorts, and the second DOE contains fill cells configured to enable NC detection of corner shorts.

Abstract: The present disclosure provides a semiconductor fabrication method. The method includes modifying an edge portion of a wafer such that the edge portion are prevented from resist coating; coating a resist layer on the front surface of the wafer, wherein the resist layer is free from the edge portion of the wafer; and performing an exposing process to the resist layer.

Abstract: In a method of calculating a shift value of a cell contact, a reference region and a correction region may be set on an image of an actual cell block. The cell block may include a plurality of actual cell contacts formed using a mask. Each of preliminary shift values of the actual cell contacts with respect to target cell contacts in a target cell block to be formed using the mask may be measured based on the image. The preliminary shift values of the actual cell contacts in the reference region may be minimized. Actual shift values of the actual cell contacts in the correction region with respect to the minimized preliminary shift values may be calculated. Thus, the mask may be corrected using the accurately measured shift values so that the cell contacts may have designed positions.

Abstract: A method for pixel patterning and pixel position inspection of an organic light-emitting display device includes: forming, on a substrate using a first mask, a thin film layer of a first color corresponding to a first pixel pattern and a first pixel positioning pattern for inspecting a position of a first pixel; shifting, by a determined pitch, the first mask from a position associated with forming the thin film layer of the first color; aligning the shifted first mask with respect to the substrate; and forming, on the substrate using the shifted first mask, a thin film layer of a second color corresponding to the first pixel pattern and another first pixel positioning pattern for inspecting a position of a second pixel.

Abstract: An integrated circuit structure includes a dielectric layer, and a conductive line in the dielectric layer. The conductive line has a first top surface and a second top surface lower than the first top surface, and a sidewall connecting the first top surface to the second top surface. A via includes a portion overlying the second top surface of the conductive line. The via is electrically coupled to the conductive line through the second top surface and the sidewall of the conductive line.

Abstract: A method of manufacturing a semiconductor device, includes forming a thin film containing silicon, oxygen and carbon or a thin film containing silicon, oxygen, carbon and nitrogen on a substrate by performing a cycle a predetermined number of times. The cycle includes supplying a precursor gas serving as a silicon source and a carbon source or a precursor gas serving as a silicon source but no carbon source, and a first catalyst gas to the substrate; supplying an oxidizing gas and a second catalyst gas to the substrate; and supplying a modifying gas containing at least one selected from the group consisting of carbon and nitrogen to the substrate.

Abstract: Method for manufacturing a bonded wafer, including implanting at least one gas ion into a bond wafer from a bond wafer surface forming an ion implantation layer, bonding the surface from the ion implantation into bond wafer and base wafer surface, and delaminating the bond wafer part along the ion implantation layer by heat treatment forming a bonded wafer having thin-film on the base wafer, wherein heat treatment is at most 400° C. to delaminate bond wafer part along the ion implantation layer, including measuring bond wafer thicknesses and base wafer, selecting a combination of bond and base wafers so difference between both wafers thicknesses is 5 ?m or more before bonding the bond and base wafers. Inhibition of film thickness unevenness with marble pattern caused in thin-film when a bonded wafer is manufactured by ion implantation delamination method, and can manufacture a bonded wafer having thin-film with high thickness uniformity.

Abstract: A method for performing a semiconductor parametric test comprising performing a full voltage sweep for a first component on a first semiconductor wafer to determine a first value of an electrical characterization parameter for the first component, wherein the full voltage sweep comprises a range between about a minimum input voltage level of the first component and about a maximum input voltage level of the first component, determining a smart sensing window (SSW) for a plurality of subsequent components on the first semiconductor wafer according to the first value, wherein the SSW comprises a range comprising a portion of the full voltage sweep range, performing a partial voltage sweep in the SSW for each of the subsequent components to determine a second value of the electrical characterization parameter for each of the subsequent semiconductor components, and adapting the SSW for at least some of the subsequent components.

Abstract: A method of manufacturing a silicon carbide semiconductor device includes a step of preparing a silicon carbide substrate having a first main surface and a second main surface located opposite to the first main surface, a step of forming a doped region in the silicon carbide substrate by doping the first main surface with an impurity, a step of forming a first protecting film on the doped region at the first main surface, and a step of activating the impurity included in the doped region by annealing with the first protecting film having been formed, the step of forming a first protecting film including a step of disposing a material which will form the first protecting film and in which the concentration of a metal element is less than or equal to 5 ?g/kg on the first main surface.

Abstract: An example provides an apparatus including a substrate, a metal layer, and an adhesive layer adhered between the substrate and the metal layer, the adhesive layer comprising indium oxide, tin oxide, gallium oxide, indium-tin oxide, indium-gallium oxide, tin-gallium oxide, or indium-tin-gallium oxide.

Abstract: Creation and maintenance of preferred or “gold” data sets are automated using objective, predefined rules or filters. The rules may be applied as part of a data publication workflow when new data becomes available in a database. The rules govern the type of data to be included in a gold data set, the currency of the data, the quality of the data, and the naming of the data. This helps reduce the amount of work required by users to create gold data sets and also ensures that the gold data set are up-to-date and high-value. The disclosed approach is particularly suited for use with data from hydrocarbon exploration and production related operations.

Abstract: A Zinc Oxide (ZnO) layer deposited using Atomic Layer Deposition (ALD) over a phase-change material forms a self-selected storage device. The diode formed at the ZnO/GST interface shows both rectification and storage capabilities within the PCM architecture.

Abstract: A method of placing a dummy fill layer on a substrate is disclosed (FIG. 2). The method includes identifying a sub-region of the substrate (210). A density of a layer in the sub-region is determined (212). A pattern of the dummy fill layer is selected to produce a predetermined density (216). The selected pattern is placed in the sub-region (208).

Abstract: Integrated circuits (1) on a wafer comprise a wafer substrate (2) and a plurality of integrated circuits (Ia, Ib, Ic) formed on the wafer substrate (2). Each integrated circuit (Ia, Ib, Ic) comprises an electric circuit (24) and some of the integrated circuits (Ib, Ic) comprise, in addition to their electric circuits (24), process control modules (3) as integral parts. The process control modules (3) are employed during dicing and pick-and-place to align the dicing/pick-and-place devices.

Abstract: In some embodiments, an field effect transistor structure includes a first semiconductor structure and a gate structure. The first semiconductor structure includes a channel region, and a source region and a drain region. The source region and the drain region are formed on opposite ends of the channel region, respectively. The gate structure includes a central region and footing regions. The central region is formed over the first semiconductor structure. The footing regions are formed on opposite sides of the central region and along where the central region is adjacent to the first semiconductor structure.

Abstract: Disclosed herein is a pre space transformer including: a substrate having a first surface and a second surface, which is an opposite surface to the first surface; individual electrodes disposed on the first surface; and common electrodes disposed in the substrate, wherein the individual electrodes are repeatedly disposed while configuring a unit pattern.

Abstract: Laser sub-divisional error (SDE) effect is compensated by using adaptive tuning. This compensated signal can be applied to position detection of stage in ebeam inspection tool, particularly for continuous moving stage.

Abstract: A system (10) for directly measuring the depth of a high aspect ratio etched feature on a wafer (80) that includes an etched surface (82) and a non-etched surface (84). The system (10) utilizes an infrared reflectometer (12) that in a preferred embodiment includes a swept laser (14), a fiber circulator (16), a photodetector (22) and a combination collimator (18) and an objective lens (20). From the objective lens (20) a focused incident light (23) is produced that is applied to the non-etched surface (84) of the wafer (80). From the wafer (80) is produced a reflected light (25) that is processed through the reflectometer (12) and applied to an ADC (24) where a corresponding digital data signal (29) is produced. The digital data signal (29) is applied to a computer (30) that, in combination with software (32), measures the depth of the etched feature that is then viewed on a display (34).

Abstract: Controlled recessing of materials in cavities and resulting devices are disclosed.

Abstract: An embodiment is a method including forming a fin on a substrate, forming a first doped region in a top portion of the fin, the first doped region having a first dopant concentration, and forming a second doped region in a middle and bottom portion of the fin, the second doped region having a second dopant concentration, the second dopant concentration being less than the first dopant concentration.

Abstract: The present disclosure relates to a method for manufacturing one or more optical engine packages, each optical engine package comprising a silicon photonic die. The method includes receiving a substrate comprising a package portion and a cutting area adjacent to the package portion, assembling the optical engine package on the substrate such that an edge-coupled waveguide of the silicon photonic die overlaps a boundary between the cutting area and the package portion, and cutting the optical engine package and the substrate in the cutting area to expose the edge-coupled waveguide for optical coupling thereof to an optical fiber core.

Abstract: A method and an apparatus for precisely detecting a trench S in a product W to become a thin film solar cell are provided. In the product W, a lower electrode layer 12, in which the trench S is created, and light absorbing layers 13 and 14 are layered on a substrate 11 in this order. The method includes the steps of: detecting infrared rays for imaging, of which the wavelengths are in such a range that can transmit through the light absorbing layers 13 and 14 and which are irradiated from the product W, by means of an infrared ray imaging apparatus 16 that is provided above the light absorbing layers 13 and 14 so that image data for radiation intensity distribution can be taken; and detecting the trench S in the lower electrode layer 12 on the basis of this image data for radiation intensity distribution.

Abstract: A method of manufacturing a semiconductor device includes forming a film on a substrate by performing a cycle a predetermined number of times. The cycle includes non-simultaneously performing: forming a first layer by supplying a precursor gas including a chemical bond of a first element and carbon and a first catalyst gas to the substrate; exhausting the precursor gas and the first catalyst gas through an exhaust system; forming a second layer by supplying a reaction gas including a second element and a second catalyst gas to the substrate to modify the first layer; and exhausting the reaction gas and the second catalyst gas through the exhaust system. At least in a specific cycle, the respective gases are supplied and confined in the process chamber while closing the exhaust system in at least one of the act of forming the first layer and the act of forming the second layer.

Abstract: The reliability of multipoint contact by a contact pin with an external terminal is improved while achieving an improvement in easiness of manufacture of the contact pin. The contact pin includes first and second contact pins. Further, the first contact pin has a support portion extending in a y direction and a tip portion connected to the support portion. The second contact pin also has a support portion extending in the y direction and a tip portion connected to the support portion. Here, the support portion of the first contact pin and the support portion of the second contact pin are arranged side by side along an x direction in a horizontal plane (xy plane). Further, the tip portion of the second contact pin is shifted from the tip portion of the first contact pin along the y direction in the horizontal plane, crossing (perpendicular to) the x direction.