With Measuring Or Testing Patents (Class 438/14)
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Patent number: 10516725Abstract: Roughly described, a technique for approximating a target property of a target material is provided. For each material in a plurality of anchor materials, a correspondence is provided between the value for a predetermined index property of the material and a value for the target property of the material, the values of all the index properties being different. A predictor function is identified in dependence upon the correspondence. A computer system determines a value for the target property for the target material in dependence upon the predictor function and a value for the index property for the target material. The determined value for the target property for the target material is reported to a user. The correspondence can be provided in a database on a non-transitory computer readable medium. The correspondence can be determined experimentally or analytically for each material in a plurality of anchor materials.Type: GrantFiled: September 26, 2014Date of Patent: December 24, 2019Assignee: SYNOPSYS, INC.Inventors: Victor Moroz, Stephen Lee Smith, Yong-Seog Oh, Jie Liu, Michael C. Shaughnessy-Culver, Terry Sylvan Kam-Chiu Ma
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Patent number: 10490614Abstract: A display device includes a thin film transistor, a gate insulting layer, an interlayer insulating layer, a data line, a spacer, and a pixel. The thin film transistor includes a semiconductor layer and a gate electrode. The semiconductor layer includes a source region and a drain region on respective sides of the channel region. The gate insulating layer is between the semiconductor layer and the gate electrode. The interlayer insulating layer covers the thin film transistor. The data line contacts the semiconductor layer via a hole passing through the gate insulating layer and the interlayer insulating layer. The spacer is on an inner wall of the hole and contacting the data line. The pixel electrode is electrically connected to the thin film transistor.Type: GrantFiled: October 10, 2017Date of Patent: November 26, 2019Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Subin Bae, Shinil Choi, Changok Kim, Chulmin Bae, Sanggab Kim, Sunghoon Yang, Yeoungkeol Woo, Yugwang Jeong
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Patent number: 10490458Abstract: A method includes forming a gate stack, which includes a gate dielectric and a metal gate electrode over the gate dielectric. An inter-layer dielectric is formed on opposite sides of the gate stack. The gate stack and the inter-layer dielectric are planarized. The method further includes forming an inhibitor film on the gate stack, with at least a portion of the inter-layer dielectric exposed, selectively depositing a dielectric hard mask on the inter-layer dielectric, with the inhibitor film preventing the dielectric hard mask from being formed thereon, and etching to remove a portion of the gate stack, with the dielectric hard mask acting as a portion of a corresponding etching mask.Type: GrantFiled: January 2, 2018Date of Patent: November 26, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsu-Hsiu Perng, Kai-Chieh Yang, Zhi-Chang Lin, Teng-Chun Tsai, Wei-Hao Wu
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Patent number: 10466596Abstract: The present disclosure is directed to a method of determining at least one correctable for a process tool. In an embodiment, the method includes the steps of: measuring one or more parameter values at one or more measurement locations of each field of a selection of measured fields of a wafer; estimating one or more parameter values for one or more locations of each field of a selection of unmeasured fields of the wafer; and determining at least one correctable for a process tool based upon the one or more parameter values measured at the one or more measurement locations of each field of the selection of measured fields of the wafer and the one or more parameter values estimated for the one or more locations of each field of the selection of unmeasured fields of the wafer.Type: GrantFiled: February 21, 2014Date of Patent: November 5, 2019Assignee: KLA-Tencor CorporationInventors: Bill Pierson, Ramkumar Karur-Shanmugam, Chin-Chou Huang, Ady Levy, John Charles Robinson
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Patent number: 10436829Abstract: A device for measuring electrical properties of electrical contacts within an electroplating apparatus has a disc-shaped structure like that of a wafer. Multiple conductive pads are formed to collectively circumscribe an outer periphery of the disc-shaped structure. Adjacently positioned ones of the conductive pads are electrically isolated from each other. The device includes a current source that supplies electric current at a first terminal and sinks electric current at a second terminal. The device includes measurement circuitry, having first and second input terminals, that determines a value of an electrical parameter based on signals present at the first and second input terminals. The device includes switching circuitry for connecting selected ones of the conductive pads to the first and second terminals of the current source and to the first and second input terminals of the measurement circuitry at a given time. The device also includes an onboard power supply.Type: GrantFiled: April 18, 2017Date of Patent: October 8, 2019Assignee: Lam Research CorporationInventors: Mark E. Emerson, Steven T. Mayer, Lawrence Ossowski
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Patent number: 10431708Abstract: An integrated circuit including ESD device is disclosed. One embodiment includes a semiconductor region being electrically isolated from adjacent semiconductor regions by an isolating region. Both an ESD device and a device configured to emit radiation are formed within the semiconductor region.Type: GrantFiled: September 22, 2015Date of Patent: October 1, 2019Assignee: Infineon Technologies AGInventors: Michael Mayerhofer, Joost Willemen, David Johnsson
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Patent number: 10422037Abstract: A film formation apparatus and a film formation method that can homogenize the distribution of gas in each zone in a chamber and improve film formation precision are provided. A film formation apparatus according to one embodiment includes: a chamber which includes a plurality of zones into which gas is introduced, and a plurality of discharge ports that discharge the gas located in at least any of the zones and that can individually adjust an opening state; and a transportation unit that transports a substrate so as to pass through the plurality of the zones in the chamber.Type: GrantFiled: March 13, 2017Date of Patent: September 24, 2019Assignee: TOPPAN PRINTING CO., LTD.Inventor: Masato Kon
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Patent number: 10409171Abstract: A process control system may include a controller configured to receive after-development inspection (ADI) data after a lithography step for the current layer from an ADI tool, receive after etch inspection (AEI) overlay data after an exposure step of the current layer from an AEI tool, train a non-zero offset predictor with ADI data and AEI overlay data to predict a non-zero offset from input ADI data, generate values of the control parameters of the lithography tool using ADI data and non-zero offsets generated by the non-zero offset predictor, and provide the values of the control parameters to the lithography tool for fabricating the current layer on the at least one production sample.Type: GrantFiled: January 10, 2018Date of Patent: September 10, 2019Assignee: KLA-Tencor CorporationInventors: Michael E. Adel, Amnon Manassen, William Pierson, Ady Levy, Pradeep Subrahmanyan, Liran Yerushalmi, DongSub Choi, Hoyoung Heo, Dror Alumot, John Charles Robinson
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Patent number: 10395933Abstract: A method for manufacturing a semiconductor wafer including: slicing off a plurality of wafers from an ingot; chamfering outer peripheral portions of the plurality of sliced wafers; and performing double-side polishing to polish both surfaces of each wafer whose outer peripheral portion is held by a carrier, wherein includes performing warp direction adjustment to uniform directions of warps of the plurality of wafers in one direction after the slicing and before the chamfering, and the chamfering and the double-side polishing are performed in a state where the directions of the warps of the plurality of wafers are uniformed in one direction after the warp direction adjustment. Consequently, it is possible to provide the method for manufacturing a semiconductor wafer which can suppress degradation of flatness of the double-side polished wafers even in case of uniforming the directions of the warps of the wafers in one direction before the double-side polishing.Type: GrantFiled: July 15, 2016Date of Patent: August 27, 2019Assignee: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Yoshihiro Usami, Shiro Amagai
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Patent number: 10388662Abstract: A manufacturing method of a semiconductor memory device includes disposing a first stacked body on a substrate, forming a first through via hole in the first stacked body, and determining to remove an upper portion of the first stacked body based on a comparison of a determined value of a width of the first through via hole with a reference value. The method further includes forming a second film in the first through via hole responsive to the determination to remove the upper portion of the first stacked body, removing the upper portion of the first stacked body and a portion of the second film, and disposing a second stacked body on the first stacked body and the second film. The method further includes forming a second through via hole to expose at least a portion of the second film, and removing the second film in the first through via hole.Type: GrantFiled: September 5, 2017Date of Patent: August 20, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Kazunori Horiguchi, Takashi Ohashi
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Patent number: 10365557Abstract: A method, system or computer usable program product for building a fast lithography OPC model that predicts semiconductor manufacturing process outputs on silicon wafers including providing a first principles model of the semiconductor manufacturing process, providing a set of empirical data for storage in memory, utilizing a processor to develop a rigorous model for a process condition from the first principles model and the set of empirical data, and utilizing the processor running the rigorous model to generate emulated data for the process condition to develop a virtual model for predicting the semiconductor manufacturing process outputs.Type: GrantFiled: February 19, 2014Date of Patent: July 30, 2019Assignee: SYNOPSYS, INC.Inventors: Artak Isoyan, Lawrence S. Melvin, III
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Patent number: 10356614Abstract: A secure element uses a backup context to restore a deleted electronic Subscriber Identity Module (eSIM) without compromising a trust relationship with a mobile network operator (MNO). A backup copy of a data binary large object (data blob) originally used to instantiate the eSIM is retrieved. The secure element determines if the eSIM within the data blob is uniquely associated with the secure element from a previous installation. The secure element examines the data blob to determine an identifier unique to the eSIM. The identifier can be an integrated circuit card identifier (ICC-ID) or a profile identifier. The secure element searches a table of instantiated eSIMs in the secure memory. If the secure element is able to match the recovered eSIM identifier with an entry in the table, then the secure element installs this eSIM in the secure element.Type: GrantFiled: November 18, 2016Date of Patent: July 16, 2019Assignee: Apple Inc.Inventors: Li Li, Arun G. Mathias
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Patent number: 10356391Abstract: 3D information may be extracted from two 2D images by capturing a first image of a sample at a first orientation. The sample may be titled at a second or different orientation, resulting in a second image of the titled sample to be captured. Third dimension of information may be extracted from the images.Type: GrantFiled: May 22, 2018Date of Patent: July 16, 2019Assignee: Triad National Security, LLCInventors: Benjamin P. Eftink, Stuart Andrew Maloy
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Patent number: 10345371Abstract: A method is provided for parameter extraction of a semiconductor device with a multi-finger gate. The method includes measuring gate-to-source and gate-to-drain capacitances and performing 3D simulation to compute fringing capacitances, thereby computing an overlap capacitance between the gate and a source/drain extension region, and computing a length of the source/drain extension region according to the overlap capacitance.Type: GrantFiled: November 15, 2016Date of Patent: July 9, 2019Assignee: NATIONAL CHIAO TUNG UNIVERSITYInventors: Jyh-Chyurn Guo, Yen-Ying Lin
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Patent number: 10345102Abstract: A method for evaluating warpage of a wafer, includes measuring the warpage of the wafer that is in a free state without suction and determining, from measured warpage data, a wafer warpage amount A between two points Q1 and Q2 and a wafer warpage amount B between two points R1 and R2, the points Q1 and Q2 being located on a straight line passing through an arbitrary point P in a wafer plane and a distance “a” away from the point P, the points R1 and R2 being located on the same straight line and a distance “b” away from the point P, the distance “b” differing from the distance “a”, calculating, from the wafer warpage amount A and the wafer warpage amount B, a difference in wafer warpage amount at the point P, and evaluating the warpage on the basis of the difference in wafer warpage amount.Type: GrantFiled: March 12, 2015Date of Patent: July 9, 2019Assignee: SHIN-ETSU HANDOTAI CO., LTD.Inventor: Hisayuki Saito
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Patent number: 10338132Abstract: The disclosed technology generally relates to integrated circuit devices with wear out monitoring. An integrated circuit device includes a core circuit and a wear-out monitor device. The wear-out monitor device configured to adjust an indication of wear out of the core circuit regardless of whether the core circuit is activated The integrated circuit further includes a sensing circuit coupled to the wear-out monitor device and configured to detect an electrical property of the wear-out monitor device that is indicative of a wear-out level of the core-circuit.Type: GrantFiled: October 12, 2016Date of Patent: July 2, 2019Assignee: Analog Devices GlobalInventors: Edward John Coyne, Alan J. O'Donnell, Colm Patrick Heffernan, Kevin B. Manning, Mark Forde, David J. Clarke, Thomas G. O'Dwyer, David Aherne, Michael A. Looby
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Patent number: 10331027Abstract: The present invention provides an imprint apparatus which performs an imprint process for forming a pattern on an imprint material on a substrate using a mold, the apparatus including an obtaining unit configured to obtain each shape of a plurality of shot regions on the substrate before the mold and the shot region as an imprint target on the substrate face each other, a first correction unit configured to correct, for each shot region on the substrate, a shape difference between a pattern of the mold and the shot region, a measurement unit configured to measure a displacement between the pattern of the mold and the shot region on the substrate, a second correction unit configured to correct the displacement, and a control unit configured to control the imprint process.Type: GrantFiled: August 25, 2015Date of Patent: June 25, 2019Assignee: CANON KABUSHIKI KAISHAInventors: Hiroshi Sato, Hiroshi Morohoshi, Yukio Takabayashi
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Patent number: 10310490Abstract: A method and apparatus for evaluating and controlling a semiconductor manufacturing process having a plurality of process steps in a process flow is described. The method comprises retrieving measurements of process step parameters from a process measurement database. The process step parameters comprise at least one of process step measurement data, process step context data or process step control data. The process step parameters are subsequently associated with one or more of the process steps.Type: GrantFiled: February 1, 2016Date of Patent: June 4, 2019Assignee: Qoniac GmbHInventors: Stefan Buhl, Martin Rößiger, Boris Habets
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Patent number: 10288423Abstract: A measuring apparatus, for measuring the distance to a surface having fluctuating reflectivity, the measuring apparatus comprising, a measuring light source and sensor unit positioned at an angle to the perpendicular of the surface to allow the light to be reflected to a diffuse target surface in a known position; and a processor unit, wherein the processor unit is adapted to collect and analyze data from the a measuring light source and sensor unit and classify whether the reading of the measuring light source and sensor unit is a direct reading or a reflected reading.Type: GrantFiled: December 9, 2014Date of Patent: May 14, 2019Assignee: HATCH LTD.Inventor: Owen Pearcey
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Patent number: 10269661Abstract: According to an embodiment, a manufacturing system for a semiconductor device includes a first processing device and a second processing device, a measurement section, and an analysis section. The first processing device and the second processing device are adapted to perform a film formation process on a substrate in a wafer. The measurement section is adapted to measure a first value related to a shape of the wafer after film formation by the first processing device, and then measure a second value related to a distortion of the wafer based on the first value. The analysis section is adapted to change a film formation condition of the second processing device based on processing information of the first processing device, the second value, and information of the second processing device.Type: GrantFiled: September 6, 2017Date of Patent: April 23, 2019Assignee: Toshiba Memory CorporationInventor: Kazuhiro Segawa
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Patent number: 10263542Abstract: A plate, a transducer, a method for making a transducer, and a method for operating a transducer are disclosed. An embodiment comprises a plate comprising a first material layer comprising a first stress, a second material layer arranged beneath the first material layer, the second material layer comprising a second stress, an opening arranged in the first material layer and the second material layer, and an extension extending into opening, wherein the extension comprises a portion of the first material layer and a portion of the second material layer, and wherein the extension is curved away from a top surface of the plate based on a difference in the first stress and the second stress.Type: GrantFiled: December 14, 2017Date of Patent: April 16, 2019Assignee: INFINEON TECHNOLOGIES AGInventor: Alfons Dehe
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Patent number: 10242849Abstract: A system and method of identifying a selected process point in a multi-mode pulsing process includes applying a multi-mode pulsing process to a selected wafer in a plasma process chamber, the multi-mode pulsing process including multiple cycles, each one of the cycles including at least one of multiple, different phases. At least one process output variable is collected for a selected at least one of the phases, during multiple cycles for the selected wafer. An envelope and/or a template of the collected at least one process output variable can be used to identify the selected process point. A first trajectory for the collected process output variable of a previous phase can be compared to a second trajectory of the process output variable of the selected phase. A multivariate analysis statistic of the second trajectory can be calculated and used to identify the selected process point.Type: GrantFiled: April 5, 2017Date of Patent: March 26, 2019Assignee: Lam Research CorporationInventors: Yassine Kabouzi, Jorge Luque, Andrew D. Bailey, III, Mehmet Derya Tetiker, Ramkumar Subramanian, Yoko Yamaguchi
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Patent number: 10241502Abstract: Methods and computer program products for performing automatically determining when to shut down a fabrication tool, such as a semiconductor wafer fabrication tool, are provided herein. The methods include, for example, creating a measurement vector including process parameters of semiconductor wafers, creating a correlation matrix of correlations between measurements of parameters obtained of each wafer, creating autocorrelation matrixes including correlations between measurements of the parameter obtained for pairs of wafers; creating a combined matrix of correlation and autocorrelation matrixes, obtaining a T2 value from the measurement vector and combined matrix, and stopping a semiconductor wafer fabrication tool if the T2 value exceeds a critical value.Type: GrantFiled: December 9, 2016Date of Patent: March 26, 2019Assignee: GLOBALFOUNDRIES Inc.Inventors: Eugene Barash, James Broc Stirton, Richard Good
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Patent number: 10242319Abstract: A baseline predictive maintenance method for a target device (TD) and a computer program product thereof are provided. Fresh samples which are generated when the target device produces workpieces just after maintenance are collected, and a new workpiece sample which is generated when the target device produces a new workpiece is collected. A plurality of modeling samples are used to build a TD baseline model in accordance with a conjecturing algorithm, wherein the modeling samples include the new workpiece sample and the fresh samples. A TD healthy baseline value for the new workpiece is computed by the TD baseline model, and a device health index (DHI), a baseline error index (BEI) and baseline individual similarity indices (ISIB) are computed, thereby achieving the goals of fault detection and classification (FDC) and predictive maintenance (PdM).Type: GrantFiled: March 18, 2013Date of Patent: March 26, 2019Assignee: NATIONAL CHENG KUNG UNIVERSITYInventors: Fan-Tien Cheng, Yao-Sheng Hsieh, Chung-Ren Wang, Saint-Chi Wang
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Patent number: 10224482Abstract: A method for pixel patterning and pixel position inspection of an organic light-emitting display device includes: forming, on a substrate using a first mask, a thin film layer of a first color corresponding to a first pixel pattern and a first pixel positioning pattern for inspecting a position of a first pixel; shifting, by a determined pitch, the first mask from a position associated with forming the thin film layer of the first color; aligning the shifted first mask with respect to the substrate; and forming, on the substrate using the shifted first mask, a thin film layer of a second color corresponding to the first pixel pattern and another first pixel positioning pattern for inspecting a position of a second pixel.Type: GrantFiled: June 22, 2017Date of Patent: March 5, 2019Assignee: Samsung Display Co., Ltd.Inventors: Sangshin Lee, Dongjin Ha, Mingoo Kang, Ohseob Kwon, Sangmin Yi
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Patent number: 10215718Abstract: An electron beam inspection apparatus includes a stage to mount a substrate to be inspected thereon and to be continuously movable, an electron beam column, while the stage continuously moves, to scan the substrate by irradiating the substrate with multi-beams composed of a plurality of first electron beams in a plurality of beam rows, in each of which corresponding beams of the plurality of first electron beams are arranged at a same pitch in a straight line, such that the center of each of irradiation regions irradiated with the multi-beams does not overlap with the other irradiation regions in a movement direction of the stage, and a detector to detect a secondary electron emitted from the substrate due to irradiation of the multi-beams on the substrate.Type: GrantFiled: June 15, 2017Date of Patent: February 26, 2019Assignee: NuFlare Technology, Inc.Inventor: Atsushi Ando
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Patent number: 10184182Abstract: A plasma processing apparatus, to which process control such as APC is applied, includes: a processing chamber in which plasma processing is performed on a sample; and a plasma processing control device which performs control to optimize a condition for plasma processing which recovers the status inside a processing chamber, in which plasma processing is performed, based on a waiting time from the time when plasma processing for a second lot, which is a lot immediately before a first lot, is completed to the time when plasma processing for the first lot is started, and the content of plasma processing for the second lot.Type: GrantFiled: August 24, 2015Date of Patent: January 22, 2019Assignee: HITACHI HIGH-TECHNOLOGIES CORPORATIONInventors: Akira Kagoshima, Daisuke Shiraishi, Yuji Nagatani
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Patent number: 10181517Abstract: A silicon carbide single crystal includes: threading dislocations each of which having a dislocation line extending through a C-plane, and a Burgers vector including at least a component in a C-axis direction. In addition, a density of the threading dislocations having angles, each of which is formed by an orientation of the Burgers vector and an orientation of the dislocation line, larger than 0° and within 40° is set to 300 dislocations/cm2 or less. Furthermore, a density of the threading dislocations having the angles larger than 40° is set to 30 dislocations/cm2 or less.Type: GrantFiled: August 25, 2016Date of Patent: January 15, 2019Assignee: DENSO CORPORATIONInventors: Takeshi Okamoto, Hiroyuki Kondo, Takashi Kanemura, Shinichiro Miyahara, Yasuhiro Ebihara, Shoichi Onda, Hidekazu Tsuchida, Isaho Kamata, Ryohei Tanuma
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Patent number: 10163958Abstract: A method for manufacturing a semiconductor device includes providing a substrate structure including a substrate having a front side and a back side and a pixel region having a plurality of pixels in the front side, each pixel including a sensor element, forming a metal reflective layer in the front side of the substrate and on the pixel region, thinning the back side of the substrate, doping the thinned back side of the substrate with a dopant, and laser annealing the doped back side of the substrate. The sensor element is configured to receive incident light to the thinned back side of the semiconductor substrate. The metal reflective layer reflects heat generated in the laser annealing process to more fully activate the dopant in the back side of the substrate, thereby effectively reducing dark current and improving the device performance.Type: GrantFiled: July 28, 2017Date of Patent: December 25, 2018Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATIONInventor: Wenjie Peng
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Patent number: 10163901Abstract: Methods for preventing step-height difference of flash and logic gates in FinFET devices and related devices are provided. Embodiments include forming fins in flash and logic regions; recessing an oxide exposing an upper portion of the fins; forming an oxide liner over the upper portion in the flash region; forming a polysilicon gate over and perpendicular to the fins in both regions; removing the gate from the logic region and patterning the gate in the flash region forming a separate gate over each fin; forming an ONO layer over the gates in the flash region; forming a second polysilicon gate over and perpendicular to the fins in both regions; planarizing the second polysilicon gate exposing a portion of the ONO layer over the gates in the flash region; forming and patterning a hardmask, exposing STI regions between the flash and logic regions; and forming an ILD over the STI regions.Type: GrantFiled: June 23, 2017Date of Patent: December 25, 2018Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Ming Zhu, Pinghui Li, Su Yi Susan Yeow, Yiang Aun Nga, Danny Pak-Chum Shum, Eng Huat Toh
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Patent number: 10157802Abstract: A workpiece evaluating method evaluates the gettering property of a device wafer having a plurality of devices formed on the front side of the wafer and having a gettering layer formed inside the wafer. The method includes the steps of applying excitation light for exciting a carrier to the wafer, applying microwaves to a light applied area where the excitation light is applied and also to an area other than the light applied area, measuring the intensity of the microwaves reflected from the light applied area and from the area other than the light applied area, subtracting the intensity of the microwaves reflected from the area other than the light applied area from the intensity of the microwaves reflected from the light applied area to thereby obtain a differential signal, and determining the gettering property of the gettering layer according to the intensity of the differential signal obtained above.Type: GrantFiled: March 17, 2017Date of Patent: December 18, 2018Assignee: Disco CorporationInventors: Naoya Sukegawa, Seiji Harada
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Patent number: 10153141Abstract: Provided is an apparatus for monitoring a gas and plasma process equipment including the same. The apparatus includes: a housing including a gas inflow hole, a gas discharge hole, and windows; a light source disposed adjacent to one of the windows outside the housing to provide source light to a gas supplied between the gas inflow hole and the gas discharge hole; a sensor disposed adjacent to the other of the windows outside the housing to detect fluorescence emitted from the gas by the source light; and a coil disposed in the housing between the gas inflow hole and the gas discharge hole to heat and decompose the gas between the light source and the sensor, thereby increasing the fluorescence emitted from the gas.Type: GrantFiled: February 13, 2015Date of Patent: December 11, 2018Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Sun Jin Yun, Kyu Sung Lee, JungWook Lim
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Patent number: 10147657Abstract: A semiconductor device including an electrical conductive sensor structure connected to a sensor circuit. At least a part of the electrical conductive sensor structure is located below a pad of the semiconductor device. Further, the sensor circuit is configured to detect a value or a change of a value of an electrical parameter associated with the electrical conductive sensor structure indicating a crack within proximity of the pad.Type: GrantFiled: April 26, 2016Date of Patent: December 4, 2018Assignee: Infineon Technologies AGInventor: Nikolay Ilkov
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Patent number: 10133263Abstract: Defect inspection methods and systems that use process conditions to dynamically determine how to perform defect inspections during a semiconductor manufacturing process are disclosed. A defect inspection method may include: obtaining process conditions from a process tool utilized to process at least one wafer; determining whether to perform defect inspection of a layer, a wafer, or a high risk area/spot within the at least one wafer based on the process conditions obtained; bypassing the defect inspection when it is determined not to perform the defect inspection; and performing the defect inspection after the at least one wafer is processed by the process tool when it is determined to perform the defect inspection.Type: GrantFiled: August 18, 2015Date of Patent: November 20, 2018Assignee: KLA-Tencor CorporationInventor: Poh Boon Yong
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Patent number: 10121969Abstract: A light-emitting element and its fabrication method are provided. The light-emitting element includes an EL layer between a pair of electrode, and the EL layer is formed by evaporation of an organic compound. The evaporation is conducted so that the partial pressure of a component with a specific molecular weight in a film-formation chamber, which is monitored by a mass spectrometer, does not exceed a specific value during the evaporation. This method allows the formation of a light-emitting element having an improved lifetime.Type: GrantFiled: June 6, 2016Date of Patent: November 6, 2018Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Satoshi Seo, Tsunenori Suzuki
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Patent number: 10121681Abstract: Embodiments of a semiconductor processing apparatus are disclosed. The semiconductor processing apparatus includes a micro chamber for tightly accommodating and processing a semiconductor wafer. The micro chamber includes an upper chamber portion defining an upper working surface and a lower chamber portion defining a lower working surface. The upper chamber portion and the lower chamber portion are relatively movable between an open position for loading and removing the semiconductor wafer and a closed position for tightly accommodating the semiconductor wafer. The semiconductor processing apparatus adopts a modified column device, a lower chamber portion and a balance correction device to achieve easy operation and maintenance, better prevention of chemical processing fluid leakage, and corrosion-resistant design.Type: GrantFiled: April 14, 2012Date of Patent: November 6, 2018Assignee: WUXI HUAYING MICROELECTRONICS TECHNOLOGY CO., LTDInventor: Sophia Wen
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Patent number: 10121667Abstract: In one aspect, a method of processing a semiconductor substrate is disclosed, which comprises incorporating at least one dopant in a semiconductor substrate so as to generate a doped polyphase surface layer on a light-trapping surface, and optically annealing the surface layer via exposure to a plurality of laser pulses having a pulsewidth in a range of about 1 nanosecond to about 50 nanoseconds so as to enhance crystallinity of said doped surface layer while maintaining high above-bandgap, and in many embodiments sub-bandgap optical absorptance.Type: GrantFiled: November 12, 2015Date of Patent: November 6, 2018Assignee: President And Fellows of Harvard CollegeInventors: Eric Mazur, Benjamin Franta, Michael J. Aziz, David Pastor
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Patent number: 10114076Abstract: Systems and methods for semiconductor device selection, including identifying a worst operation condition for a plurality of semiconductor devices in a Modular Multilevel Converter (MMC). The identifying includes determining power losses for each of the semiconductor devices under a plurality of operation conditions, and calculating a maximum junction temperature for each of the plurality of semiconductor devices at each of the plurality of operation conditions. A maximum junction temperature under the identified worst operation condition is determined for each of a plurality of commercially available semiconductor devices which satisfy a threshold voltage rating, and all semiconductor devices which satisfy the threshold voltage rating and a maximum junction temperature threshold condition are compared to identify a semiconductor device with a lowest system cost.Type: GrantFiled: April 7, 2016Date of Patent: October 30, 2018Assignee: NEC CorporationInventors: Feng Guo, Ratnesh Sharma
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Patent number: 10117340Abstract: A manufacturing method of a package substrate includes forming a patterned first dielectric layer on a carrier; forming a first wiring layer on a first surface of the first dielectric layer facing away from the carrier, a wall surface facing one of the openings of the first dielectric layer, and the carrier in one of the openings; forming a first conductive pillar layer on the first wiring layer on the first surface; forming a second dielectric layer on the first surface, the first wiring layer, and the openings, wherein the first conductive pillar layer is exposed from the second dielectric layer; forming a second wiring layer on the exposed first conductive pillar layer and the second dielectric layer; forming an electrical pad layer on the second wiring layer; and forming a third dielectric layer on the second dielectric layer and the second wiring layer.Type: GrantFiled: May 7, 2018Date of Patent: October 30, 2018Assignee: Phoenix Pioneer technology Co., Ltd.Inventors: Che-Wei Hsu, Shih-Ping Hsu, Pao-Hung Chou
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Patent number: 10109539Abstract: An integrated circuit, in the form of a wafer, die, or chip, includes multiple standard cell-compatible fill cells, configured to enable non-contact electrical measurements. Such fill cells include mesh pads that contain at least three conductive stripes disposed between adjacent gate stripes. Such fill cells further include geometry to enable non-contact evaluation of tip-to-side shorts and/or leakages.Type: GrantFiled: September 29, 2017Date of Patent: October 23, 2018Assignee: PDF Solutions, Inc.Inventors: Stephen Lam, Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli, Indranil De, Kelvin Doong, Hans Eisenmann, Timothy Fiscus, Jonathan Haigh, Christopher Hess, John Kibarian, Sherry Lee, Marci Liao, Sheng-Che Lin, Hideki Matsuhashi, Kimon Michaels, Conor O'Sullivan, Markus Rauscher, Vyacheslav Rovner, Andrzej Strojwas, Marcin Strojwas, Carl Taylor, Rakesh Vallishayee, Larg Weiland, Nobuharu Yokoyama
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Patent number: 10096712Abstract: A FinFET structure with a gate structure having two notch features therein and a method of forming the same is disclosed. The method includes the steps of: forming a plurality of fins supported by a substrate; depositing a gate layer on the fins; and etching the gate layer by plasma etching with an etching gas to form a gate having two notch features. The etching gas is supplied at a ratio of a flow rate at a center area of the substrate to a flow rate at a periphery area of the substrate in a range from 0.2 to 1. The disclosure also provides a method of monitoring a quality of the FinFET device, the method comprising: measuring a profile of the notch feature; and obtaining the quality of the FinFET device by comparing the profile of the notch feature with a predetermined criterion.Type: GrantFiled: January 20, 2016Date of Patent: October 9, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chang-Yin Chen, Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
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Patent number: 10072986Abstract: Apparatus and methods of processing substrates include a detector manifold to detect radiation from proximate a processing area in a chamber body; a radiation detector optically coupled to the detector manifold; and a spectral multi-notch filter. Apparatus and methods of processing substrates include detecting transmitted radiation from an emitting surface of a substrate in a chamber body; conveying at least one spectral band of the detected radiation to a photodetector; and analyzing the detected radiation in the at least one spectral band to determine an inferred temperature of the substrate.Type: GrantFiled: July 20, 2017Date of Patent: September 11, 2018Assignee: APPLIED MATERIALS, INC.Inventor: Samuel C. Howells
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Patent number: 10060973Abstract: Described herein are various technologies pertaining to identifying counterfeit integrated circuits (ICs) by way of allowing the origin of fabrication to be verified. An IC comprises a main circuit and a test circuit that is independent of the main circuit. The test circuit comprises at least one ring oscillator (RO) signal that, when energized, is configured to output a signal that is indicative of a semiconductor fabrication facility where the IC was manufactured.Type: GrantFiled: May 22, 2015Date of Patent: August 28, 2018Assignee: National Technology & Engineering Solutions of Sandia, LLCInventors: Ryan Helinski, Lyndon G. Pierson, Jr., Edward I. Cole, Jr., Tan Q. Thai
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Patent number: 10061038Abstract: Disclosed herein is an apparatus for detecting X-ray. The apparatus has an X-ray absorption layer with an electrode, one or more voltage comparators configured to compare a voltage of the electrode to one or more thresholds, a counter configured to register the number of X-ray photons absorbed by the X-ray absorption layer, and a controller.Type: GrantFiled: April 7, 2015Date of Patent: August 28, 2018Assignee: SHENZHEN XPECTVISION TECHNOLOGY CO., LTD.Inventor: Peiyan Cao
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Patent number: 10048656Abstract: A control device for controlling a line in which a plurality of machines performs processes in sequence on a workpiece, the control device having a monitoring section that monitors an amount of electric energy of at least a first machine of the plurality of machines, and a power source control section that controls a power source of at least a second machine of the plurality of machines in accordance with the amount of electric energy of the first machine.Type: GrantFiled: March 17, 2011Date of Patent: August 14, 2018Assignee: OMRON CorporationInventor: Wakahiro Kawai
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Patent number: 10042357Abstract: Described herein are methods and systems for providing a user interface to indicate health of a tool in a manufacturing facility. A method may include receiving, via a user interface, user selection of fault detection data pertaining to a tool in a manufacturing facility, obtaining health abnormality indicators of the tool using the fault detection data, and presenting the health abnormality indicators of the tool in the user interface.Type: GrantFiled: October 23, 2013Date of Patent: August 7, 2018Assignee: Applied Materials, Inc.Inventors: James R. Moyne, Jimmy Iskandar, Bradley D. Schulze
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Patent number: 10043970Abstract: The present disclosure relates to a method for determining a characteristic of a monitored layer of an integrated chip structure. In some embodiments, the method may be performed by forming an integrated chip structure over a substrate. The method further includes forming a monitor layer over the integrated chip structure. The monitor layer includes a plurality of monitor pads. The method also includes measuring an electrical property between a set of monitor pads of the plurality of monitor pads. The set of monitor pads are laterally spaced apart by a monitor pad distance. A characteristic of a region of the integrated chip structure underlying the monitor pad distance between the set of monitor pads is determined based on the measured electrical property.Type: GrantFiled: March 3, 2017Date of Patent: August 7, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Harry-Hak-Lay Chuang, Tien-Wei Chiang, Wen-Chun You
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Patent number: 10042159Abstract: Disclosed herein is a scanning ladar transmitter that employs an optical field splitter/inverter to improve the gaze characteristics of the ladar transmitter on desirable portions of a scan area. Also disclosed is the use of scan patterns such as Lissajous scan patterns for a scanning ladar transmitter where a phase drift is induced into the scanning to improve the gaze characteristics of the ladar transmitter on desirable portions of the scan area. Also disclosed is a compact beam scanner assembly that includes an ellipsoidal reimaging mirror.Type: GrantFiled: July 7, 2017Date of Patent: August 7, 2018Assignee: AEYE, INC.Inventors: Luis Carlos Dussan, David R. Demmer, John Stockton, Allan Steinhardt, David Cook
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Patent number: 10030971Abstract: A measurement method and system are presented for in-line measurements of one or more parameters of thin films in structures progressing on a production line. First measured data and second measured data are provided from multiple measurements sites on the thin film being measured, wherein the first measured data corresponds to first type measurements from a first selected set of a relatively small number of the measurement sites, and the second measured data corresponds to second type optical measurements from a second set of significantly higher number of the measurements sites. The first measured data is processed for determining at least one value of at least one parameter of the thin film in each of the measurement sites of said first set. Such at least one parameter value is utilized for interpreting the second measured data, thereby obtaining data indicative of distribution of values of said at least one parameter within said second set of measurement sites.Type: GrantFiled: August 4, 2016Date of Patent: July 24, 2018Assignees: Globalfoundries, Inc., Nova Measuring Instruments Ltd.Inventors: Cornel Bozdog, Alok Vaid, Sridhar Mahendrakar, Mainul Hossain, Taher Kagalwala
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Patent number: RE47208Abstract: A single crystal silicon layer is formed on a principal surface of a first wafer by epitaxial growth. A silicon oxide layer is formed on the single crystal silicon layer. Next, a defect layer is formed inside the single crystal silicon layer by ion implantation, and then, the second wafer is bonded to the silicon oxide layer on the first wafer. After that, an SOI wafer including the silicon oxide layer formed on the second wafer and the single crystal silicon layer formed on the silicon oxide layer is formed by separating the first wafer including the single crystal silicon layer from the second wafer including the single crystal silicon layer in the defect layer. Then, a photodiode is formed in the single crystal silicon layer. An interconnect layer is formed on a surface of the single crystal silicon layer which is opposite to the silicon oxide layer.Type: GrantFiled: April 28, 2017Date of Patent: January 15, 2019Assignee: Conversant Intellectual Property Management Inc.Inventor: Akira Tsukamoto