Abstract: In some embodiments, an field effect transistor structure includes a first semiconductor structure and a gate structure. The first semiconductor structure includes a channel region, and a source region and a drain region. The source region and the drain region are formed on opposite ends of the channel region, respectively. The gate structure includes a central region and footing regions. The central region is formed over the first semiconductor structure. The footing regions are formed on opposite sides of the central region and along where the central region is adjacent to the first semiconductor structure.

Abstract: Integrated circuits (1) on a wafer comprise a wafer substrate (2) and a plurality of integrated circuits (Ia, Ib, Ic) formed on the wafer substrate (2). Each integrated circuit (Ia, Ib, Ic) comprises an electric circuit (24) and some of the integrated circuits (Ib, Ic) comprise, in addition to their electric circuits (24), process control modules (3) as integral parts. The process control modules (3) are employed during dicing and pick-and-place to align the dicing/pick-and-place devices.

Abstract: A method of placing a dummy fill layer on a substrate is disclosed (FIG. 2). The method includes identifying a sub-region of the substrate (210). A density of a layer in the sub-region is determined (212). A pattern of the dummy fill layer is selected to produce a predetermined density (216). The selected pattern is placed in the sub-region (208).

Abstract: Disclosed herein is a pre space transformer including: a substrate having a first surface and a second surface, which is an opposite surface to the first surface; individual electrodes disposed on the first surface; and common electrodes disposed in the substrate, wherein the individual electrodes are repeatedly disposed while configuring a unit pattern.

Abstract: Laser sub-divisional error (SDE) effect is compensated by using adaptive tuning. This compensated signal can be applied to position detection of stage in ebeam inspection tool, particularly for continuous moving stage.

Abstract: Controlled recessing of materials in cavities and resulting devices are disclosed.

Abstract: A system (10) for directly measuring the depth of a high aspect ratio etched feature on a wafer (80) that includes an etched surface (82) and a non-etched surface (84). The system (10) utilizes an infrared reflectometer (12) that in a preferred embodiment includes a swept laser (14), a fiber circulator (16), a photodetector (22) and a combination collimator (18) and an objective lens (20). From the objective lens (20) a focused incident light (23) is produced that is applied to the non-etched surface (84) of the wafer (80). From the wafer (80) is produced a reflected light (25) that is processed through the reflectometer (12) and applied to an ADC (24) where a corresponding digital data signal (29) is produced. The digital data signal (29) is applied to a computer (30) that, in combination with software (32), measures the depth of the etched feature that is then viewed on a display (34).

Abstract: An embodiment is a method including forming a fin on a substrate, forming a first doped region in a top portion of the fin, the first doped region having a first dopant concentration, and forming a second doped region in a middle and bottom portion of the fin, the second doped region having a second dopant concentration, the second dopant concentration being less than the first dopant concentration.

Abstract: The present disclosure relates to a method for manufacturing one or more optical engine packages, each optical engine package comprising a silicon photonic die. The method includes receiving a substrate comprising a package portion and a cutting area adjacent to the package portion, assembling the optical engine package on the substrate such that an edge-coupled waveguide of the silicon photonic die overlaps a boundary between the cutting area and the package portion, and cutting the optical engine package and the substrate in the cutting area to expose the edge-coupled waveguide for optical coupling thereof to an optical fiber core.

Abstract: A method and an apparatus for precisely detecting a trench S in a product W to become a thin film solar cell are provided. In the product W, a lower electrode layer 12, in which the trench S is created, and light absorbing layers 13 and 14 are layered on a substrate 11 in this order. The method includes the steps of: detecting infrared rays for imaging, of which the wavelengths are in such a range that can transmit through the light absorbing layers 13 and 14 and which are irradiated from the product W, by means of an infrared ray imaging apparatus 16 that is provided above the light absorbing layers 13 and 14 so that image data for radiation intensity distribution can be taken; and detecting the trench S in the lower electrode layer 12 on the basis of this image data for radiation intensity distribution.

Abstract: A method of manufacturing a semiconductor device includes forming a film on a substrate by performing a cycle a predetermined number of times. The cycle includes non-simultaneously performing: forming a first layer by supplying a precursor gas including a chemical bond of a first element and carbon and a first catalyst gas to the substrate; exhausting the precursor gas and the first catalyst gas through an exhaust system; forming a second layer by supplying a reaction gas including a second element and a second catalyst gas to the substrate to modify the first layer; and exhausting the reaction gas and the second catalyst gas through the exhaust system. At least in a specific cycle, the respective gases are supplied and confined in the process chamber while closing the exhaust system in at least one of the act of forming the first layer and the act of forming the second layer.

Abstract: The reliability of multipoint contact by a contact pin with an external terminal is improved while achieving an improvement in easiness of manufacture of the contact pin. The contact pin includes first and second contact pins. Further, the first contact pin has a support portion extending in a y direction and a tip portion connected to the support portion. The second contact pin also has a support portion extending in the y direction and a tip portion connected to the support portion. Here, the support portion of the first contact pin and the support portion of the second contact pin are arranged side by side along an x direction in a horizontal plane (xy plane). Further, the tip portion of the second contact pin is shifted from the tip portion of the first contact pin along the y direction in the horizontal plane, crossing (perpendicular to) the x direction.

Abstract: A temperature measurement device is provided with: light collection means; extraction means; optical intensity calculation means; and temperature measurement means. The light collection means collects the emission spectrum of a measurement subject. The extraction means extracts light having the wavelength of the atomic spectral lines and light having a wavelength in a wavelength region where there are no atomic spectral lines, from the emission spectrum collected by the aforementioned light collection means. The optical intensity calculation means calculates the optical intensities of the light extracted by the aforementioned extraction means. The temperature measurement means calculates the temperature of the aforementioned measurement subject, based on the intensities of the beams calculated by the aforementioned optical intensity calculation means.

Abstract: A semiconductor structure is provided. The semiconductor includes a gate stack on a substrate. The semiconductor includes a first set of sidewall spacers on opposite sidewalls of the gate stack. The semiconductor includes a flowable dielectric layer on the substrate, covering at least a portion of the first set of sidewall spacers. The semiconductor includes a second set of sidewall spacers next to the first set of sidewall spacers covering an upper portion thereof, the second set of sidewall spacers are directly on top of the flowable dielectric layer. The semiconductor includes a contact next to at least one of the second set of sidewall spacers.

Abstract: An image forming apparatus including an engine unit to perform an image forming operation, and a board unit to control the engine unit. The board unit includes at least one chip package that includes a chip. The chip includes first pads to transmit a first type of signal, a second pad to transmit a second type of signal, and a third pad interposed between the first and second pads, to reduce cross-talk between the first and second types of signals.

Abstract: Methods for processes to form and use merged spacers in fin generation and the resulting devices are disclosed. Embodiments include providing first and second mandrels separated from each other across adjacent cells on a Si layer; forming first and second dummy-spacers and third and fourth dummy-spacers on opposite sides of the first and second mandrels, respectively; removing, through a block-mask, the first and fourth dummy spacers and a portion of the second and third dummy-spacers; forming first spacers on each exposed side of the mandrels and in between the second and third dummy-spacers, forming a merged spacer; removing the mandrels; removing a section of the merged-spacer; forming second spacers on all exposed sides of the first spacers and the merged-spacer; removing the merged-spacer and the first spacers; removing exposed sections of the Si layer through the second spacers; and removing the second spacers to reveal Si fins.

Abstract: System and method for test structure on a wafer. According to an embodiment, the present invention provides a test structure for testing an integrated circuit. For example, the test structure and the integrated circuit are manufactured on a same substrate material and the testing being conducted is in a temperature-controlled environment. The test structure includes a top structure positioned above the integrated circuit, the top structure including a first metal material, which includes a first electrical terminal and a second electrical terminal. The test structure also includes a bottom structure positioned below the integrated circuit, the bottom structure including a first silicon material. A first side structure is positioned between the top structure and the bottom structure and located next to a first side of the integrated circuit. A second side structure is positioned between the top structure and the bottom structure and located next to a second side of the integrated circuit.

Abstract: A method for inspecting a polysilicon layer includes: radiating excitation light to the polysilicon layer; and detecting a photoluminescence signal generated by the excitation light, wherein average power of the excitation light has a range of 1 W/cm2 to 10 W/cm2, and peak power of the excitation light has a range of 100 W/cm2 to 1000 W/cm2.

Abstract: A method of manufacturing semiconductor and an exposure system are provided. The method includes the following step. A material layer is formed on a substrate. A patterned photoresist layer is formed a on the material layer and a monitor parameter group is produced from a state information of the patterned photoresist layer. The monitor parameter group is calculated based on a mathematic formula to obtain a virtual parameter. Whether the virtual parameter is less than a reference value is determined. A layout process is performed on the material layer when the virtual parameter is less than the reference value.

Abstract: This invention relates to slicing a thin semiconductor substrate from side wall into two substrates of half thickness. The substrate slicing process involves a laser irradiation step. The substrate slicing process can also involve a mechanical cleaving process after the laser irradiation step. The apparatus for substrate slicing comprises two opposite-facing substrate chucks, with a gap in between for the substrate to pass through. One portion of the two substrate chucks are in parallel to each other to center the substrate sidewall. The gap can increase between the second portion of the two substrate chucks after the location for substrate separation, to spread out the resulting two substrates after the slicing and to facilitate the continuous substrate separation process. The present invention is further directed to methods and apparatus of separating a continuous thin layer of materials from side wall of a rotating ingot.

Abstract: An integrated circuit structure includes a dielectric layer, and a conductive line in the dielectric layer. The conductive line has a first top surface and a second top surface lower than the first top surface, and a sidewall connecting the first top surface to the second top surface. A via includes a portion overlying the second top surface of the conductive line. The via is electrically coupled to the conductive line through the second top surface and the sidewall of the conductive line.

Abstract: Various methods include: forming an opening in a resist layer to expose a portion of an underlying blocking layer; performing an etch on the exposed portion of the blocking layer to expose a portion of an etch stop layer, wherein the etch stop layer resists etching during the etch of the exposed portion of the blocking layer; etching the exposed portion of the etch stop layer to expose a portion of a substrate below the exposed portion of the etch stop layer and leave a remaining portion of the etch stop layer; and ion implanting the exposed portion of the substrate, wherein the blocking layer prevents ion implanting of the substrate outside of the exposed portion.

Abstract: An integrated circuit (IC) is designed that includes one variant having a plurality of a modular circuits communicatively coupled together and a second variant having a sub-set of the plurality of modular circuits. The modular circuits are then laid out on a wafer for fabricating each of the variants of the IC. The layout includes routing communicative couplings between the sub-set of the modular circuits of the second variant to the other modular circuits of the first variant in one or more metallization layers to be fabricated last. Fabricating the IC is then started, up to but not including the one or more metallization layers to be fabricated last. One or more of the plurality of variants of the IC is selected based upon a demand predicted during fabrication. Fabrication then continues with the last metallization layers of the IC according to the selected layout.

Abstract: A method of designing a diode includes generating a layout of the diode and calculating a calculated voltage overshoot based on the layout. The calculating includes calculating variables of: the length of an N region of the diode; current density during an ESD event; electron charge; hole mobility; electron mobility; doping concentration of the diode; and rise time of the ESD event.

Abstract: Disclosed are chip carriers and methods of using them. The chip carriers each comprise a base with a first surface, a second surface opposite the first surface, and wire bond pads on the first and second surfaces. The first surface also has a chip attach area with opening(s) that extends from the first surface to the second surface. A chip can be attached to the chip attach area and, because of the opening(s), wire bond pads on opposite sides (e.g., on the top and bottom) of the chip are accessible for testing. That is, wire bond pads on the first surface can be electrically connected to one side of the chip (e.g., to the top of the chip) and/or wire bond pads on the second surface can be electrically connected through the opening(s) to the opposite side of the chip (e.g., to the bottom of the chip).

Abstract: A substrate position detecting apparatus detects a position of a substrate inside a chamber from an image of a target inside the chamber. The apparatus includes an image pickup device to pick up the image of the target inside the chamber through a window, an illumination device to irradiate light upwards, an illumination reflecting plate provided above the illumination device and including a reflecting surface to reflect the light from the illumination device towards the window, and a reflection restricting part provided on the reflecting surface to form a shadow in a predetermined region that includes the target inside the chamber.

Abstract: The disclosure describes a metal-wire-based method for making an integrated ingot, which basically comprises a dielectric matrix and a patterned array of metal wires, and may further comprise other additive elements at desired locations. After sawing the integrated ingot into slices, a plurality of substrates containing through substrate metal pillars and other additive elements at desired locations are produced in a batch way. The metal-wire-based method comprises the key steps: forming a patterned array of metal wires, precisely integrating other additive elements at desired locations when needed, forming a solid dielectric material in the empty space among and around metal wires and other additive elements. Furthermore, a guidance metal wire method is described for precisely integrating other additive elements at desired locations in a patterned array of metal wires.

Abstract: A method and system are provided for profiling data packets as they flow along a datapath in a device under test to locate and debug problems with the datapath or the individual nodes constituting the datapath to thereby expedite formal verification of a device under test and resolve any problems found.

Abstract: A method of calibrating or monitoring an exposing tool including forming a substrate pattern in a substrate, wherein forming the substrate pattern includes providing a first patterned photo resist layer having an etch coating layer disposed thereon and using the first patterned photo resist layer and the etch coating layer to pattern an underlying layer. The patterned underlying layer is then used as a masking element when etching the substrate pattern into the substrate. A second photo resist pattern is formed over the substrate pattern. An overlay measurement is executed of the second photo resist pattern to the substrate pattern.

Abstract: A test voltage having a first voltage or a second voltage is applied to an output terminal of a complementary fuse that includes a first fuse to one end of which the first voltage is applied and the other end of which serves as the output terminal and a second fuse to one end of which the second voltage is applied and the other end of which is connected to the output terminal. The test voltage then stops being applied. In such a state, whether output data from the output terminal of the complementary fuse coincides with an expected value is determined. The result of determination is output as a test result.

Abstract: A method for patterning a wafer includes performing a first patterning on a wafer, and after performing the first patterning, calculating a simulated dose mapper (DoMa) map predicting a change in critical dimensions of the wafer due to performing a second patterning on the wafer. The method further includes performing the second patterning on the wafer. Performing the second patterning includes adjusting one or more etching parameters of the second patterning in accordance with differences between the simulated DoMa map and desired critical dimensions of the wafer.

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with a line shaped laser beam profile laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.

Abstract: A semiconductor device is provided with: a semiconductor substrate; an insulation film formed above the semiconductor substrate; a pad formed on the insulation film, the pad including a trace; a first passivation film formed on the insulation film, located adjacent the pad, and separated from the pad; and a second passivation film formed on the first passivation film and the pad, the second passivation film covering the trace, and the second passivation film including an opening which exposes a part of the pad.

Abstract: A mounting system includes a jig storage that stores an identifier of a component mounted on a circuit board with an identifier of a jig relative to which the component is provided, a component storage that stores an identifier of a circuit board with an identifier of a component to be mounted on the circuit board, a first identification unit that identifies a new component to be mounted on a new circuit board unit and a current component mounted on a circuit board unit currently being manufactured from the component storage when the new component is to be mounted, a second identification unit that compares the identified new component with the identified current component to identify a current component not included in the new component, and an emitter that causes light to be emitted via a light emitting element on a jig with the identified current component.

Abstract: A packaged semiconductor device includes a semiconductor substrate, a metal pad, a metal base, a polymer insulating layer, a copper-containing structure and a conductive bump. The metal pad and the metal base are disposed on the semiconductor substrate. The polymer insulating layer overlies the metal base and the semiconductor substrate. The copper-containing structure is disposed over the polymer insulating layer, and includes a support structure and a post-passivation interconnect (PPI) line. The support structure is aligned with the metal base. The PPI line is located partially within the support structure, and extends out through an opening of the support structure, in which a top of the support structure is elevated higher than a top of the PPI line. The conductive bump is held by the support structure.

Abstract: A polishing method is used for polishing a substrate such as a semiconductor wafer to a flat mirror finish. A method of polishing a substrate by a polishing apparatus includes a polishing table (100) having a polishing surface, a top ring (1) for holding a substrate and pressing the substrate against the polishing surface, and a vertically movable mechanism (24) for moving the top ring (1) in a vertical direction. The top ring (1) is moved to a first height before the substrate is pressed against the polishing surface, and then the top ring (1) is moved to a second height after the substrate is pressed against the polishing surface.

Abstract: A method of controlling polishing includes polishing a substrate, during polishing monitoring the substrate with an in-situ monitoring system, the monitoring including generating a signal from a sensor, and filtering the signal to generate a filtered signal. The signal includes a sequence of measured values, and the filtered signal including a sequence of adjusted values. The filtering includes for each adjusted value in the sequence of adjusted values, generating at least one predicted value from the sequence of measured values using linear prediction, and calculating the adjusted value from the sequence of measured values and the predicted value. At least one of a polishing endpoint or an adjustment for a polishing rate is determined from the filtered signal.

Abstract: Provided herein are a method and apparatus for the formation of conductive films on a substrate using precise sintering of a conductive film and thermal management of the substrate during sintering. In particular, a method may include depositing a conductive metal-based ink on a translucent or transparent substrate, positioning a mask between the deposited conductive metal-based ink and a light source, exposing the mask and the underlying deposited conductive metal-based ink to the light source, sintering the conductive metal-based ink exposed to the light source, and cleaning the non-sintered conductive metal-based ink from the translucent or transparent substrate. The mask may be configured to shield at least a portion of the conductive metal-based ink from the light source. The portion of the conductive metal-based ink shielded from the light source may remain non-sintered in response to the sintering of the conductive metal-based ink exposed to the light source.

Abstract: A method and an apparatus of etching a semiconductor wafer are provided. The etching apparatus of a semiconductor wafer having a marker inside includes: a monitoring device capable of monitoring a surface of the semiconductor wafer so as to detect the marker; a nozzle capable of jetting a mixed gas that contains hydrogen fluoride and ozone onto the surface of the semiconductor wafer; a regulator capable of adjusting at least one of hydrogen fluoride concentration and ozone concentration in the mixed gas; and a controller capable of determining whether the marker is detected by the monitoring device and terminating the etching process.

Abstract: The present disclosure relates to a method of generating a scaled integrated chip design by scaling a FEOL and a BEOL of an original IC design at different scaling ratios, and an associated apparatus. In some embodiments, the method is performed by forming an original integrated chip (IC) design that is a graphical representation of an integrated chip. The original IC design has a front-end-of-the-line (FEOL) section, a back-end-of-the-line (BEOL) section, and a middle-of-the-line (MOL) section that is disposed between the FEOL and BEOL sections. A scaled integrated chip design is formed by scaling (i.e., shrinking) the FEOL section and the BEOL section of the original integrated chip design at different scaling ratios, and by scaling different design layers within the MOL section at different scaling ratios to avoid misalignment errors between the FEOL section and the BEOL section.

Abstract: Semiconductor devices and fabrication methods for simultaneously forming a 3T-FinFET and a 4T-FinFET on a same substrate are provided. A first fin and a second fin can be formed on a semiconductor substrate. The first fin has a top surface higher than the second fin. A first gate dielectric layer and a first gate can be formed across the first fin. A second gate dielectric layer and a second gate can be formed across the second fin. An interlayer dielectric layer can be formed to cover the first gate, the second gate, and the semiconductor substrate. A first portion of the interlayer dielectric layer, a portion of the first gate, and a portion of the first gate dielectric layer, over the first fin, and a second portion of the interlayer dielectric layer over the second fin can be removed to expose the second gate.

Abstract: A method for measuring critical dimension (CD) includes steps of: scanning at least one area of interest of a die to obtain at least one scanned image; aligning the scanned image to at least one designed layout pattern to identify a plurality of borders within the scanned image; and averaging distances each measured from the border or the plurality of borders of a pattern associated with a specific type of CD corresponding to the designed layout pattern to obtain a value of CD of the die. The value of critical dimensions of dies can be obtained from the scanned image with lower resolution which is obtained by relatively higher scanning speed, so the above-mentioned method can obtain value of CD for every die within entire wafer to monitor the uniformity of the semiconductor manufacturing process within an acceptable inspection time.

Abstract: A method of detecting an asymmetric portion of an overlay mark includes forming a plurality of virtual overlay marks having a plurality of virtual asymmetric portions. The virtual asymmetric portions may have different sizes with respect to a reference model profile of a reference overlay mark. Virtual information with respect to each virtual overlay mark may be obtained. The virtual information of the virtual overlay marks may be compared with actual information of an actual overlay mark to identify virtual information of the virtual overlay mark corresponding to the actual information of the actual overlay mark. Thus, measuring the overlay of the actual overlay mark may be performed under than the actual asymmetric portion may be excluded from the actual overlay mark, so that the overlay may be accurately measured. As a result, errors may not be generated in a correcting process to a layer using the accurate overlay.

Abstract: A method of modifying a substrate carrier to improve process performance includes depositing material or fabricating devices on a substrate supported by a substrate carrier. A parameter of layers deposited on the substrate is then measured as a function of their corresponding positions on the substrate carrier. The measured parameter of at least some devices fabricated on the substrate or a property of the deposited layers is related to a physical characteristic of substrate carrier to obtain a plurality of physical characteristics of the substrate carrier corresponding to a plurality of positions on the substrate carrier. The physical characteristic of the substrate carrier is then modified at one or more of the plurality of corresponding positions on the substrate carrier to obtain desired parameters of the deposited layers or fabricated devices as a function of position on the substrate carrier.

Abstract: The present disclosure relates to the field of integrated circuit packaging and, more particularly, to packages using embedded microelectronic die applications, such a bumpless build-up layer (BBUL) designs. Embodiments of the present description relate to the field of alignment correction of microelectronic dice within the bumpless build-up layer packages. This alignment correction may comprise characterizing the misalignment of each microelectronic die mounted on a carrier and forwarding this characterization, along with data regarding the orientation of the carrier, to processing equipment that can compensate for the misalignment of each microelectronic die.

Abstract: Disclosed is a manufacturing method of a semiconductor device including a step of attaching semiconductor wafers together, in which it is prevented that the bonding strength between the attached semiconductor wafers may be decreased due to a void caused between the two semiconductor wafers. Moisture, etc., adsorbed to the surfaces of the semiconductor wafers is desorbed by performing a heat treatment on the semiconductor wafers after cleaning the surfaces thereof with pure water. Subsequently, after a plasma treatment is performed on the semiconductor wafers, the two semiconductor wafers are attached together. The wafers are firmly bonded together by subjecting to a high-temperature heat treatment.

Abstract: An integrated circuit with probeable and routable interfaces is disclosed. The integrated circuit includes multiple micro-pillars that are attached to the surface of the integrated circuit, and multiple macro-pillars also attached to the surface of the integrated circuit. The micro-pillars provide an electrical interface to the integrated circuit during regular operation. The macro-pillars provide an electrical interface to the integrated circuit both during regular operation and during testing of the integrated circuit.

Abstract: A method and system for real-time, in-line calculations of opto-electronic properties and thickness of the layers of multi-layered transparent conductive oxide stacks of photovoltaic devices is provided. The method and system include taking measurements of each layer of the stack during deposition thereof. The measurements are then used to calculate the opto-electronic properties and thicknesses of the layers in real-time.

Abstract: According to various embodiments of the disclosure, an apparatus and method for enhanced deposition and etch techniques is described, including a pedestal, the pedestal having at least two electrodes embedded in the pedestal, a showerhead above the pedestal, a plasma gas source connected to the showerhead, wherein the showerhead is configured to deliver plasma gas to a processing region between the showerhead and the substrate and a power source operably connected to the showerhead and the at least two electrodes with plasma being substantially contained in an area which corresponds with one electrode of the at least two electrodes.

Abstract: A method is provided for forming multiple-LED (light-emitting-diode) light emitters from a plurality of LEDs, wherein the number of LEDs in each emitter is an integer M. The method includes providing a plurality of LEDs, each of the LEDs characterized by a first parameter and a second parameter, which are related to color coordinates CIEx and CIEy in a chromaticity diagram. The method also includes determining first and second parameter X0 and Y0 for a target color. The method further includes, for all possible combinations of M LEDs out of the plurality of LEDs, determining a first group parameter and a second group parameter based on the first and second parameters for all of the M LEDs, and selecting a group of M LEDs whose first group parameter and second group parameter are closest to X0 and Y0 as a candidate for forming a light emitter of M LEDs.