Abstract: A temperature measurement device is provided with: light collection means; extraction means; optical intensity calculation means; and temperature measurement means. The light collection means collects the emission spectrum of a measurement subject. The extraction means extracts light having the wavelength of the atomic spectral lines and light having a wavelength in a wavelength region where there are no atomic spectral lines, from the emission spectrum collected by the aforementioned light collection means. The optical intensity calculation means calculates the optical intensities of the light extracted by the aforementioned extraction means. The temperature measurement means calculates the temperature of the aforementioned measurement subject, based on the intensities of the beams calculated by the aforementioned optical intensity calculation means.

Abstract: A semiconductor structure is provided. The semiconductor includes a gate stack on a substrate. The semiconductor includes a first set of sidewall spacers on opposite sidewalls of the gate stack. The semiconductor includes a flowable dielectric layer on the substrate, covering at least a portion of the first set of sidewall spacers. The semiconductor includes a second set of sidewall spacers next to the first set of sidewall spacers covering an upper portion thereof, the second set of sidewall spacers are directly on top of the flowable dielectric layer. The semiconductor includes a contact next to at least one of the second set of sidewall spacers.

Abstract: An image forming apparatus including an engine unit to perform an image forming operation, and a board unit to control the engine unit. The board unit includes at least one chip package that includes a chip. The chip includes first pads to transmit a first type of signal, a second pad to transmit a second type of signal, and a third pad interposed between the first and second pads, to reduce cross-talk between the first and second types of signals.

Abstract: Methods for processes to form and use merged spacers in fin generation and the resulting devices are disclosed. Embodiments include providing first and second mandrels separated from each other across adjacent cells on a Si layer; forming first and second dummy-spacers and third and fourth dummy-spacers on opposite sides of the first and second mandrels, respectively; removing, through a block-mask, the first and fourth dummy spacers and a portion of the second and third dummy-spacers; forming first spacers on each exposed side of the mandrels and in between the second and third dummy-spacers, forming a merged spacer; removing the mandrels; removing a section of the merged-spacer; forming second spacers on all exposed sides of the first spacers and the merged-spacer; removing the merged-spacer and the first spacers; removing exposed sections of the Si layer through the second spacers; and removing the second spacers to reveal Si fins.

Abstract: System and method for test structure on a wafer. According to an embodiment, the present invention provides a test structure for testing an integrated circuit. For example, the test structure and the integrated circuit are manufactured on a same substrate material and the testing being conducted is in a temperature-controlled environment. The test structure includes a top structure positioned above the integrated circuit, the top structure including a first metal material, which includes a first electrical terminal and a second electrical terminal. The test structure also includes a bottom structure positioned below the integrated circuit, the bottom structure including a first silicon material. A first side structure is positioned between the top structure and the bottom structure and located next to a first side of the integrated circuit. A second side structure is positioned between the top structure and the bottom structure and located next to a second side of the integrated circuit.

Abstract: A method for inspecting a polysilicon layer includes: radiating excitation light to the polysilicon layer; and detecting a photoluminescence signal generated by the excitation light, wherein average power of the excitation light has a range of 1 W/cm2 to 10 W/cm2, and peak power of the excitation light has a range of 100 W/cm2 to 1000 W/cm2.

Abstract: A method of manufacturing semiconductor and an exposure system are provided. The method includes the following step. A material layer is formed on a substrate. A patterned photoresist layer is formed a on the material layer and a monitor parameter group is produced from a state information of the patterned photoresist layer. The monitor parameter group is calculated based on a mathematic formula to obtain a virtual parameter. Whether the virtual parameter is less than a reference value is determined. A layout process is performed on the material layer when the virtual parameter is less than the reference value.

Abstract: This invention relates to slicing a thin semiconductor substrate from side wall into two substrates of half thickness. The substrate slicing process involves a laser irradiation step. The substrate slicing process can also involve a mechanical cleaving process after the laser irradiation step. The apparatus for substrate slicing comprises two opposite-facing substrate chucks, with a gap in between for the substrate to pass through. One portion of the two substrate chucks are in parallel to each other to center the substrate sidewall. The gap can increase between the second portion of the two substrate chucks after the location for substrate separation, to spread out the resulting two substrates after the slicing and to facilitate the continuous substrate separation process. The present invention is further directed to methods and apparatus of separating a continuous thin layer of materials from side wall of a rotating ingot.

Abstract: An integrated circuit structure includes a dielectric layer, and a conductive line in the dielectric layer. The conductive line has a first top surface and a second top surface lower than the first top surface, and a sidewall connecting the first top surface to the second top surface. A via includes a portion overlying the second top surface of the conductive line. The via is electrically coupled to the conductive line through the second top surface and the sidewall of the conductive line.

Abstract: Various methods include: forming an opening in a resist layer to expose a portion of an underlying blocking layer; performing an etch on the exposed portion of the blocking layer to expose a portion of an etch stop layer, wherein the etch stop layer resists etching during the etch of the exposed portion of the blocking layer; etching the exposed portion of the etch stop layer to expose a portion of a substrate below the exposed portion of the etch stop layer and leave a remaining portion of the etch stop layer; and ion implanting the exposed portion of the substrate, wherein the blocking layer prevents ion implanting of the substrate outside of the exposed portion.

Abstract: An integrated circuit (IC) is designed that includes one variant having a plurality of a modular circuits communicatively coupled together and a second variant having a sub-set of the plurality of modular circuits. The modular circuits are then laid out on a wafer for fabricating each of the variants of the IC. The layout includes routing communicative couplings between the sub-set of the modular circuits of the second variant to the other modular circuits of the first variant in one or more metallization layers to be fabricated last. Fabricating the IC is then started, up to but not including the one or more metallization layers to be fabricated last. One or more of the plurality of variants of the IC is selected based upon a demand predicted during fabrication. Fabrication then continues with the last metallization layers of the IC according to the selected layout.

Abstract: A method of designing a diode includes generating a layout of the diode and calculating a calculated voltage overshoot based on the layout. The calculating includes calculating variables of: the length of an N region of the diode; current density during an ESD event; electron charge; hole mobility; electron mobility; doping concentration of the diode; and rise time of the ESD event.

Abstract: Disclosed are chip carriers and methods of using them. The chip carriers each comprise a base with a first surface, a second surface opposite the first surface, and wire bond pads on the first and second surfaces. The first surface also has a chip attach area with opening(s) that extends from the first surface to the second surface. A chip can be attached to the chip attach area and, because of the opening(s), wire bond pads on opposite sides (e.g., on the top and bottom) of the chip are accessible for testing. That is, wire bond pads on the first surface can be electrically connected to one side of the chip (e.g., to the top of the chip) and/or wire bond pads on the second surface can be electrically connected through the opening(s) to the opposite side of the chip (e.g., to the bottom of the chip).

Abstract: A substrate position detecting apparatus detects a position of a substrate inside a chamber from an image of a target inside the chamber. The apparatus includes an image pickup device to pick up the image of the target inside the chamber through a window, an illumination device to irradiate light upwards, an illumination reflecting plate provided above the illumination device and including a reflecting surface to reflect the light from the illumination device towards the window, and a reflection restricting part provided on the reflecting surface to form a shadow in a predetermined region that includes the target inside the chamber.

Abstract: The disclosure describes a metal-wire-based method for making an integrated ingot, which basically comprises a dielectric matrix and a patterned array of metal wires, and may further comprise other additive elements at desired locations. After sawing the integrated ingot into slices, a plurality of substrates containing through substrate metal pillars and other additive elements at desired locations are produced in a batch way. The metal-wire-based method comprises the key steps: forming a patterned array of metal wires, precisely integrating other additive elements at desired locations when needed, forming a solid dielectric material in the empty space among and around metal wires and other additive elements. Furthermore, a guidance metal wire method is described for precisely integrating other additive elements at desired locations in a patterned array of metal wires.

Abstract: A method and system are provided for profiling data packets as they flow along a datapath in a device under test to locate and debug problems with the datapath or the individual nodes constituting the datapath to thereby expedite formal verification of a device under test and resolve any problems found.

Abstract: A method of calibrating or monitoring an exposing tool including forming a substrate pattern in a substrate, wherein forming the substrate pattern includes providing a first patterned photo resist layer having an etch coating layer disposed thereon and using the first patterned photo resist layer and the etch coating layer to pattern an underlying layer. The patterned underlying layer is then used as a masking element when etching the substrate pattern into the substrate. A second photo resist pattern is formed over the substrate pattern. An overlay measurement is executed of the second photo resist pattern to the substrate pattern.

Abstract: A test voltage having a first voltage or a second voltage is applied to an output terminal of a complementary fuse that includes a first fuse to one end of which the first voltage is applied and the other end of which serves as the output terminal and a second fuse to one end of which the second voltage is applied and the other end of which is connected to the output terminal. The test voltage then stops being applied. In such a state, whether output data from the output terminal of the complementary fuse coincides with an expected value is determined. The result of determination is output as a test result.

Abstract: A method for patterning a wafer includes performing a first patterning on a wafer, and after performing the first patterning, calculating a simulated dose mapper (DoMa) map predicting a change in critical dimensions of the wafer due to performing a second patterning on the wafer. The method further includes performing the second patterning on the wafer. Performing the second patterning includes adjusting one or more etching parameters of the second patterning in accordance with differences between the simulated DoMa map and desired critical dimensions of the wafer.

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with a line shaped laser beam profile laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.

Abstract: A semiconductor device is provided with: a semiconductor substrate; an insulation film formed above the semiconductor substrate; a pad formed on the insulation film, the pad including a trace; a first passivation film formed on the insulation film, located adjacent the pad, and separated from the pad; and a second passivation film formed on the first passivation film and the pad, the second passivation film covering the trace, and the second passivation film including an opening which exposes a part of the pad.

Abstract: A mounting system includes a jig storage that stores an identifier of a component mounted on a circuit board with an identifier of a jig relative to which the component is provided, a component storage that stores an identifier of a circuit board with an identifier of a component to be mounted on the circuit board, a first identification unit that identifies a new component to be mounted on a new circuit board unit and a current component mounted on a circuit board unit currently being manufactured from the component storage when the new component is to be mounted, a second identification unit that compares the identified new component with the identified current component to identify a current component not included in the new component, and an emitter that causes light to be emitted via a light emitting element on a jig with the identified current component.

Abstract: A packaged semiconductor device includes a semiconductor substrate, a metal pad, a metal base, a polymer insulating layer, a copper-containing structure and a conductive bump. The metal pad and the metal base are disposed on the semiconductor substrate. The polymer insulating layer overlies the metal base and the semiconductor substrate. The copper-containing structure is disposed over the polymer insulating layer, and includes a support structure and a post-passivation interconnect (PPI) line. The support structure is aligned with the metal base. The PPI line is located partially within the support structure, and extends out through an opening of the support structure, in which a top of the support structure is elevated higher than a top of the PPI line. The conductive bump is held by the support structure.

Abstract: Provided herein are a method and apparatus for the formation of conductive films on a substrate using precise sintering of a conductive film and thermal management of the substrate during sintering. In particular, a method may include depositing a conductive metal-based ink on a translucent or transparent substrate, positioning a mask between the deposited conductive metal-based ink and a light source, exposing the mask and the underlying deposited conductive metal-based ink to the light source, sintering the conductive metal-based ink exposed to the light source, and cleaning the non-sintered conductive metal-based ink from the translucent or transparent substrate. The mask may be configured to shield at least a portion of the conductive metal-based ink from the light source. The portion of the conductive metal-based ink shielded from the light source may remain non-sintered in response to the sintering of the conductive metal-based ink exposed to the light source.

Abstract: A polishing method is used for polishing a substrate such as a semiconductor wafer to a flat mirror finish. A method of polishing a substrate by a polishing apparatus includes a polishing table (100) having a polishing surface, a top ring (1) for holding a substrate and pressing the substrate against the polishing surface, and a vertically movable mechanism (24) for moving the top ring (1) in a vertical direction. The top ring (1) is moved to a first height before the substrate is pressed against the polishing surface, and then the top ring (1) is moved to a second height after the substrate is pressed against the polishing surface.

Abstract: A method of controlling polishing includes polishing a substrate, during polishing monitoring the substrate with an in-situ monitoring system, the monitoring including generating a signal from a sensor, and filtering the signal to generate a filtered signal. The signal includes a sequence of measured values, and the filtered signal including a sequence of adjusted values. The filtering includes for each adjusted value in the sequence of adjusted values, generating at least one predicted value from the sequence of measured values using linear prediction, and calculating the adjusted value from the sequence of measured values and the predicted value. At least one of a polishing endpoint or an adjustment for a polishing rate is determined from the filtered signal.

Abstract: A method and an apparatus of etching a semiconductor wafer are provided. The etching apparatus of a semiconductor wafer having a marker inside includes: a monitoring device capable of monitoring a surface of the semiconductor wafer so as to detect the marker; a nozzle capable of jetting a mixed gas that contains hydrogen fluoride and ozone onto the surface of the semiconductor wafer; a regulator capable of adjusting at least one of hydrogen fluoride concentration and ozone concentration in the mixed gas; and a controller capable of determining whether the marker is detected by the monitoring device and terminating the etching process.

Abstract: The present disclosure relates to a method of generating a scaled integrated chip design by scaling a FEOL and a BEOL of an original IC design at different scaling ratios, and an associated apparatus. In some embodiments, the method is performed by forming an original integrated chip (IC) design that is a graphical representation of an integrated chip. The original IC design has a front-end-of-the-line (FEOL) section, a back-end-of-the-line (BEOL) section, and a middle-of-the-line (MOL) section that is disposed between the FEOL and BEOL sections. A scaled integrated chip design is formed by scaling (i.e., shrinking) the FEOL section and the BEOL section of the original integrated chip design at different scaling ratios, and by scaling different design layers within the MOL section at different scaling ratios to avoid misalignment errors between the FEOL section and the BEOL section.

Abstract: Semiconductor devices and fabrication methods for simultaneously forming a 3T-FinFET and a 4T-FinFET on a same substrate are provided. A first fin and a second fin can be formed on a semiconductor substrate. The first fin has a top surface higher than the second fin. A first gate dielectric layer and a first gate can be formed across the first fin. A second gate dielectric layer and a second gate can be formed across the second fin. An interlayer dielectric layer can be formed to cover the first gate, the second gate, and the semiconductor substrate. A first portion of the interlayer dielectric layer, a portion of the first gate, and a portion of the first gate dielectric layer, over the first fin, and a second portion of the interlayer dielectric layer over the second fin can be removed to expose the second gate.

Abstract: A method for measuring critical dimension (CD) includes steps of: scanning at least one area of interest of a die to obtain at least one scanned image; aligning the scanned image to at least one designed layout pattern to identify a plurality of borders within the scanned image; and averaging distances each measured from the border or the plurality of borders of a pattern associated with a specific type of CD corresponding to the designed layout pattern to obtain a value of CD of the die. The value of critical dimensions of dies can be obtained from the scanned image with lower resolution which is obtained by relatively higher scanning speed, so the above-mentioned method can obtain value of CD for every die within entire wafer to monitor the uniformity of the semiconductor manufacturing process within an acceptable inspection time.

Abstract: A method of detecting an asymmetric portion of an overlay mark includes forming a plurality of virtual overlay marks having a plurality of virtual asymmetric portions. The virtual asymmetric portions may have different sizes with respect to a reference model profile of a reference overlay mark. Virtual information with respect to each virtual overlay mark may be obtained. The virtual information of the virtual overlay marks may be compared with actual information of an actual overlay mark to identify virtual information of the virtual overlay mark corresponding to the actual information of the actual overlay mark. Thus, measuring the overlay of the actual overlay mark may be performed under than the actual asymmetric portion may be excluded from the actual overlay mark, so that the overlay may be accurately measured. As a result, errors may not be generated in a correcting process to a layer using the accurate overlay.

Abstract: The present disclosure relates to the field of integrated circuit packaging and, more particularly, to packages using embedded microelectronic die applications, such a bumpless build-up layer (BBUL) designs. Embodiments of the present description relate to the field of alignment correction of microelectronic dice within the bumpless build-up layer packages. This alignment correction may comprise characterizing the misalignment of each microelectronic die mounted on a carrier and forwarding this characterization, along with data regarding the orientation of the carrier, to processing equipment that can compensate for the misalignment of each microelectronic die.

Abstract: A method of modifying a substrate carrier to improve process performance includes depositing material or fabricating devices on a substrate supported by a substrate carrier. A parameter of layers deposited on the substrate is then measured as a function of their corresponding positions on the substrate carrier. The measured parameter of at least some devices fabricated on the substrate or a property of the deposited layers is related to a physical characteristic of substrate carrier to obtain a plurality of physical characteristics of the substrate carrier corresponding to a plurality of positions on the substrate carrier. The physical characteristic of the substrate carrier is then modified at one or more of the plurality of corresponding positions on the substrate carrier to obtain desired parameters of the deposited layers or fabricated devices as a function of position on the substrate carrier.

Abstract: An integrated circuit with probeable and routable interfaces is disclosed. The integrated circuit includes multiple micro-pillars that are attached to the surface of the integrated circuit, and multiple macro-pillars also attached to the surface of the integrated circuit. The micro-pillars provide an electrical interface to the integrated circuit during regular operation. The macro-pillars provide an electrical interface to the integrated circuit both during regular operation and during testing of the integrated circuit.

Abstract: Disclosed is a manufacturing method of a semiconductor device including a step of attaching semiconductor wafers together, in which it is prevented that the bonding strength between the attached semiconductor wafers may be decreased due to a void caused between the two semiconductor wafers. Moisture, etc., adsorbed to the surfaces of the semiconductor wafers is desorbed by performing a heat treatment on the semiconductor wafers after cleaning the surfaces thereof with pure water. Subsequently, after a plasma treatment is performed on the semiconductor wafers, the two semiconductor wafers are attached together. The wafers are firmly bonded together by subjecting to a high-temperature heat treatment.

Abstract: According to various embodiments of the disclosure, an apparatus and method for enhanced deposition and etch techniques is described, including a pedestal, the pedestal having at least two electrodes embedded in the pedestal, a showerhead above the pedestal, a plasma gas source connected to the showerhead, wherein the showerhead is configured to deliver plasma gas to a processing region between the showerhead and the substrate and a power source operably connected to the showerhead and the at least two electrodes with plasma being substantially contained in an area which corresponds with one electrode of the at least two electrodes.

Abstract: A method and system for real-time, in-line calculations of opto-electronic properties and thickness of the layers of multi-layered transparent conductive oxide stacks of photovoltaic devices is provided. The method and system include taking measurements of each layer of the stack during deposition thereof. The measurements are then used to calculate the opto-electronic properties and thicknesses of the layers in real-time.

Abstract: A method is provided for forming multiple-LED (light-emitting-diode) light emitters from a plurality of LEDs, wherein the number of LEDs in each emitter is an integer M. The method includes providing a plurality of LEDs, each of the LEDs characterized by a first parameter and a second parameter, which are related to color coordinates CIEx and CIEy in a chromaticity diagram. The method also includes determining first and second parameter X0 and Y0 for a target color. The method further includes, for all possible combinations of M LEDs out of the plurality of LEDs, determining a first group parameter and a second group parameter based on the first and second parameters for all of the M LEDs, and selecting a group of M LEDs whose first group parameter and second group parameter are closest to X0 and Y0 as a candidate for forming a light emitter of M LEDs.

Abstract: A warp correction apparatus includes an injection mechanism including a nozzle that performs injection treatment, an adsorption table that holds the semiconductor element substrate by adsorption at a principal surface side or a film surface side, a moving mechanism that moves the adsorption table so that the semiconductor element substrate relatively moves with respect to an injection area of an injection particle by the nozzle, an injection treatment chamber that houses the semiconductor element substrate held on the adsorption table and in the interior of which injection treatment is performed, a measurement mechanism that measures a warp of the semiconductor element substrate, and a control device that, based on a difference between a target warp amount and a warp amount measured by the measurement mechanism, performs at least either one of a setting processing of an injection treatment condition of the injection mechanism and an accept/reject determination of the semiconductor element substrate for which

Abstract: A mask inspection microscope is provided for characterizing a mask having a feature. The mask inspection microscope is configured to generate an aerial image of at least one segment of the feature of the mask, acquire a spatially resolved intensity distribution of the aerial image, and determine a total intensity from the intensities of at least one region of the aerial image.

Abstract: The present invention is a cooling block that forms an electrode for generating a plasma for use in a plasma process, and includes a channel for a cooling liquid, the cooling block comprising: a first base material and a second base material respectively made of aluminum, at least one of the first and second base materials having a recess for forming a channel for a cooling liquid; and a diffusion bonding layer, in which zinc is diffused in aluminum, and an anti-corrosion layer of a zinc oxide film, the layers being formed by interposing zinc between the first and second base materials, and by bonding the first and second base materials with zinc interposed therebetween in a heating atmosphere containing oxygen.

Abstract: A method of operating a charged particle beam device is provided. The charged particle beam device includes a beam separator that defines an optical axis, and includes a magnetic beam separation portion and an electrostatic beam separation portion. The method includes generating a primary charged particle beam, and applying a voltage to a sample, the voltage being set to a first value to determine a first landing energy of the primary charged particle beam. The method further includes creating an electric current in the magnetic beam separation portion, the current being set to a first value to generate a first magnetic field, and applying a voltage to the electrostatic beam separation portion, the voltage being set to a first value to generate a first electric field.

Abstract: A defect inspection apparatus is disclosed that includes a stage, a photosensitive element, and a controller. The stage can support a semiconductor element that has a plurality of complete dies and partial dies surrounding the complete dies. The photosensitive element is located above the stage. The controller is electrically connected to the photosensitive element to drive the photosensitive element to inspect the defects of the complete dies and the partial dies.

Abstract: The present invention provides a processing apparatus using a scanning electron microscope, which includes the scanning electron microscope having an electron optical system radiating and scanning a focused electron beam on a sample placed on a stage to image the sample, and an image processing/control section which controls the scanning electron microscope and processes the image obtained by imaging with the scanning electron microscope. The electron optical system of the scanning electron microscope has image shift electrodes comprised of electrostatic electrodes, the image shift electrodes moving a position at which to apply the focused electron beam onto the sample with the stage stopped to thereby shift a region in which the sample is to be imaged.

Abstract: A method and system for updating tuning parameters associated with a controller without repetitive compilation of a controller code. The controller code represents an algorithm associated with the controller and can be compiled separately from a data set representing a solution for an optimization problem and also from a data set representing parameters required for prediction. The algorithm can be implemented in a programming language code suitable for implementation on an embedded platform or other types of computer platforms. The data sets can be represented in a specified data structure and the variables associated with the data structure can be declared in the controller template code. The variables can be updated independently without varying the compiled code associated with the controller algorithm that is referring to the variables. The controller can also be updated while the controller actively performs online.

Abstract: A method of controlling polishing includes receiving user input through a graphical user interface selecting a function, the function including at least one parameter that can be varied, polishing a substrate, monitoring a substrate during polishing with an in-situ monitoring system, generating a sequence of values from measurements from the in-situ monitoring system, fitting the function to the sequence of values, the fitting including determining a value of the at least one parameter that provides a best fit of the function to the sequence of values, determining a projected time at which the function equals a target value, and determining at least one of a polishing endpoint or an adjustment for a polishing rate based on the projected time.

Abstract: A method is capable of monitoring the polishing surface of the polishing pad without removing the polishing pad from the polishing table. The method includes: conditioning the polishing surface of the polishing pad by causing a rotating dresser to oscillate on the polishing surface; measuring a height of the polishing surface when the conditioning of the polishing surface is performed; calculating a position of a measuring point of the height on a two-dimensional surface defined on the polishing surface; and repeating the measuring of the height of the polishing surface and the calculating of the position of the measuring point to create height distribution in the polishing surface.

Abstract: Disclosed is a semiconductor device. For instance, the semiconductor device includes a main via formed on a dielectric and a ground via formed in a circular arc shape and spaced apart from the main via. The semiconductor device is superior in electric characteristics such as insertion loss or reflection loss and allows efficient use of space.

Abstract: In accordance with an embodiment, a sample includes a base material and a metal-based heavy element compound. The base material includes a tunnel structure portion with a cavity portion. The metal-based heavy element compound fills the cavity portion of the tunnel structure portion. The metal-based heavy element compound has a thickness that at least locally allows passage of a charged particle beam.

Abstract: A number of wafers of a same semiconductor device are inspected to generate a plurality of candidate defect lists for identifying systematic defects. Each candidate defect list comprises a plurality of candidate defects obtained from inspecting one of the wafers. Each candidate defect is represented by a plurality of defect attributes including a defect location. The candidate defects in every one or more candidate defect lists are processed as a set by stage one grouping and filtering to generate a stage one defect list for each set. The candidate defects in all the stage one defect lists are then processed together by stage two grouping and filtering to generate a final defect lists for systematic defects. The defect attributes of each defect and a design pattern clip extracted from a design database based on the defect location are used in the hierarchical grouping and filtering.