Abstract: Concentration of metal element which promotes crystallization of silicon and which exists within a crystal silicon film obtained by utilizing the metal element is reduced. A first heat treatment for crystallization is implemented after introducing nickel to an amorphous silicon film. Then, after obtaining the crystal silicon film, another heat treatment is implemented within an oxidizing atmosphere at a temperature higher than that of the previous heat treatment. A thermal oxide film is formed in this step. At this time, gettering of the nickel element into the thermal oxide film takes place. Then, the thermal oxide film is removed. Thereby, a crystal silicon film having low concentration of the metal element and a high crystalinity can be obtained.

Abstract: A method for fabricating a triode field emitter array using carbon nanotubes having excellent electron emission characteristics is provided. In the method for fabricating a triode-structure carbon nanotube field emitter array, a catalyst layer is formed on a cathode electrode without forming a base layer, and carbon nanotubes are grown on the catalyst layer using a Spind't process. In this method, a non-reactive layer is formed on a catalyst layer outside the micro-cavity such that the carbon nanotubes can be grown only on the catalyst within the micro-cavity. Accordingly, even though a separation layer is etched and removed, since carbon nanotubes do not exist outside the micro-cavity, it does not happen that carbon nanotubes are drifted into the micro-cavities. Therefore, the fabrication yield is increased, and the fabrication cost is decreased.

Abstract: One or more capacitors are formed using thermally oxidized films formed on a silicon layer of an SOI substrate. The capacitors may be formed alone or together with other semiconductor elements on a single SOI substrate. A diffused layer having an impurity in a high density is first formed on the silicon layer, and then an oxidized film is formed on the diffused layer by thermal oxidation. Then, contaminants in the oxidized film are driven-out under a high temperature heat treatment, thereby to improve quality of the oxidized film, such as durability against a high voltage. Plural capacitors may be formed using oxidized films having a respectively different thickness, by repeating thermal oxidation and removal of the oxidized film.

Abstract: An SRAM cell includes a pair of N channel transistors acting as inverting circuits, a pair of N channel transistors which perform the control function for the cell, and a pair of N channel thin film transistors in depletion mode with gate and source shorted to provide load devices for the N channel inverter transistors of the SRAM cell.

Abstract: Improved methods and structures are provided that are lateral to surfaces with a (110) crystal plane orientation such that an electrical current of such structures is conducted in the <110> direction. Advantageously, improvements in hole carrier mobility of approximately 50% can be obtained by orienting the structure's channel in a (110) plane such that the electrical current flow is in the <110> direction. Moreover, these improved methods and structures can be used in conjunction with existing fabrication and processing techniques with minimal or no added complexity. Embodiments of a method of forming an integrated circuit include forming a trench in a silicon wafer. A trench wall of the trench has a (110) crystal plane orientation. A semiconductor device is also formed lateral to the trench wall such that the semiconductor device is capable of conducting an electrical current in a <110> direction. One method of the present invention provides for forming an integrated circuit.

Abstract: This invention pertains to a method for forming thin films on substrates wherein the films are produced by applying a solution of an electrically insulating, heat-curing resin onto the substrate, evaporating the solvent and exposing the resin to high energy radiation to cure the resin. The resin solution contains a substance selected from solvents and gas generating additives that causes the dedensification of the film during the cure of the resin. This results in a film having a dielectric constant of below 2.7. This invention also pertains to a semiconductor device having an interconnect structure comprising at least one electrically conductive layer with an interposed insulating layer having a dielectric constant of less than 2.7 wherein the insulating layer is produced by the method of this invention.

Abstract: A method for crystallizing an amorphous silicon thin-film is provided, in which amorphous silicon thin-films on a large-area glass substrate for use in a TFT-LCD (TFT-Liquid Crystal Display) are crystallized uniformly and quickly by a scanning method using a linear lamp to prevent deforming of the glass substrate. The crystallization method includes the steps of forming an amorphous silicon thin-film on a glass substrate, and illuminating a linear light beam on the amorphous silicon thin-film from the upper portion of the glass substrate according to a scanning method. The crystallization method is applied to a polycrystalline silicon thin-film transistor manufacturing method including the steps of forming an amorphous silicon thin-film on a glass substrate, and crystallizing the amorphous silicon of the thin-film transistor according to a scanning method using a linear light beam.

Abstract: A method for crystallizing an amorphous silicon thin-film is provided, in which amorphous silicon thin-films on a large-area glass substrate for use in a TFT-LCD (TFT-Liquid Crystal Display) are crystallized uniformly and quickly by a scanning method using a linear lamp to prevent deforming of the glass substrate. The crystallization method includes the steps of forming an amorphous silicon thin-film on a glass substrate, and illuminating a linear light beam on the amorphous silicon thin-film from the upper portion of the glass substrate according to a scanning method. The crystallization method is applied to a polycrystalline silicon thin-film transistor manufacturing method including the steps of forming an amorphous silicon thin-film on a glass substrate, and crystallizing the amorphous silicon of the thin-film transistor according to a scanning method using a linear light beam.

Abstract: A semiconductor device is disclosed including a first insulating film having a contact hole and being formed on a substrate. A first impurity region is formed in the active layer on the bottom of the contact hole, and a second impurity region is formed in the active layer on the first insulating film outside the contact hole. In addition, a semiconductor region is formed in the active layer on the sidewall of the contact hole, and a second insulating film is formed on the first impurity region in the contact hole. A gate electrode is formed on the second insulating film.

Abstract: A method of manufacturing a semiconductor device which has a crystalline silicon film comprises the steps of forming crystal nuclei in a surface region of an amorphous silicon film and then growing the crystals from the nuclei by a laser light. Typically the crystal nuclei are silicon crystals or metal silicides having an equivalent structure as silicon crystal.

Abstract: A MOS-gated power device includes a plurality of elementary functional units, each elementary functional unit including a body region of a first conductivity type formed in a semiconductor material layer of a second conductivity type having a first resistivity value. Under each body region a respective lightly doped region of the second conductivity type is provided having a second resistivity value higher than the first resistivity value.

Abstract: The method includes patterning a first polysilicon layer on a substrate. A first dielectric having a first via hole is defined over the substrate. A second polysilicon layer is formed along the surface of the first dielectric layer and refilled into the first via hole. Then, an etching is used to etch the layer. A residual portion of the layer is located at the lower portion of the first via hole. An undoped polysilicon is then patterned on the first dielectric layer and along the surface of the first via hole. An isolation structure is then refilled into the first via hole. An oxide layer is formed on the first polysilicon, the first dielectric layer and the upper surface of isolation structure to act as the gate oxide of the TFT. Then, the oxide and the first dielectric layer are etched to define a second via hole. A further polysilicon layer is pattern on the first dielectric layer and refilled into the second via hole for defining the gate.

Abstract: A memory cell configuration in a semiconductor substrate is proposed, in which the semiconductor substrate is of the first conductivity type. Trenches which run parallel to one another are incorporated in the semiconductor substrate, and first address lines run along the side walls of the trenches. Second address lines are formed on the semiconductor substrate, transversely with respect to the trenches. Semiconductor substrate regions, in which a diode and a dielectric whose conductivity can be changed are arranged, are located between the first address lines and the second address lines. A suitable current pulse can be used to produce a breakdown in the dielectric, with information thus being stored in the dielectric.

Abstract: There are provided a double-diffused MOS (Metal Oxide Semiconductor) transistor and a fabricating method thereof. In the double-diffused MOS transistor, a buried layer of a first conductive type and an epitaxial layer of the first conductive type are sequentially formed on a semiconductor substrate, and a gate electrode is formed on the epitaxial layer of the first conductive type with interposition of a gate insulating film. Source and drain regions of the first conductive type are formed in the surface of the epitaxial layer of the first conductive type in self-alignment and non-self-alignment with the gate electrode, respectively. A body region of a second conductive type is formed in the surface of the epitaxial layer of the first conductive type to be surrounded by the source region of the first conductive type, and a bulk bias region of the second conductive type is formed in the body region of the second conductive type under the source region of the first conductive type.

Abstract: An encapsulation process for flip-chip bonding chips to a substrate encapsulates solder balls on the chip in a separate encapsulation process in which the chip is coated with encapsulation layer and then a portion of the encapsulation layer is removed to expose a portion of the solder balls.

Abstract: A thin film transistor includes a first insulating layer and a first conductive layer formed on a semiconductor substrate, a second insulating layer, a second conductive layer and a third insulating layer sequentially formed on the first conductive layer, a contact hole formed in the second insulating layer, second conductive layer and third insulating layer, a gate insulating layer formed along the sidewall of the contact hole, and a third conductive layer formed on the contact hole formed with the gate insulating layer thereon and surface of the third insulating layer to be used as a channel region and a source region by implanting an impurity, in which a drain region, a gate electrode and the source region are stacked, or vertically aligned, on the substrate to allow a cell to occupy a small area for accomplishing high packing density of the cell and permit the gate electrode to encircle the channel region for improving a characteristic of the transistor, thereby stabilizing the cell.

Abstract: A semiconductor chip (105') and a substrate (102) are bonded with an organic adhesive layer (409) containing conductive particles (406), and a pad (405) and an electrode (412) are mutually, electrically connected through the conductive particles (406).The semiconductor chip (105') is formed by contacting a semiconductor wafer (105) attached to a tape (107) with an etchant while rotating the semiconductor wafer (105) within an in-plane direction at a high speed or reciprocating the wafer (105) laterally to uniformly etch the semiconductor wafer (105) thereby reducing the thickness thereof, and dicing the thus reduced wafer. The resultant thin chip (105') is hot-pressed by means of a heating head (106) for bonding on the substrate (102).In this way, a thin semiconductor chip can be formed stably at low costs and bonded on a substrate without causing any crack of the chip, thereby obtaining a semiconductor device which is unlikely to break owing to the bending stress from outside.

Abstract: The invention encompasses DRAM constructions, capacitor constructions, conductive contacts, integrated circuitry, methods of forming DRAM constructions, and methods of forming capacitor constructions.

Abstract: A field effect transistor occupying a small area and a semiconductor device using the same can be obtained. A gate electrode is provided on a substrate on which a source region is provided with a first interlayer insulating film interposed therebetween. The gate electrode is covered with a second interlayer insulating film. A contact hole for exposing a part of the surface of the source region is provided so as to penetrate through the first interlayer insulating film, the gate electrode, and the second interlayer insulating film. A sidewall surface of the contact hole is covered with a gate insulating film. A first semiconductor layer of a first conductivity type is provided on the surface of the source region in contact therewith up to the lower surface of the gate electrode. A channel semiconductor layer is provided on the surface of the first semiconductor layer up to the upper surface of the gate electrode.

Abstract: A method of fabricating a DRAM cell and the DRAM cell include a substrate, and a bit line formed in a first direction on the substrate. A channel region is then formed on a portion of the bit line. The channel region has a lateral surface extending vertically from the bit line. A first insulating layer is formed over the substrate, excluding the channel region, and is formed on at least a portion of the lateral surface of the channel region. A gate electrode is formed on a portion of the first insulating layer, which is on the portion of the lateral surface of the channel region, and a word line, connected to the gate electrode, is formed in a second direction on the first insulating layer. A second insulating layer is then formed over a portion of the substrate. The second insulating layer has a contact hole which exposes the channel region. Next, a capacitor is formed on a portion of the second insulating layer and on the channel region via the contact hole.

Abstract: A MOS-technology power device integrated structure includes a first plurality of elongated doped semiconductor stripes of a first conductivity type formed in a semiconductor layer of a second conductivity type, each including an elongated source region of the first conductivity type, an annular doped semiconductor region of the first conductivity type formed in the semiconductor layer and surrounding and merged with the elongated stripes, insulated gate stripes extending over the semiconductor layer between adjacent elongated stripes, a plurality of conductive gate fingers extending over and electrically connected to the insulated gate stripes, and a plurality of source metal fingers, each one extending over a respective elongated stripe and contacting the elongated stripe and the respective elongated source region, so that the source metal fingers and the conductive gate fingers are interdigitated.

Abstract: A method of forming, on an ultra-thin SOI substrate, an ESD protected device, includes: preparing a single crystal silicon substrate, including forming insulated areas thereon and forming selectively conductive areas thereon; doping the selectively conductive layers with dopants; growing, epitaxially, silicon layers over selected insulated areas and the doped, selectively conductive areas; heating the substrate and the structures formed thereon at between about 850.degree. C. to 1150.degree. C. for between about 30 minutes to three hours to redistribute the dopant into the epitaxially grown silicon layer; completing the fabrication of additional layers in the structure; and metallizing the structure.

Abstract: Improvements in the compactness and performance of integrated circuit devices are gained through the fabrication of vertical transistors for which channel sizes are determined by the accuracy of etch techniques rather than the resolution of photolithographic techniques. A method of fabricating an integrated circuit includes forming a plurality of doped layers in a series of depths in a substrate wafer, and etching a trench in the substrate wafer. The trench extends through the doped layers at a plurality of depths and is bounded by vertical sidewalls and a planar horizontal floor. The method further includes forming a conductive sidewall spacer adjacent to the vertical sidewalls of the trench.

Abstract: After a contact hole for an aluminum gate electrode is formed, a nickel film is formed by electroless plating, and coincidently, a natural oxide film formed on the gate electrode is removed by wet etching. This provides a reliable contact between the gate electrode and an external lead-out wiring line.

Abstract: A vertical field effect transistor (1) and a method of manufacturing thereof are disclosed, in which a buried layer (3) of a conduction type opposite to that of a substrate (2) is formed to a predetermined depth in the substrate (2) by ion implantation. The bottom of recess (2a) for forming a protrusion (2b) on the substrate (2) is located within the corresponding one of the buried layer (3). The width of the recess (2a) is set smaller than the width of the buried layer (3). The surface of the protrusion (2b) and the bottom of the recess (2a) are formed with impurities regions (4a, 4b; 5a, 5b) constituting a source and a drain, respectively. A channel length (L) of the channel region formed on the side wall of the protrusion (2b) is defined by the distance between the buried layer (3) and the impurities regions (5a, 5b) on the surface of the protrusion (2b).

Abstract: A transistor and a fabrication method thereof, and in particular, a technique for compatibly improving reduction of an ON-state voltage and reduction of a turn-off time. First and second emitter layers are selectively formed in isolation from each other on a surface of a base layer 3, and a channel region 6 opposed to a gate electrode 8 through a gate insulating film is formed therebetween. In an ON state, a base current I.sub.b is supplied from a base electrode, while a prescribed gate voltage is applied to the gate electrode. The first and second emitter layers couple with each other and function as a single emitter layer, whereby the ON-state voltage becomes a low value of about the same degree as a bipolar transistor. When bringing a device into an OFF state, supply of the base current I.sub.b is stopped while a zero (or negative) voltage is applied to the gate electrode. Consequently, coupling between the first emitter layer and the second emitter layer is canceled, whereby a second collector current I.

Abstract: A merged power device structure, of the emitter-switching type, in which the emitter of the bipolar power transistor has a minimum-width pattern which is aligned to the trenches of a trench control transistor. Thus the current density of the bipolar is maximized, since the emitter edge length per unit area is increased. The parasitic base resistance of the bipolar can also be reduced.

Abstract: An integrated circuit and fabrication method includes a vertical transistor for a memory cell in a dynamic random access memory (DRAM) or other integrated circuit. Vertically oriented access transistors are formed on semiconductor pillars on buried bit lines. Buried gates and body contacts are provided for each access transistor on opposing sides of the pillars. Buried word lines extend in first alternating trenches orthogonal to the bit lines. The buried word lines interconnect ones of the gates. Buried body lines extend in second alternating trenches orthogonal to the bit lines. The buried body lines interconnect body regions of adjacent access transistors. Unitary and split-conductor gate and body lines are provided for shared or independent signals to access transistors on either side of the trenches. In one embodiment, the memory cell has a surface area that is approximately 4 F.sup.2, where F is a minimum feature size. Bulk-semiconductor and semiconductor-on-insulator (SOI) embodiments are provided.

Abstract: A MOS-gated power device includes a plurality of elementary functional units, each elementary functional unit including a body region of a first conductivity type formed in a semiconductor material layer of a second conductivity type having a first resistivity value. Under each body region a respective lightly doped region of the second conductivity type is provided having a second resistivity value higher than the first resistivity value.

Abstract: A field effect transistor comprising source and drain regions, a channel region composed of a semiconductor layer formed between the source and drain regions and gate electrodes disposed to at least three surfaces surrounding the channel region. The structure can increase the number of carriers induced in the channel region and enhance the current driving performance and mutual conductance as compared with the single gate structure or double gate structure.

Abstract: A method for forming a trench transistor structure begins by forming a buried layers (12 and 16) and a doped well (22) in a substrate (10) via epitaxial growth processing. A trench region (24) is then etched into the substrate (10) to expose a the layer (12). A conductive sidewall spacer (28) is formed within the trench (24) as a gate electrode. The spacer (28) gates a first transistor (12, 28, 32) located adjacent a first half of the trench (24) and a second transistor (12, 28, 34) located adjacent a second half of the trench (24). Region (12) is a common electrode wherein the channel regions of both the first and second transistor are coupled in a serial manner through the region (12).

Abstract: A method for forming a semiconductor structure on an active area mesa with minimal loss of field oxide deposited in isolation trenches adjacent the mesa. The trench insulating material is protected by an etch barrier layer having at least a partial resistance to etchants used in further device processing steps. The barrier layer may also be deposited over the surface of the substrate to protect it from damage during device processing. The barrier layer may be removed by an etchant having a selectivity for the barrier layer over that of the surrounding device elements. Final processing of the device may be completed once the barrier layer is removed.

Abstract: A thin film transistor includes a substrate with a trench having first and second sides and a bottom, and a gate electrode at one of the first and second sides of the trench. The thin film transistor further includes a gate insulating layer on the entire surface of the substrate including the gate electrode, and an active layer on the gate insulating layer along the trench, the active layer having source and drain regions substantially outside the trench.

Abstract: A thin film transistor (TFT) comprises a n.sup.+ source region and a p.sup.+ drain separated by an undoped offset region, or the complementary structure with a p.sup.+ source and a n.sup.+ drain. By means of this arrangement in the offset region is conduction is by way of both electron and hole carriers and the offset region is conductivity modulated. The TFT of the present invention has lower on-resistance than a conventional thin film transistor.

Abstract: A MOS-technology power device integrated structure includes a first plurality of elongated doped semiconductor stripes of a first conductivity type formed in a semiconductor layer of a second conductivity type, each including an elongated source region of the first conductivity type, an annular doped semiconductor region of the first conductivity type formed in the semiconductor layer and surrounding and merged with the elongated stripes, insulated gate stripes extending over the semiconductor layer between adjacent elongated stripes, a plurality of conductive gate fingers extending over and electrically connected to the insulated gate stripes, and a plurality of source metal fingers, each one extending over a respective elongated stripe and contacting the elongated stripe and the respective elongated source region, so that the source metal fingers and the conductive gate fingers are interdigitated.

Abstract: A vertical double-gate field effect transistor includes a source layer, an epitaxial channel layer and a drain layer arranged in a stack on a bulk or SOI substrate. The gate oxide is thermally grown on the sides of the stack using differential oxidation rates to minimize input capacitance problems. The gate wraps around one end of the stack, while contacts are formed on a second end. An etch-stop layer embedded in the second end of the stack enables contact to be made directly to the channel layer.

Abstract: The present invention provides an optical link amplifier which reduces the attenuation of the optical signal passing through optical an link amplifier so as to have a fail-safe function to ensure the communication path of an optical signal even if abnormality occurs at an optical amplifier, and an wavelength multiplex laser oscillator in which the spectrum width of the laser beam is narrow and coupling coefficient with an optical fiber is increased.

Abstract: A process for fabricating Ultra Large Scale Integrated (ULSI) circuits in Silicon On Insulator (SOI) technology in which the device structures, which can be bipolar, FET, or a combination, are formed in vertical silicon sidewalls having insulation under and in back thereof so as to create SKI device structures. The silicon sidewall device SOI structures, when fabricated, take the form of cells with each cell having a plurality of either bipolar devices, FET devices, or a combination of these devices, such as collectors, emitters, bases, sources, drains, and gates interconnected within the planes of the regions of the devices in the cells and can be interconnected within the planes of the regions of devices in adjacent cells. Further, the interconnections to adjacent cells can be made from the back of the silicon sidewalls.

Abstract: A method of forming a thin film transistor over a substrate is provided whereby at least one of the source region or the drain region is conductively doped while preventing conductivity doping of the channel region without any masking of the channel region occurring by any separate masking layer.

Abstract: Vertical epitaxial SOI transistors and memory cells are disclosed. The devices are formed completely within a substrate trench and have a bulk channel epitaxially grown on an exposed surface of the substrate within the trench. The bulk channel is disposed proximate to a transistor gate electrode such that an inversion layer is formed therein when the gate electrode is appropriately biased. Back biasing of the bulk region is accomplished through the substrate. In the transistor embodiment, a first node diffusion and a second node diffusion are disposed at opposite ends of the bulk channel. In a memory cell configuration the access transistor is disposed above a trench storage node, which electrically connects with the transistor's second node diffusion. Arrays of the trench transistors and trench memory cells are also described. Further, fabrication methods for the various structures disclosed are presented. A novel wiring approach to construction of bit lines in a cell array is also set forth.