Abstract: A manufacturing method of pixel structure includes: sequentially forming a gate, a gate insulation layer, a semiconductor layer and a conductive layer on a substrate; forming a first patterned photoresist layer including multiple first photoresist blocks and multiple second photoresist blocks on the conductive layer; reducing the thickness of the first patterned photoresist layer until the second photoresist blocks are completely removed; forming a pixel electrode layer and a second photoresist layer on a partial pixel electrode layer; removing a part of the pixel electrode layer exposed by the second photoresist layer, a partial conductive layer and a partial semiconductor layer both under the removed pixel electrode layer to define a first electrode block, a second electrode block and a channel region; removing the remained first patterned photoresist layer and second photoresist layer and forming a protective layer and a common electrode layer on a part of the protective layer.

Abstract: A method for forming a conductor structure is provided. The method comprises: (1) providing a substrate; (2) forming a patterned dielectric layer with a first opening which exposes a portion of the substrate; forming a patterned organic material layer on the dielectric layer with a second opening which corresponds to the first opening and expose the exposed portion of the substrate; (3) forming a first barrier layer on the organic material layer and the exposed portion of the substrate; (4) forming a metal layer on the first barrier layer; and (5) removing the organic material layer, the first barrier layer thereon and the metal layer thereon.

Abstract: An object is to provide an n-channel transistor and a p-channel transistor having a preferred structure using an oxide semiconductor. A first source or drain electrode which is electrically connected to a first oxide semiconductor layer and is formed using a stacked-layer structure including a first conductive layer containing a first material and a second conductive layer containing a second material, and a second source or drain electrode which is electrically connected to a second oxide semiconductor layer and is formed using a stacked-layer structure including a third conductive layer containing the first material and a fourth conductive layer containing the second material are included. The first oxide semiconductor layer is in contact with the first conductive layer of the first source or drain electrode, and the second oxide semiconductor layer is in contact with the third and the fourth conductive layers of the second source or drain electrode.

Abstract: Provided is an image display device including thin film transistors on a substrate, including: gate lines and drain lines intersecting the gate lines, each thin film transistor having, in a channel region, a laminate structure in which a gate electrode, a gate insulating film, and a semiconductor layer are laminated in the stated order from the substrate side; and a pair of removal regions in which parts of the gate insulating film are removed, which are formed on both sides of the gate electrode and formed in a channel width direction of the channel region, in which when W represents a width of the gate electrode in the channel width direction of the channel region, and R represents a width of the gate insulating film in the channel width direction, which is sandwiched between the pair of removal regions, R?W is satisfied.

Abstract: In a method for manufacturing an organic transistor element, an electrode is subjected to wet etching into a predetermined pattern on an organic semiconductor layer. In the process for performing wet etching on the electrode so as to obtain a predetermined pattern, an etching liquid containing a dopant of the organic semiconductor layer is used to perform wet etching on the electrode and, simultaneously, the organic semiconductor layer is doped with the dopant.

Abstract: A display device including a thin film transistor with high electric characteristics and high reliability, and a method for manufacturing the display device in high yield are proposed. In a display device including a channel stop thin film transistor with an inverted-staggered structure, the channel stop thin film transistor with the inverted-staggered structure includes a microcrystalline semiconductor film including a channel formation region. An impurity region including an impurity element imparting one conductivity type is formed as selected in a region in the channel formation region of the microcrystalline semiconductor film which does not overlap with a source electrode or a drain electrode. In the channel formation region, a non-doped region, to which the impurity element imparting one conductivity type is not added, is formed between the impurity region, which is a doped region to which the impurity element is added, and the source region or the drain region.

Abstract: A pixel structure disposed on a substrate having an array of pixel areas is provided. The common electrode wire is positioned only in a portion of the pixel area. A first capacitance storage electrode is disposed in each of the pixel areas and electrically connected between two adjacent common electrode wires. A gate insulation layer covers the scan line, the gate electrode, the common electrode wire and the first capacitance storage electrode. A semiconductor layer is disposed on the gate insulation layer above the gate electrode. The source and the drain are disposed on two sides of the semiconductor layer. A passivation layer is disposed on the substrate to cover the data line, the source and the drain. The passivation layer above the drain has a contact window. A pixel electrode is electrically connected with the drain through the contact window.

Abstract: A fabricating method of a pixel structure is provided. A substrate has an array of pixel areas. The common electrode wire is positioned only in a portion of the pixel area. A first capacitance storage electrode is formed in each of the pixel areas and electrically connected between two adjacent common electrode wires. A gate insulation layer covers the scan line, the gate electrode, the common electrode wire and the first capacitance storage electrode. A semiconductor layer is formed on the gate insulation layer above the gate electrode. The source and the drain is formed on two sides of the semiconductor layer. A passivation layer is formed on the substrate to cover the data line, the source and the drain. A pixel electrode is formed in each of the pixel areas, and the pixel electrode is electrically connected with the drain through the contact window.

Abstract: A thin film transistor fabrication method allows forming a first photoresist pattern on a triple layer of insulation, conductive and metal films opposite to a semiconductor pattern. A first metal pattern and a conductive pattern are formed through an etch process before forming source and drain regions through a first ion injection process. A second photoresist pattern with a narrower width than that of the first photoresist pattern is derived from the first photoresist pattern. The first metal pattern is reformed into a second metal pattern with a narrower width than that of the second photoresist pattern. A process is performed that includes removing the second photoresist pattern, forming LDD (Lightly Doped Drain) regions in the semiconductor pattern, and forming GOLDD (Gate Overlap LDD) regions in the semiconductor pattern. A second insulation film is formed before forming source and drain electrodes on the second insulation film.

Abstract: A silicon compound film is dry etched by parallel-plate type dry etching using an etching gas including at least COF2.

Abstract: A method of producing a transistor includes providing a substrate including in order a first electrically conductive material layer and a second electrically conductive material layer. The first electrically conductive material layer has a thickness. A resist material layer is deposited over the second electrically conductive material layer. The resist material layer is patterned to expose a portion of the second electrically conductive material layer. Some of the second electrically conductive material layer is removed to expose a portion of the first electrically conductive material layer. The second electrically conductive material layer is caused to overhang the first electrically conductive material layer by removing some of the first electrically conductive material layer.

Abstract: A method for manufacturing a thin film transistor having high electric characteristics with high productivity. In the method for forming a channel region of a dual-gate thin film transistor including a first gate electrode and a second gate electrode which faces the first gate electrode with the channel region provided therebetween, a first microcrystalline semiconductor film is formed under a first condition for forming a microcrystalline semiconductor film in which a space between crystal grains is filled with an amorphous semiconductor, and a second microcrystalline semiconductor film is formed over the first microcrystalline semiconductor film under a second condition for promoting crystal growth.

Abstract: One of factors that increase the contact resistance at the interface between a first semiconductor layer where a channel is formed and source and drain electrode layers is a film with high electric resistance formed by dust or impurity contamination of a surface of a metal material serving as the source and drain electrode layers. As a solution, a first protective layer and a second protective layer including a second semiconductor having a conductivity that is less than or equal to that of the first semiconductor layer is stacked successively over source and drain electrode layers without exposed to air, the stack of films is used for the source and drain electrode layers.

Abstract: A photo-mask includes a first opaque pattern, a second opaque pattern, a transparent single slit, and a translucent pattern. The transparent single slit is disposed between the first opaque pattern and the second opaque pattern, and the width of the transparent single slit is substantially between 1.5 micrometers and 2.5 micrometers. The translucent pattern is connected to the first opaque pattern and the second opaque pattern.

Abstract: Objects are to provide a semiconductor device for high power application in which a novel semiconductor material having high productivity is used and to provide a semiconductor device having a novel structure in which a novel semiconductor material is used. The present invention is a vertical transistor and a vertical diode each of which has a stacked body of an oxide semiconductor in which a first oxide semiconductor film having crystallinity and a second oxide semiconductor film having crystallinity are stacked. An impurity serving as an electron donor (donor) which is contained in the stacked body of an oxide semiconductor is removed in a step of crystal growth; therefore, the stacked body of an oxide semiconductor is highly purified and is an intrinsic semiconductor or a substantially intrinsic semiconductor whose carrier density is low. The stacked body of an oxide semiconductor has a wider band gap than a silicon semiconductor.

Abstract: An LCD device is disclosed, to minimize the signal distortion by decreasing the instability of voltage in a-Si:H TFT of a gate driving signal output unit, which includes a signal controller for outputting first and second control signals Q and /Q; a pull-up transistor between a clock signal terminal CLK and a gate driving signal output terminal for receiving the first control signal Q, the pull-up transistor having a first gate electrode, a first source electrode and a first drain electrode, wherein the pull-up transistor has an asymmetric structure in a first area of the first source electrode overlapped with the first gate electrode and a second area of the first drain electrode overlapped with the first gate electrode; and a pull-down transistor connected between the gate driving signal output terminal and a ground voltage terminal, wherein the pull-down transistor receives the second control signal.

Abstract: A method for fabricating a pixel structure includes providing a substrate having a pixel area. A first metal layer, a gate insulator and a semiconductor layer are formed on the substrate and patterned by using a first half-tone mask or a gray-tone mask to form a transistor pattern, a lower capacitance pattern and a lower circuit pattern. Next, a dielectric layer and an electrode layer both covering the three patterns are sequentially formed and patterned to expose a part of the lower circuit pattern, a part of the lower capacitance pattern and a source/drain region of the transistor pattern. A second metal layer formed on the electrode layer and the electrode layer are patterned by using a second half-tone mask or the gray-tone mask to form an upper circuit pattern, a source/drain pattern and an upper capacitance pattern. A portion of the electrode layer constructs a pixel electrode.

Abstract: The thin film transistor manufacturing apparatus comprises a surface modification layer forming means, which forms a surface modification layer on a substrate, an illuminating part, which irradiates light that includes ultraviolet rays, a mask, on which the patterns of the source electrode and the drain electrode are drawn, a projection optical system, which illuminates a mask using light from the illuminating part and projects the pattern of the mask to the substrate as a pattern image, and a coating part, which coats a fluid electrode material to a region in which the surface modification layer has been modified by projection of the pattern image in order to form the source electrode and the drain electrode.

Abstract: The present invention provides a method for manufacturing a highly reliable semiconductor device with a small amount of leakage current. In a method for manufacturing a thin film transistor, etching is conducted using a resist mask to form a back channel portion in the thin film transistor, the resist mask is removed, a part of the back channel is etched to remove etching residue and the like left over the back channel portion, whereby leakage current caused by the residue and the like can be reduced. The etching step of the back channel portion can be conducted by dry etching using non-bias.

Abstract: A method for manufacturing a flexible semiconductor device includes (i) forming an insulating film on the upper surface of metal foil, (ii) forming an extraction electrode pattern on the upper surface of the metal foil, (iii) forming a semiconductor layer on the insulating film such that the semiconductor layer is in contact with the extraction electrode pattern, (iv) forming a sealing resin layer on the upper surface of the metal foil such that the sealing resin layer covers the semiconductor layer and the extraction electrode pattern, and (v) forming electrodes by etching the metal foil, the metal foil being used as a support for the insulating film, the extraction electrode pattern, the semiconductor layer, and the sealing resin layer formed in (i) to (iv) and used as a constituent material for the electrodes in (v). The metal foil need not be stripped, and a high-temperature process can be used.

Abstract: To provide a method for manufacturing a transistor which has little variation in characteristics and favorable electric characteristics. A gate insulating film is formed over a gate electrode; a semiconductor layer including a microcrystalline semiconductor is formed over the gate insulating film; an impurity semiconductor layer is formed over the semiconductor layer; a mask is formed over the impurity semiconductor layer, and then the semiconductor layer and the impurity semiconductor layer are etched with use of the mask to form a semiconductor stacked body; the mask is removed and then the semiconductor stacked body is exposed to plasma generated in an atmosphere containing a rare gas to form a barrier region on a side surface of the semiconductor stacked body; and a wiring over the impurity semiconductor layer of the semiconductor stacked body is formed.

Abstract: A gate driver on array of a display includes a substrate having a peripheral region, and a gate driver on array structure formed in the peripheral region. The gate driver on array structure includes a pull-down transistor, and the pull-down transistor has a gate electrode, an insulating layer, a semiconductor island, a source electrode, and a drain electrode. The semiconductor island extends out of both edges of the gate electrode, and extends out of an edge of the source electrode and an edge of the drain electrode.

Abstract: It is an object to reduce the effect of a characteristic of the edge portion of a channel forming region in a semiconductor film, on a transistor characteristic. An island-like semiconductor film is formed over a substrate, and a conductive film forming a gate electrode provided over the island-like semiconductor film with a gate insulating film interposed therebetween, is formed over the semiconductor film. In the semiconductor film, a channel forming region, a first impurity region forming a source or drain region, and a second impurity region are provided. The channel forming region is provided in a region which overlaps with the gate electrode crossing the island-like semiconductor film, the first impurity region is provided so as to be adjacent to the channel forming region, and the second impurity region is provided so as to be adjacent to the channel forming region and the first impurity region.

Abstract: An object is to improve the aperture ratio of a semiconductor device. The semiconductor device includes a driver circuit portion and a display portion (also referred to as a pixel portion) over the same substrate. The driver circuit includes a channel-etched thin film transistor for driver circuit and a driver circuit wiring formed using metal. Source and drain electrodes of the thin film transistor for the driver circuit are formed using a metal. A channel layer of the thin film transistor for the driver circuit is formed using an oxide semiconductor. The display portion includes a bottom-contact thin film transistor for a pixel and a display portion wiring formed using an oxide conductor. Source and drain electrode layers of the thin film transistor for the pixel are formed using an oxide conductor. A semiconductor layer of the thin film transistor for the pixel is formed using an oxide semiconductor.

Abstract: A display substrate includes a driving element, a switching element, a gate line, a data line, a driving voltage line and an electroluminescent element. The driving element includes a driving control electrode formed from a first conductive layer, and a driving input electrode and a driving output electrode formed from a second conductive layer. The switching element includes a switching control electrode formed from the second conductive layer, and a switching input electrode and a switching output electrode formed from a third conductive layer. The gate and data lines are formed from the second and third conductive layers, respectively. The driving voltage line is formed from the third conductive layer. Thus, misalignment between upper and lower patterns may be prevented to improve the reliability of a manufacturing process and increase an aperture ratio, thereby enhancing display quality.

Abstract: The display device having a thin film transistor formed on a substrate including a display portion is provided. The thin film transistor including: a gate electrode; a gate insulating film formed so as to cover the gate electrode; a semiconductor laminated film formed on top the gate insulating film so as to extend over the gate electrode, the semiconductor laminated film being formed by laminating at least a polycrystalline semiconductor film and an amorphous semiconductor film, a first electrode and a second electrode disposed on top of the semiconductor laminated film so as to be opposed to each other across a region superposing the gate electrode. In the display device, the semiconductor laminated film is formed immediately below a wiring extending from the first electrode and immediately below a wiring extending from the second electrode.

Abstract: A method of fabricating an array substrate includes forming a gate line and a gate electrode; forming a gate insulating layer, an intrinsic amorphous silicon layer, an inorganic material insulating layer and a heat transfer layer on the gate line and the gate electrode; irradiating a laser beam onto the heat transfer layer to crystallize the intrinsic amorphous silicon layer into a polycrystalline silicon layer; removing the heat transfer layer; patterning the inorganic insulating material layer using a buffered oxide etchant to form an etch-stopper corresponding to the gate electrode forming an impurity-doped amorphous silicon layer and a metal layer on the etch-stopper and the polycrystalline silicon layer; patterning the metal layer to form a data line, a source electrode and a drain electrode and forming a pixel electrode on the passivation layer.

Abstract: A display device including a thin film transistor with high electric characteristics and high reliability, and a method for manufacturing the display device with high mass-productivity. In a display device including an inverted-staggered channel-stop-type thin film transistor, the inverted-staggered channel-stop-type thin film transistor includes a microcrystalline semiconductor film including a channel formation region, and an impurity region containing an impurity element of one conductivity type is selectively provided in a region which is not overlapped with source and drain electrodes, in the channel formation region of the microcrystalline semiconductor film.

Abstract: A method for manufacturing a thin film transistor substrate including forming bus lines by etching a surface of a substrate to form bus line patterns and filling the bus line patterns with a bus line metal; forming a semiconductor channel layer at one portion of a pixel area defined by the bus lines; and forming source-drain electrodes on the semiconductor channel layer, a pixel electrode extending from the drain electrode within the pixel area, and a common electrode parallel with the pixel electrode. The bus lines are formed as being thicker but the bus lines are buried in the substrate so that the line resistance can be reduced and the step difference due to the thickness of bus line does not affect the device.

Abstract: When a transistor including a conductive layer having a three-layer structure is manufactured, three-stage etching is performed. In the first etching process, an etching method in which the etching rates for the second film and the third film are high is employed, and the first etching process is performed until the first film is at least exposed. In the second etching process, an etching method in which the etching rate for the first film is higher than that in the first etching process and the etching rate for a “layer provided below and in contact with the first film” is lower than that in the first etching process is employed. In the third etching process, an etching method in which the etching rates for the first to the third films are higher than those in the second etching process is preferably employed.

Abstract: A TFT includes a gate electrode, an active layer, a source electrode, a drain electrode, and a buffer layer. The gate electrode is formed on the substrate; the active layer is formed on the gate electrode. The source and drain electrodes, formed on the active layer, are separated by a predetermined distance. The buffer layer is formed between the active layer and the source and drain electrodes. The buffer layer has a substantially continuously varying content ratio corresponding to a buffer layer thickness. The buffer layer is formed to suppress oxidation of the active layer, and reduce contact resistance.

Abstract: A semiconductor device includes a body region having a source region, a drain region, a channel region interposed between the source region and the drain region, and a body region extension extending from an end of the channel region. A gate pattern is formed on the channel region and the body region, and a body contact connects the gate pattern to the body region. A sidewall of the body region extension is self-aligned to a sidewall of the gate pattern. Methods of forming semiconductor devices having a self-aligned body and a body contact are also disclosed.

Abstract: A thin film transistor, a manufacturing method thereof, and a display device having the same are disclosed. The thin film transistor includes a semiconductor layer formed on a substrate, a gate insulating layer formed on the substrate including the semiconductor layer, a gate electrode formed on the gate insulating above the semiconductor layer, source and drain electrodes connected to the semiconductor layer, and 3.5 to 4.5 protrusions formed on the semiconductor layer overlapped with the gate electrode. Malfunction of the thin film transistor and inferior image quality of the display device can be prevented by adjusting the number of protrusions to minimize leakage current and defects.

Abstract: A manufacturing method of a thin film transistor includes forming a pair of source/drain electrodes on a substrate, such that the source/drain electrodes define a gap therebetween; forming low resistance conductive thin films, which define a gap therebetween, on the source/drain electrodes; and forming an oxide semiconductor thin film layer on upper surface of the low resistance conductive thin films and in the gap defined between the low resistance conductive thin films so that the oxide semiconductor thin film layer functions as a channel. The low resistance conductive thin films and the oxide semiconductor thin film layer are etched so that side surfaces of the resistance conductive thin films and corresponding side surfaces of the oxide semiconductor thin film layer coincide with each other in a channel width direction of the channel. A gate electrode is mounted over the oxide semiconductor thin film layer.

Abstract: A thin film transistor substrate, wherein the moving area of electrons between source and drain electrodes of a thin film transistor (TFT) is minimized, the moving distance of electrons is increased, and the sizes of capacitors defined by a gate electrode together with the respective source and drain electrodes are identical to each other so that an off current generated when the TFT is off can be minimized; a method of manufacturing the thin film transistor substrate; and a mask for manufacturing the thin film transistor substrate. Accordingly, it is possible to minimize an off current induced due to a phenomenon of electron trapping by light.

Abstract: A method of forming a thin-film transistor array substrate is provided. A first mask is used to define a source, a drain and a channel on a substrate. A dielectric layer is formed to cover the source, the drain, the channel and the substrate. A second mask is used to define a patterned photoresist and the dielectric layer. A transparent conductive layer is formed to cover the patterned photoresist and the substrate. A lift-off process is performed to remove the patterned photoresist and a portion of the transparent conductive layer disposed on the patterned photoresist. A third mask is used to define a gate disposed on the dielectric layer.

Abstract: The present invention provides a manufacturing process using a droplet-discharging method that is suitable for manufacturing a large substrate in mass production. A photosensitive material solution of a conductive film is selectively discharged by a droplet-discharging method, selectively exposed to laser light, and developed or etched, thereby allowing only the region exposed to laser light to be left and realizing a source wiring and a drain wiring having a more microscopic pattern than the pattern itself formed by discharging. One feature of the source wiring and the drain wiring is that the source wiring and the drain wiring cross an island-like semiconductor layer and overlap it.

Abstract: A TFT array substrate includes a gate line, a gate electrode, and a gate pad on a substrate, each of which including stacked layers of a first metal and a transparent conductive material, respectively, a pixel electrode formed of the transparent conductive material, a gate insulation layer on the substrate including the gate line and the gate electrode, the gate insulation layer having first and second open areas exposing the pixel electrode and the gate pad, a semiconductor layer formed on the gate insulation layer, a data line crossing the gate line to define a sub-pixel region, a source electrode diverging from the data line, a drain electrode spaced apart from the source electrode and connected to the pixel electrode, a data pad at an end of the data line; a masking layer covering the data line, the source electrode and the drain electrode, and an oxidation-prevention layer covering the gate pad and the data pad.

Abstract: A first patterned contact layer, for example a gate electrode, is formed over an insulative substrate. Insulating and functional layers are formed at least over the first patterned contact layer. A second patterned contact layer, for example source/drain electrodes, is formed over the functional layer. Insulative material is then selectively deposited over at least a portion of the second patterned contact layer to form first and second wall structures such that at least a portion of the second patterned contact layer is exposed, the first and second wall structures defining a well therebetween. Electrically conductive or semiconductive material is deposited within the well, for example by jet-printing, such that the first and second wall structures confine the conductive or semiconductive material and prevent spreading and electrical shorting to adjacent devices. The conductive or semiconductive material is in electrical contact with the exposed portion of the second patterned contact layer to form, e.g.

Abstract: In a manufacturing method of a SOI type high withstand voltage semiconductor device formed on a support substrate via an insulation film, a small-sized semiconductor device having small dispersion of withstand voltage is manufactured by introducing impurities into the whole surface of a p-type or n-type SOI substrate having an impurity concentration of 2E14 cm?3 or less and serving as an active layer of the semiconductor device with an ion implantation method and thereby forming a drift layer.

Abstract: The present invention provides a manufacturing process using a droplet-discharging method that is suitable for manufacturing a large substrate in mass production. A photosensitive material solution of a conductive film is selectively discharged by a droplet-discharging method, selectively exposed to laser light, and developed or etched, thereby allowing only the region exposed to laser light to be left and realizing a source wiring and a drain wiring having a more microscopic pattern than the pattern itself formed by discharging. One feature of the source wiring and the drain wiring is that the source wiring and the drain wiring cross an island-like semiconductor layer and overlap it.

Abstract: A thin film transistor substrate that has reduced production cost and defect rate is presented. The thin film transistor substrate includes a gate wiring line formed on an insulating substrate and including a gate electrode, a data wiring line formed on the gate wiring line and including a source electrode and a drain electrode, a passivation layer pattern formed on parts of the data wiring line other than the drain electrode and a pixel region, and a pixel electrode electrically connected to the drain electrode. The pixel electrode includes zinc oxide.

Abstract: In a first aspect, a first method of manufacturing a high-voltage transistor is provided. The first method includes the steps of (1) providing a substrate including a bulk silicon layer that is below an insulator layer that is below a silicon-on-insulator (SOI) layer; and (2) forming one or more portions of a transistor node including a diffusion region of the transistor in the SOI layer. A portion of the transistor node is adapted to reduce a voltage greater than about 5 V within the transistor to a voltage less than about 3 V. Numerous other aspects are provided.

Abstract: A thin film transistor includes a gate electrode; an active layer formed of an oxide and insulated from the gate electrode; and a source electrode and a drain electrode formed of an oxide on the active layer such that the source electrode and the drain electrode are insulated from the gate electrode and electrically connected to the active layer, wherein the active layer, the source and the drain electrode are formed using an atomic layer deposition (ALD) and an insitu process, and a root mean square (RMS) value of the surface roughness of the active layer which contacts with the source and drain electrodes is less than 1 nm in order to reduce the contact resistance between the active layer and the source and drain electrodes, a method of manufacturing the same, an organic light emitting display apparatus including the thin film transistor, and a method of manufacturing the same.

Abstract: A method for manufacturing a liquid crystal display includes simultaneously forming a gate electrode and a gate bus line on a transparent dielectric substrate, simultaneously forming a channel layer, an ohmic contact layer, and source/drain electrodes by forming a gate insulation film, an amorphous silicon film, a doped amorphous silicon film, and a metal film on the transparent dielectric substrate on which the gate electrode and the gate bus line are formed and etching the metal film, the amorphous silicon film, and the doped amorphous silicon film, and forming a pixel electrode by forming a protective film and a transparent metal film on the transparent dielectric substrate upon which the source/drain electrodes are formed and finely etching the transparent metal film through a lift-off process using a stripper solution.

Abstract: A thin film transistor substrate having a semiconductor layer including a low concentration region and a source region/drain region adjacent to the low concentration region at both sides of a channel region made of polysilicon; a gate insulating layer and a conductive layer on the substrate the conductive layer patterned to form a gate electrode.

Abstract: A multi-channel type thin film transistor includes a gate electrode over a substrate extending along a first direction, a plurality of active layers parallel to and spaced apart from each other extending along a second direction crossing the first direction, and source and drain electrodes spaced apart from each other with respect to the gate electrode and extending along the first direction, wherein each of the plurality of active layers includes a channel region overlapped with the gate electrode, a source region, a drain region, and lightly doped drain (LDD) regions, one between the channel region and the source region and another one between the channel region and the drain region, wherein the LDD regions of the adjacent active layers have different lengths from each other.

Abstract: A method of manufacturing a silicon layer includes pretreating a surface of a silicon nitride layer formed on a substrate through a plasma enhanced chemical vapor deposition method using a first reaction gas including at least one of silicone tetrafluoride (SiF4) gas, a nitrogen trifluoride (NF3) gas, SiF4—H2 gas and a mixture thereof. Then, a silicon layer is formed on the pretreated silicon nitride layer through the plasma enhanced chemical vapor deposition method using a second reaction gas including a mixture of gas including silicon tetrafluoride (SiF4), hydrogen (H2) and argon (Ar).

Abstract: The present invention comprises a method of forming a zinc oxide based thin film transistor by blanket depositing the zinc oxide layer and the source-drain metal layer and then wet etching through the zinc oxide while etching through the source-drain electrode layer. Thereafter, the active channel is formed by dry etching the source-drain electrode layer without effectively etching the zinc oxide layer.

Abstract: A compound semiconductor material for forming an active layer of a thin film transistor device is disclosed, which has a group II-VI compound doped with a dopant ranging from 0.1 to 30 mol %, wherein the dopant is selected from a group consisting of alkaline-earth metals, group IIIA elements, group IVA elements, group VA elements, group VIA elements, and transitional metals. The method for forming an active layer of a thin film transistor device by using the compound semiconductor material of the present invention is disclosed therewith.