Abstract: Disclosed is a simplified method for manufacturing liquid crystal displays. A gate wire including a gate line, a gate pad, and a gate electrode is formed on the substrate. A gate insulating layer, a semiconductor layer, and an ohmic contact layer are sequentially deposited, and a photoresist layer is coated thereon. The photoresist layer is exposed to light through a mask and developed to form a photoresist pattern. At this time, the first portion of the photoresist pattern that is located between the source electrode and the drain electrode is thinner than the second portion that is located on the data wire, and the rest of the photoresist layer are wholly removed. The thin portion is made by controlling the exposure or by a reflow process to form a thin portion. And exposure is controlled by using a mask that has a slit, a small pattern smaller than the resolution of the exposure device, or a partially transparent layer.

Abstract: To provide a method of producing a TFT array and a liquid crystal display apparatus in which a contact resistivity of a pixel electrode and a drain electrode through a contact hole in an interlayer insulating film can be not more than 10E4&OHgr; stably.

Abstract: A MOSFET has a buried shield plate under the gate and over the drain with the gate being formed on the periphery of the buried shield plate as a self-aligned structure with minimal or no overlap of the gate over the shield plate. Methods of fabricating the MOSFET are disclosed.

Abstract: A method of forming a thin film transistor includes, a) forming a thin film transistor layer of semiconductive material; b) providing a gate operatively adjacent the thin film transistor layer; c) forming at least one electrically conductive sidewall spacer over at least one lateral edge of the gate, the spacer being electrically continuous therewith; and d) providing a source region, a drain region, a drain offset region, and a channel region in the thin film transistor layer; the drain offset region being positioned operatively adjacent the one electrically conductive sidewall spacer and being gated thereby. The spacer is formed by anisotropically etching a spacer forming layer.

Abstract: A TFT having stable characteristics is obtained by using a crystal silicon film obtained by crystallizing an amorphous silicon film by using nickel. Phosphorus ions are implanted to regions 111 and 112 by using a mask 109. Then, a heat treatment is performed to getter nickel existing in a region 113 to the regions 111 and 112. Then, the mask 109 is side-etched to obtain a pattern 115. Then, the regions 111 and 112 are removed by utilizing the pattern 115 and to pattern the region 113. Thus, a region 116 from which nickel element has been removed is obtained. The TFT is fabricated by using the region 116 as an active layer.

Abstract: A method of fabricating a thin film transistor having a vertical offset layer which prevents the damage on an active layer due to the etching plasma by preserving the vertical offset layer during an etching process for separating an ohmic contact layer.

Abstract: A thin film transistor includes a substrate, a gate electrode formed on the substrate, and including opposing edge portions and a middle portion. An insulating film is formed on the surface of the gate electrode having a greater thickness on one of the gate edge portions. An active region is formed on the surface of the insulating film and the exposed substrate. The active region includes an off-set region, a channel region, a source region, and a drain region.

Abstract: A method of manufacturing an LCD requires only 4 masking while preventing undercutting of a semiconductor layer and includes the steps of etching a passivation layer, an a-Si layer and a gate insulating layer simultaneously by using CF.sub.4 /He gas. The flow ratio of the He gas to CF.sub.4 gas is preferably about 15% to about 35%.

Abstract: A method of fabricating silicon TFTs (thin-film transistors) is disclosed. The method comprises a crystallization step by laser irradiation effected after the completion of the device structure. First, amorphous silicon TFTs are fabricated. In each of the TFTs, the channel formation region, the source and drain regions are exposed to laser radiation illuminated from above or below the substrate. Then, the laser radiation is illuminated to crystallize and activate the channel formation region, and source and drain regions. After the completion of the device structure, various electrical characteristics of the TFTs are controlled. Also, the amorphous TFTs can be changed into polysilicon TFTs.

Abstract: In a method for manufacturing an LCD device where a gate insulating layer is formed on an insulating substrate and a signal line pattern layer and a pixel electrode pattern layer are formed on a signal line forming area and a pixel electrode forming area, respectively, of the gate insulating layer, a part of the gate insulating layer between the signal line forming area and the pixel electrode forming area is etched.

Abstract: A dual level transistor integrated circuit and a fabrication technique for making the integrated circuit. The dual level transistor is an integrated circuit in which a first transistor is formed on an upper surface of a global dielectric and a second transistor is formed on an upper surface of a first local substrate such that the second transistor is vertically displaced from the first transistor. The first local substrate is formed upon a first inter-substrate dielectric. By vertically displacing the first and second transistors, the lateral separation required to isolate first and second transistors in a typical single plane process is eliminated. The integrated circuit includes a semiconductor global substrate. The integrated circuit further includes a first transistor. The first transistor includes a first gate dielectric formed on an upper surface of the global substrate and a first conductive gate structure formed on an upper surface of the first dielectric.

Abstract: A thin semiconductor film device according to the present invention includes an insulative substrate, a metal layer formed on the insulative substrate, and a metal oxide layer formed on the metal layer. The metal oxide layer is obtained from anodization of the metal layer. In a preferred embodiment, an insulation film of silicon oxide or silicon nitride is formed on the metal oxide layer, and a semiconductor layer obtained by crystallizing the amorphous silicon layer is formed on the insulation film.

Abstract: During the formation of a self-aligned thin film transistor (50), the semiconductor material channel layer (58) on the gate insulating layer (56) has a passivation shield (P.sub.S) applied to it aligned with the gate electrode (54). The channel layer is then exposed to a reagent selected to yield a chemical reaction with the portions of the channel layer (58) not covered by the passivation shield (P.sub.S) causing removal of a component of the semiconductor material thereby to change the electrical properties of those portions of the channel layer. In this manner, doped source and drain regions (60, 62) can be formed on opposite sides of the channel having edges that extend to the edges of the gate electrode avoiding any overlap therebetween and reducing the parasitic capacitance of the thin film transistor (50).

Abstract: In production of a thin film transistor, a gate electrode is formed on an insulating substrate. A gate nitride film and a gate oxide film are formed on the gate electrode. A semiconductor thin film is formed on the gate oxide film. The semiconductor thin film is irradiated with laser light for crystallization. The growth of the crystal grains in a first section of the semiconductor thin film lying just above the gate electrode is more significant than that of the crystal grains in a second section of the semiconductor thin film lying in a position other than just above the gate electrode. An impurity is selectively doped into the second section of the semiconductor thin film to form a source region and a drain region, while the first section of the semiconductor thin film is left without modification as a channel-forming region.

Abstract: The present invention includes forming a conductive layer on a substrate. Portions of the conductive layer are removed using a first photoresist layer as a mask. A first oxide layer is formed over the conductive layer and the substrate, and an amorphous silicon layer is then formed on the first oxide layer. After annealing the amorphous silicon layer, thereby transforming amorphous silicon layer to a polysilicon layer, a second oxide layer is formed on the polysilicon layer. The second oxide layer is removed using a second photoresist layer as a mask. An amorphous silicon carbon layer is formed over the second oxide layer and the polysilicon layer, and a heavily-doped amorphous silicon carbon layer is formed on the amorphous silicon carbon layer.

Abstract: The semiconductor device of this invention includes a substrate having an insulating surface and a thin film transistor formed on the substrate, wherein the thin film transistor has a semiconductor island including a channel region and source/drain regions, a gate insulating film formed on the semiconductor island and a gate electrode covering the channel region of the semiconductor island interposing the gate insulating film therebetween, and wherein a distance between an edge of the channel region of the semiconductor island and the gate electrode is larger than a distance between a central portion of the channel region of the semiconductor island and the gate electrode.

Abstract: There is provided a semiconductor device in which a semiconductor layer and a gate electrode are formed with a gate insulating layer between then and in which a region of the semiconductor layer opposite to the gate electrode is used as a channel region. On the semiconductor layer, an insulating protection film and an amorphous semiconductor layer are successively formed. The protection film covers at least the channel region of the amorphous semiconductor layer, and annealing is applied to the amorphous semiconductor layer, thereby converting the amorphous semiconductor layer into the polycrystal semiconductor layer. A portion to be the channel region of the amorphous semiconductor layer is covered by the protection film. Therefore, even when exposed to the atmosphere due to annealing, surface contamination can be prevented and a semiconductor device having satisfactory characteristics can be obtained. A thickness d of the protection film is set to be nearly ".lambda./4n" for a wavelength .lambda.

Abstract: A dual-gate SOI transistor has self-aligned upper and lower gates, in which a gate trench that will hold the dual-gate structure is formed by damaging the oxide under the transistor active area and preferentially etching that damaged region with HF, thus producing a self-aligned opening that has less overlap of the lower gate and the source/drain junctions and is filled with LPCVD polysilicon to form a dual-gate structure having reduced capacitance compared with prior art devices.

Abstract: The present invention is related to a self-aligned manufacturing method of a thin film transistor for forming a single-crystal bottom-gate and an offset drain. The main object of the present invention is to disclose two manufacturing methods to attain the self-aligned manufacturing method of a thin film transistor for forming a single-crystal bottom-gate and an offset drain. In the first method, a photoresistor and a silicon nitride are used to form a dual stack as a mask, further a large-angle ion implant is used to form a thin film transistor with a single-crystal bottom-gate and an offset drain. In the second method, the source side is protected by a dual stack formed by a P+ polysilicon layer which may be discarded selectively and a silicon nitride and an insulation spacer of sidewall in order to selectively discard the silicon nitride on the drain side, thus the object of a thin film transistor with a single-crystal bottom-gate and an offset drain is obtained.

Abstract: Plasma treatment is performed on an exposed portion of an undoped amorphous silicon layer in a thin film transistor, after etching source/drain contacts and a doped amorphous silicon layer. The plasma treatment can repair damage caused during the etching. The plasma treatment is preferably a hydrogen plasma treatment, and more preferably a helium plasma treatment. These treatments are particularly useful in repairing damage when the source/drain electrodes comprise molybdenum or molybdenum/tungsten alloy, and etching is performed by dry etching the doped amorphous silicon layer using CF.sub.4 and HCl gases.

Abstract: A thin film transistor structure for use in driving liquid crystal display elements has a semiconductor active layer, a control electrode layer underlying the active layer with an insulating layer interposed therebetween and first and second main electrode layers formed on or above the active layer in a spaced relation with each other to define a channel in the active layer in cooperation with the control electrode layer between the main electrode layers. The active layer has a first peripheral edge portion generally perpendicular to the direction of the channel and a second peripheral edge portion generally not perpendicular to the direction of the channel. The first and/or second main electrode layer extends over the first and/or second peripheral edge portion of the active layer such that at least a part of the first peripheral edge portion and/or at least part of the second peripheral edge portion of the active layer has its side face directly covered with the main electrode layer.

Abstract: There is provided a method of fabricating a thin film transistor array having a transparent insulating substrate, a plurality of thin film transistors formed on the substrate in a matrix, a gate bus line connected to gate electrodes of the thin film transistors, a drain bus line connected to drain electrodes of the thin film transistors, and a pixel electrode driven by the thin film transistors, the method including the steps of forming the gate electrode and the gate bus line on the transparent insulating substrate, forming a gate insulating film over the substrate, forming an operative semiconductor on the gate insulating film, forming the source electrodes, drain electrodes, and drain bus line of the thin film transistors on the gate insulating film and the operative semiconductor, forming a protection film all over the substrate, removing a portion of both the gate insulating film and the protection film, located above a terminal of the gate bus line, and also removing a portion of the protection film loc

Abstract: The present invention relates to a method for manufacturing TFTs in which a gate electrode is first formed on a transparent glass substrate by depositing and patterning a first metal layer. Next, a first insulating layer, a semiconductor layer, impurity-containing semiconductor layer and a second insulating layer are deposited over the first metal layer and the substrate surface. The insulating layer is patterned followed by deposition of a second metal layer. First portions of the second metal layer and the impurity-containing semiconductor layer along with part of the second insulating layer are etched over the gate electrode (thereby forming source and drain electrodes) at the same time second portions of the second metal layer and impurity-containing semiconductor layer and portions of the semiconductor layer laterally spaced from the gate electrode are etched. As a result, the number of etching steps is reduced, and the second insulating layer controls the etching speed.

Abstract: A field effect transistor and method for making the same is described wherein the field effect transistor incorporates a T-shaped gate and source and drain contacts self-aligned with preexisting shallow junction regions. The present invention provides a low resistance gate electrode and self-aligned low resistance source/drain contacts suitable for submicron FET devices, and scalable to smaller device dimensions.

Abstract: A method of forming film transistor includes, a) forming a thin film transistor layer of semiconductive material; b) providing a gate operatively adjacent the thin film transistor layer; c) forming at least one electrically conductive sidewall spacer over at least one lateral edge of the gate, the spacer being electrically continuous therewith; and d) providing a source region, a drain region, a drain offset region, and a channel region in the thin film transistor layer; the drain offset region being positioned operatively adjacent the one electrically conductive sidewall spacer and being gated thereby. The spacer is formed by anisotropically etching a spacer forming layer.

Abstract: In a method for manufacturing a liquid crystal display apparatus, a gate electrode is formed on an insulating substrate, and a gate insulating layer is formed on the gate electrode. Then, a semiconductor active layer is formed on the gate insulating layer. Then, a metal silicide layer is formed on the semiconductor active layer by using a sputtering process, and a metal layer is formed on the metal silicide layer. Then, the metal layer is etched by a dry etching process using a mask, an the metal silicide layer is etched by a wet etching process using the same mask. Finally, the semiconductor active layer is etched by using the metal layer as a mask.

Abstract: The present invention discloses a hybrid polysilicon/amorphous silicon TFT device for switching a LCD and a method for fabrication wherein a n.sup.+ doped amorphous silicon layer is advantageously used as a mask during a laser annealing process such that only a selected portion of a hydrogenated amorphous silicon layer is converted to a crystalline structure while other portions retain their amorphous structure. As a result, a polysilicon TFT and at least one amorphous silicon TFT are formed in the same structure and the benefits of both a polysilicon TFT and amorphous silicon TFT such as a high charge current and a low leakage current are retained in the hybrid structure.

Abstract: A MOS transistor including a gate electrode on a gate oxide over a channel region between a source region and a drain region also includes a shield electrode at least partially on the gate oxide adjacent to, self-aligned with, and at least partially coplanar with the gate electrode and between the gate electrode and drain region. Placing the shield electrode on the gate oxide improves the gate-drain shielding, reduces the gate-drain capacitance, Cgd, and reduces hot electron related reliability hazard.

Abstract: A TFT structure includes a variably doped contact layer system in order to reduce leakage current characteristics and increase mobility of the TFT. Such TFTs may be utilized in, for example, X-ray imagers or liquid crystal displays. In certain embodiments, the contact layer system is lightly doped adjacent a semiconductor or channel layer, and is more heavily doped adjacent the source/drain electrodes. The variation in doping density of the contact layer system may be performed in a step-like manner, gradually, continuously, or in any other suitable manner. In certain embodiments, the contact layer system may include a single layer which is deposited over an intrinsic semiconductor layer, with the amount of dopant gas being used during the deposition process being adjusted through the deposition of the single layer so as to cause the doping density to vary (increase or decrease) throughout the thickness of the system/layer.

Abstract: Disclosed is a thin film transistor formed on a substrate, comprising a patterned gate electrode formed on said substrate; a channel layer formed around said gate electrode with a gate insulating layer interposed therebetween; a interlayer insulating layer formed on said channel layer; and source and drain electrodes formed on both side walls of said channel layer and on both side portions of said interlayer insulating layer, and isolated from each other. Each of the channel and source/drain layers is composed of polysilicon with impurity ions. In the thin film transistor, because each of the source and drain electrodes is formed relatively thicker than the channel layer, them can be significantly reduced in resistance.

Abstract: A thin film transistor includes a substrate, a gate electrode formed on the substrate, and including opposing edge portions and a middle portion. An insulating film is formed on the surface of the gate electrode having a greater thickness on one of the gate edge portions. An active region is formed on the surface of the insulating film and the exposed substrate. The active region includes an off-set region, a channel region, a source region, and a drain region.

Abstract: The thin film transistor is fabricated by etching a semiconductor layer, n.sup.+ semiconductor layer, etch stopper layer, and metal layer with single etching process to decrease the number of masks. By controlling the thickness of the semiconductor layer or the etching selection ratio of the etch stopper layer, an etch stopper thin film transistor or back channel etched thin film transistor can be fabricated.

Abstract: In a method for manufacturing an LCD device where a gate insulating layer is formed on an insulating substrate and a signal line pattern layer and a pixel electrode pattern layer are formed on a signal line forming area and a pixel electrode forming area, respectively, of the gate insulating layer, a part of the gate insulating layer between the signal line forming area and the pixel electrode forming area is etched.

Abstract: A thin film transistor includes a substrate with a trench having first and second sides and a bottom, and a gate electrode at one of the first and second sides of the trench. The thin film transistor further includes a gate insulating layer on the entire surface of the substrate including the gate electrode, and an active layer on the gate insulating layer along the trench, the active layer having source and drain regions substantially outside the trench.

Abstract: In an active matrix substrate of a liquid crystal display using a TFT as a switching device for each pixel, a gate bus line and a drain bus line extending perpendicular to each other are formed simultaneously by patterning a metal film, and one of the two bus lines is broken to provide a gap across which the other extends. The gap is covered by an island structure of a gate dielectric film and a semiconductor layer formed to provide the TFT, and a supplementary bus line makes direct contact with the broken bus line on both sides of the gap to provide a bridge over the gap. The supplementary bus line is formed together with a pixel electrode by patterning a transparent conductor film. By this arrangement of bus lines, the total number of photolithography steps in the production process is decreased so that the production cost can be reduced.

Abstract: A thin-film transistor including a gate electrode provided on a substrate, a gate insulation film provided on the gate electrode, an operative semiconductor film provided on the gate insulation film, and a channel protection film provided on the operative semiconductor film. Semiconductor contact portions are disposed so that they are covered by the channel protection film on either side of the operative semiconductor film. A source electrode and a drain electrode are connected to the semiconductor contact portions on either side of the channel protection film. The thin-film transistor can minimize the stray capacitance due to the overlapping of the source and drain electrodes with the gate electrode and is excellent in the contact characteristic. Also, a method for fabricating a thin-film transistor is disclosed.

Abstract: A process for manufacturing a thin film transistor for use in a CMOS SRAM circuit is described. A key feature is the formation of two different photoresist masks from the same optical mask. The first photoresist mask is generated using a normal amount of actinic radiation during exposure and is used to protect the gate region during source and drain formation through ion implantation. The second photoresist mask is aligned relative to the gate in exactly the same orientation as the first mask but is given a reduced exposure of actinic radiation. This results, after development, in a slightly larger mask which is used during etching to form the oxide cap that will protect the channel area during the subsequent silicidation step. Making the cap slightly wider than the channel ensures that small lengths of the source and the drain regions that abut the channel are not converted to silicide. Thus, the finished device continues to act as a thin film transistor, but has greatly reduced source and drain resistances.

Abstract: A method of manufacturing a thin film transistor comprising the steps of: forming a gate electrode on the surface of a substrate; forming a gate insulation film covering the gate electrode; forming an active semiconductor layer and an ohmic contact layer on the gate insulation film; forming a source/drain electrode made of Cr; and removing a portion of the ohmic contact layer except for the portion in contact with the source/drain electrode by an etching solution, wherein the step of removing the ohmic contact layer is conducted in a state of at least partially or entirely peeling a resist on the source/drain electrode made of Cr.

Abstract: A thin film transistor includes a first active layer formed on a substrate; a gate electrode formed on a center portion of the first active layer and having a lower side connected to the center portion of the first active layer; a second active layer electrically connected to the first active layer and formed on lateral sides and on an upper side of the gate electrode; and impurity regions formed at opposing lateral sides of the gate electrode.

Abstract: The present invention includes forming a conductive layer on a substrate. Portions of the conductive layer are removed using a first photoresist layer as a mask. A first oxide layer is formed over the conductive layer and the substrate, and an amorphous silicon layer is then formed on the first oxide layer. After annealing the amorphous silicon layer, thereby transforming amorphous silicon layer to a polysilicon layer, a second oxide layer is formed on the polysilicon layer. The second oxide layer is removed using a second photoresist layer as a mask. An amorphous silicon carbon layer is formed over the second oxide layer and the polysilicon layer, and a heavily-doped amorphous silicon carbon layer is formed on the amorphous silicon carbon layer.

Abstract: A method for fabricating a thin film transistor, comprising the steps of: forming a gate electrode; forming a doped polysilicon film for source/drain at the side wall of the gate electrode, to insulate the gate electrode; forming a gate insulating film; forming an amorphous polysilicon film over the resulting structure; and forming a source/drain region by diffusing the dopants of the doped polysilicon film into the amorphous silicon film, whereby it is possible to form the source/drain region and drain offset structure of a thin film transistor without formation of a source/drain mask and ion implantation and thus, thereby simplifying the overall procedure.

Abstract: A lightly doped drain thin-film transistor having an inverted staggered structure. The transistor has a glass substrate and a gate formed by a Cr layer on the substrate. An insulating layer and a semiconductor layer are deposited on the substrate and the gate. A first photo-resist layer is coated on top of the semiconductor layer. Back-side exposure and self-aligned technique are used to form an unexposed area slightly smaller than the gate area with high energy light. Low energy ion implantation is then performed on the exposed semiconductor layer to produce the lightly doped region. After removing the first photo-resist layer, another photo-resist process including a second photo-resist coating, back-side exposure and self-aligned technique is performed to form an unexposed area slightly larger than the gate area with low energy light. High energy ion implantation is then performed on the exposed semiconductor layer.

Abstract: A thin film transistor and a fabricating method for a thin film transistor is disclosed which may be suitable for memory cells of a static random access memory (SRAM) or other devices. A thin film transistor according to this invention may include an insulation substrate, a gate electrode formed to have a negative slope at one side thereof on the insulation substrate, an insulation film side wall formed at the other side of the gate electrode, a gate insulation film formed on the insulation substrate, gate electrode and side wall, a semiconductor layer formed on the gate insulation film, impurity diffusion regions selectively formed within the semiconductor layer over the gate electrode, the side wall and the insulation substrate on the other side of the gate electrode, and a channel region formed within the semiconductor layer at the side of the gate electrode having the negative slope.

Abstract: A method for fabricating Thin Film Transistors includes the steps of forming a gate electrode on a substrate, forming a gate insulation film and a semiconductor layer successively on the substrate, forming a sidewall spacer only at one sidewall of the gate electrode on the semiconductor layer, and forming impurity regions in the semiconductor layer on both sidewalls of the gate electrode by ion-injecting impurity ions into the semiconductor layer.

Abstract: Improved thin film transistors to reduce defects in the devices incorporating the transistors, including active matrix displays. A first improvement is accomplished by forming a dual insulator layer over the bottom metal layer, which can be the gate line and also the row line in an active matrix display. The first insulator layer is formed by anodizing the metal layer and the second insulator layer is deposited onto the first layer. The dual insulator structure layer can be reanodized to eliminate the effect of pinholes. A second improvement includes providing an interdigitated transistor structure to increase the channel width, minimize internal shorting and minimize the drain capacitance. The interdigitated structure includes at least one source or drain finger formed between at least two drain or source fingers, respectively. A shorted source finger can be disconnected to maintain an operative transistor.

Abstract: An additional high quality insulating layer is grown over the substrate after the formation of the gate electrode of a thin film transistor (TFT). The growth temperature of the insulating layer can be higher than conventional method and the insulating layer is more free of pin-holes. After the insulating layer in the thin oxide region of the TFT is etched away, conventional fabrication processes are followed. The dielectric of the thin film oxide region is the same as that of the conventional TFT; but the dielectric in the vincinity of the thin oxide region, the crossovers of the data lines and the scan lines, and the gate dielectric layer of the TFT are now composed of the high quality insulating layer. The TFT structure can improve the yield of fabrication by confining the channel region in the shadow of the gate electrode to reduce the leakage photo-current, and by reducing the steps at cross-overs steps and interconnections to avoid open-circuit.

Abstract: A semiconductor device comprises a semiconductor substrate of a first conductivity type with a first insulating layer formed on the semiconductor substrate and a thin film field effect transistor with a control gate containing a refractory metal silicide formed on the semiconductor substrate over the first insulating layer. A second insulating layer covers the control gate electrode. A semiconductor film is formed on the semiconductor substrate over the first and second insulating layers and having a first region of a second conductivity type opposite to the first conductivity type. A second region of the first conductivity type is formed in contact with a first end of the first region. A third region of the first conductivity type is formed in contact with a second end of the first region. The control gate electrode and a part of the first region are overlapped with each other over the second insulating layer.

Abstract: A liquid crystal display including an array of thin film transistors. Each thin film device in the array includes gate, source and drain electrodes. At least one of the source and drain electrodes include first and second metal layers offset with respect to one another so as to reduce the channel length of the transistors. Because of the reduced TFT channel length, the TFT channel width can also be reduced while maintaining the same ON current. Thus, the gate-source capacitance is reduced which in turn reduces pixel flickering and image retention and improves gray level uniformity. The first and second source-drain metal layers are of different materials so that the etchant for the second metal does not etch the first metal layer deposited. The TFT may be either a linear TFT or a ring-shaped TFT according to different embodiments of this invention.