Abstract: A passivation structure for a semiconductor device includes a high ultraviolet transmittance silicon nitride (UV-SiN) layer. This UV-SiN layer substantially conformally overlies a plurality of top metal lines, which are formed over a semiconductor substrate, such that topographical hollows are defined between adjacent top metal lines. A spin-on glass (SOG) material fills in the topographical hollows. A silicon oxynitride (SiON) layer having a thickness in a range from about 8,000 angstroms to about 10,000 angstroms overlies the UV-SiN layer and the SOG material. A method for forming the passivation structure also is described.

Abstract: A thin film transistor and a fabricating method thereof are adaptive for increasing a capacitance of a storage capacitor. In the method, a gate electrode and a lower electrode of a capacitor are formed at the transistor area and the capacitor area of an insulating substrate, respectively. A gate insulating film, an active layer and an ohmic contact layer on the insulating substrate is sequentially formed to cover the gate electrode and the lower electrode. The ohmic contact layer and the active layer are primarily patterned in such a manner as to be left only at a portion corresponding to the gate electrode of the transistor area and thus expose the gate insulating film. Then, the ohmic contact layer and the active layer are secondarily patterned in such a manner as to reduce the thickness of the gate insulating film at a portion corresponding to the lower electrode.

Abstract: A pixel portion 100 of a liquid crystal display de ice comprises a thin film transistor T comprising a gate electrode 13, a gate insulating film 16, a channel region 18, and source/drain regions 22, a source line (data) 26 for supplying current to the thin film transistor T and a pixel electrode 24. In the formation of a pixel circuit 100, a gate electrode 13, a gate insulating film 16, and the channel region 18 are firstly formed on a glass substrate 10. After the formation of the channel region 18 and the like, a polyimide film 20 surrounding the peripheries of the regions to be provide with the source/drain regions 22, the pixel electrode 24 and the source line 26 on a glass substrate 10 is formed. The regions surrounded with the wall of the polyimide film 20 are applied with a liquid material and subjected to a thermal treatment, thereby forming the element of the source/drain regions 22 and the like.

Abstract: There is provided a patterning method which makes it possible to form a desired preferable pattern having no reduction in the pattern thickness in a boundary portion where a group of patterns are joined using a plurality of exposure masks. There is provided a patterning method for forming a group of patterns in which first patterns to serve as basic units are repetitively arranged using a plurality of exposure masks. When a third region sandwiched by a first region exposed with a first exposure mask and a second region exposed with a second exposure mask is exposed with the first and second exposure masks in a complementary manner, repetitive unit patterns for exposing the third region are different from the first patterns.

Abstract: There is provided an active matrix type semiconductor display device which realizes low power consumption and high reliability. In the active matrix type semiconductor display device of the present invention, a counter electrode is divided into two, different potentials are applied to the two counter electrodes, respectively and inversion driving is carried out each other. Since a potential of an image signal can be made low by doing so, it is possible to lower a voltage necessary for operation of a driver circuit. As a result, it is possible to realize improvement of reliability of an element such as a TFT and reduction of consumed electric power. Moreover, since it is possible to lower a voltage of a timing pulse supplied by the driver circuit, a booster circuit can be omitted, and reduction of an area of the driver circuit can be realized.

Abstract: A method of fabricating an electronic device comprising a thin-film transistor, which addresses a problem of increased off-state current and reduced carrier mobility in self-aligned thin-film transistors. According to the method, a gate layer (2,46) is etched back underneath a mask layer (20,48). Following an implantation step using the mask layer as an implantation mask, the etch-back exposes implant damage which is then annealed by an energy beam (42).

Abstract: An active matrix type display device having a sufficient auxiliary capacitance and a high aperture ratio is provided. In the device, an auxiliary capacitance (a black mask being in contact with an inorganic layer/the inorganic layer/a pixel electrode being in contact with the inorganic layer) is formed on an interlayer insulating film made of an organic resin film.

Abstract: In a monolithic active matrix circuit that uses offset-gate TFTs in which the gate electrode is offset from the source and drain regions or TFTs whose gate insulating film is formed by vapor deposition, not only an active matrix circuit but also a drive circuit therefor is formed by using P-channel TFTs.

Abstract: [Problem] A liquid crystal display device in the prior art has been high in its manufactural cost for the reason that TFTs have been fabricated using, at least, five photo-masks.

Abstract: A method for manufacturing an x-ray detector comprises the steps of: preparing an insulating substrate; forming a gate and a pad on the insulating substrate; forming a gate insulating film, an amorphous silicon layer and an etch stopper over the insulating substrate, inclusive of the gate and the pad; simultaneously forming a channel layer, an ohmic contact layer and a source/drain over the gate insulating film, inclusive of the etch stopper, and a common electrode over a proper portion of the gate insulating film; forming a first storage electrode over the gate insulating film, inclusive of the common electrode; forming a protective layer over the entire structure of the insulating substrate on which the source/drain and the first storage electrode have been formed, and subsequently forming a contact hole and via holes over a proper portion of the protective layer; and forming a second storage electrode over the protective layer.

Abstract: To provide a manufacturing method for a field-effect transistor, such as a thin-film transistor, enabling reductions in the number patterning steps and the number of photomasks and improvements in the throughput and the yield. In the method, an oxide film is formed by processing the surface of a crystalline semiconductor with ozone water or hydrogen peroxide water. Using the oxide film thus formed as an etch stop, a gate electrode, a source electrode, and a drain electrode of the field-effect transistor are simultaneously formed from a same starting film in one patterning step by use of one photomask. After forming the gate electrode, the source electrode, and the drain electrode, heating is performed thereon at 800° C. or higher for a predetermined time. Thereby, the contact resistances between the source electrode and the crystalline semiconductor and between the drain electrode and the crystalline semiconductor are reduced, whereby improving the electrical conductivity.

Abstract: Disclosed is a method for manufacturing a thin film transistor of a semiconductor device, wherein an offset area is influenced by a gate voltage to increase the ON-current, which provides a thin film transistor which improves the ON/OFF characteristic of the semiconductor device. The low swing value and the high ON/OFF ratio are implemented by forming a gate insulation layer of ONO structure on the gate electrode on the semiconductor device and then performing a steam anneal process using a wet-oxidizing method to reinforce the surface the respective ONO layer. Thus, the thickness of a gate insulation layer is reduced, the margin of the device is secured, and the electrical characteristic becomes superior.

Abstract: There is provided a structure of a pixel TFT (n-channel type TFT) in which an off current value is sufficiently low. In impurity regions, a concentration distribution of an impurity element imparting one conductivity type is made to have a concentration gradient, the concentration is made low at a side of a channel formation region, and the concentration is made high at the side of an end portion of a semiconductor layer.

Abstract: A non-volatile semiconductor memory device includes an interlayer dielectric film 9, 19 flattened by etching back an SOG film. In the non-volatile semiconductor memory device, a barrier film of a silicon nitride film 9D and 19D is formed to cover at least a memory cell composed of a floating gate 4, a control gate 6, etc. Because of such a structure, even if H or OH contained in the SOG is diffused, it will not be trapped by a tunneling film 3. This improves a “trap-up rate”. The barrier film may be formed in only an area covering the memory cell. This reduces its contact area with a tungsten silicide film, thereby suppressing film peeling-off. Thus, the operation life of the memory cell in the non-volatile semiconductor memory device can be improved.

Abstract: An improved method and system for laser doping a semiconductor material is described. In the invention, phosphorous nitride is used as a dopant source. The phosphorous nitride is brought into close proximity with a region of the semiconductor to be doped. A pulse of laser light decomposes the phosphorous nitride and briefly melts the region of semiconductor to be doped to allow incorporation of dopant atoms from the phosphorous nitride into the semiconductor.

Abstract: A conductive film made of Al or alloy containing Al as a main component is formed on an underlying substrate. An upper conductive film is disposed on the conductive film. A first opening is formed through the upper conductive film. An insulating film is disposed on the upper conductive film. A second opening is formed through the insulating film. An inner wall of the second opening is retreated from an inner wall of the first opening. An ITO film is formed covering a partial upper surface of the insulating film and inner surfaces of the first and second openings, and contacting a partial upper surface of the upper conductive film at a region inside of the second opening. Good electrical contact between an Al or Al alloy film and an ITO film can be established and productivity can be improved.

Abstract: A catalyst element for accelerating crystallization is added to an amorphous silicon film containing an impurity element for threshold voltage control, and a heat treatment is then performed to obtain a crystalline silicon film. Thereafter, the catalyst element is gettered by performing a heat treatment in an atmosphere containing a halogen element. In this step, a chemical equilibrium state is established for the impurity element for threshold voltage control by mixing a compound gas containing the impurity element into the atmosphere, thereby preventing the impurity element from escaping into the vapor phase.

Abstract: A process for manufacturing a thin film transistor liquid crystal display (TFT-LCD) is disclosed. The process can reduce the number of the mask used in the photolithography process to three masks, form a capacitor during the manufacturing process simultaneously, and enhance the transmission rate of the TFT-LCD. Because the pixel electrodes are formed directly on the substrate, without forming an insulator layer in the pixel area, the transmission can be enhanced. The manufacturing process also provides a protective circuit for avoiding electrostatic discharge damage, and a passivation layer to protect the capacitor, the gate line, and the signal line.

Abstract: A thin film transistor is disclosed, including an insulating substrate, a semiconductor layer formed on the insulating substrate, the semiconductor layer having an active region and an impurity region, a gate insulating layer formed on the active region of the semiconductor layer, a first gate metal layer formed on a predetermined portion of the active region of the semiconductor layer to define a channel region, and a second gate metal layer formed on the first gate metal layer. The first and second gate metal layers have different compositions, such that the second gate metal layer etches faster than the first gate metal layer, thereby preventing formation of a hillock. A first protective layer is formed over the structure, then a light shielding layer, and then a second protective layer is formed over the light shielding layer.

Abstract: A pixel cell has a thin film transistor structure formed on a substrate. A signal conductor is patterned on the thin film transistor structure, and a first patterned layer of a transparent conductive material covers the signal conductor. The first patterned layer provides a pattern employed in etching a channel region of the thin film transistor structure. A dielectric layer is formed over the pixel cell and includes a via hole down to the first patterned layer of the transparent conductive material. A second layer of transparent conductive material extends through the via hole to contact the first patterned layer wherein the second layer is self-aligned to the transistor structure.

Abstract: An object of the present invention is to provide a fabrication method of a liquid crystal display which can reduce the number of masks used in a photolithography process. According to this structure, a gate bus line and a storage capacitor wiring are formed using a first mask, and first metal films are formed on the whole surface including a sidewall insulating film. Then, etching is performed using a second mask until an active semiconductor layer in a TFT forming area on the gate bus line and in an element separation area between pixels exposes. Along with an electroplating of a metal film on the first metal films on a drain electrode, a third metal film thinner than the second metal film is formed on an active semiconductor between the drain electrode and a source electrode and to a pixel electrode except the element separation area between pixels.

Abstract: A gate electrode is formed on the substrate, and a gate insulating layer is formed over the gate electrode. An amorphous silicon layer and a doped amorphous silicon layer is formed in sequence. On the doped amorphous silicon layer, a source and a drain electrode made of molybdenum or molybdenum-tungsten alloy is formed and the doped amorphous silicon layer is dry etched. When the doped amorphous silicon layer is dry etched, the source/drain electrodes or the photoresist pattern used to form the source/drain electrodes is used as a mask, and a HCl+CF4 gas system is used for dry etching gas. After dry etching the doped amorphous silicon layer, in-situ He plasma treatment is performed. If HCl+CF4+O2 dry etching gas is used to etch the doped amorphous silicon layer, the characteristics of TFT may be improved with one dry etch process without the additional plasma treatment.

Abstract: A method for re-forming a semiconductor layer of a thin film transistor-liquid crystal display device, including the steps of forming a gate electrode on a substrate, and forming a first gate insulation film on the gate electrode and the substrate; forming a semiconductor layer on the first gate insulation film; etching the semiconductor layer to remove the semiconductor layer if the formed semiconductor layer is defective; etching an upper portion of the first gate insulation film to a certain thickness damaged as the interface is exposed to the air by the etching of the semiconductor layer; forming a second gate insulation film on the remaining first gate insulation film; and forming a semiconductor layer on the second gate insulation film.

Abstract: A crystal growth 301 is carried out by diffusing a metal element, and a nickel element is moved into regions 108 and 109 which has been doped with phosphorus. An axis coincident with the moving directions 302 and 303 of the nickel element at this time is made to coincide with an axis coincident with the direction of the crystal growth, and a TFT having the regions as channel forming regions is manufactured. In the path of the region where nickel moved, since high crystallinity is obtained in the moving direction, the TFT having high characteristics can be obtained by this way.

Abstract: It is intended to provide a method of forming a gate overlap lightly doped impurity region (GOLD). After a gate insulating film is formed by a material mainly made of silicon oxide and a gate electrode is formed with, for instance, silicon, lightly doped impurity regions are formed. A coating mainly made of silicon is formed on the entire surface including the surface of the gate electrode. Side walls mainly made of silicon are formed on the side faces of the gate electrode by anisotropically or semi-anisotropically etching the thus-formed coating in an atmosphere of ClF3, for instance. In this etching step, since a selective etching ratio of the side walls to the gate insulating film is sufficiently large, etching of the gate insulating film is negligible. A source and a drain are then formed by doping an impurity at a high concentration using the gate electrode and the side walls as a mask.

Abstract: In a semiconductor device of this invention, a pillar projection serving as a very thin active region is formed on the surface of a p-type silicon semiconductor substrate. A gate electrode 21 is formed to cover a central portion of the pillar projection. A pair of impurity diffusion layers 22 are formed on the pillar projection on the two sides of the gate electrode. An element isolation insulating film 23 is formed to sandwich and bury the side surfaces of the pillar projection. This semiconductor device has high performance equivalent to that of an SOI structure. The semiconductor device of this invention has three channels corresponding to a pair of a source and a drain, is selectively formed on the same semiconductor substrate as a common bulk transistor, and has a very fine structure and high drivability.

Abstract: Methods and apparatus are provided for creating field effect transistor (FET) body connections with high-quality matching characteristics and no area penalty for partially depleted silicon-on-insulator (SOI) circuits. The FET body connections are created for partially depleted silicon-on-insulator (SOI) technologies by forming adjacent FET devices inside a shallow trench shape. The adjacent FET devices share a common diffusion area, such as source or drain. Selectively spacing apart adjacent gate lines form an underpath connecting bodies of the adjacent FET devices. The underpath is defined by forming an undepleted region on top of a buried oxide layer. The adjacent polysilicon gate lines are selectively spaced apart to define a depth of depletion in a shared diffusion region for creating the underpath. Also, adjacent FET devices with connecting bodies can be built by adding an ion implant masking step to the fabrication process. This masking step changes the depletion depth under the shared diffusion area.

Abstract: In a patterning process of a semiconductor device having inverted stagger type TFTs, a normal photolithography step using diazo naphthoquinone (DNQ)-Novolac resin based positive photo resist is applied, and a problem of the area dependency of the photo resist pattern side wall taper angle may occur. The problem is critical for the reason of influence on variation of an etching shape in a dry-etching step. The present invention has an object to solve the above problem. In a photolithography step, which is patterning step of a semiconductor device having inverted stagger type TFTs, by adjusting a pre-bake temperature or a PEB (post-exposure-bake) temperature, and positively performing evacuation of solvent in a state of a photo resist film, the volume contraction by evacuation of solvent at the post-bake is reduced, and the problem of the area dependency of the photo resist pattern side wall taper angle is solved, which is deformation due to the volume contraction.

Abstract: A simplified tri-layer process for forming a thin film transistor matrix for a liquid crystal display is disclosed. By using a backside exposure technique, the masking step for patterning an etch stopper layer can be omitted. After forming an active region including a gate electrode and a scan line on the front side of a substrate, and sequentially applying an etch stopper layer and a photoresist layer over the resulting structure, the backside exposure is performed by exposing from the back side of the substrate. A portion of photoresist is shielded by the active region from exposure so that an etch stopper structure having a shape similar to the shape of the active region is formed without any photo-masking and lithographic procedure. Therefore, the above self-aligned effect allows one masking step to be reduced so as to simplify the process.

Abstract: This invention relates to a TFT-LCD and a manufacturing method therefor which etches triple layer patterns in a single process step. As a result, the number of masking processes is reduced and a high quality device is produced with less defects.

Abstract: The shape of chrome patterns on an optical pattern transfer tool are adjusted to get a desired shape on a wafer in the manufacture of semiconductor devices, wherein very small regions on a photoresist are defined and these regions are controlled with a high degree of accuracy. The optical pattern transfer tool has first and second planar surfaces lying in substantially parallel planes and a plurality of opaque regions overlying the first planar surface. First and second steps formed between and the first and second planar surfaces at first and second edges, respectively, define a width of the first planar surface. Each of the opaque regions are spaced from one another and offset from one another such that they are alternately aligned along a length of the first planar surface, such that one of the opaque regions is aligned with a portion of the first edge and the next one of the opaque regions along the length is aligned with a portion of the second edge.

Abstract: A thin-film circuit element such as a top-gate TFT has good quality electrical contacts formed between an electrode (151, 152, 155) of chromium nitride and the semiconductor film (50) of the circuit element and/or another conductive film such as a connection track (37,39,40) of, for example, aluminium. Chromium nitride has a particularly advantageous combination of propertied for use as such an electrode material, including, for example, low affinity for oxide growth even during deposition thereon of semiconductor, insulating and/or metal films, a doping potential to enhance ohmic contact to semiconductors, a barrier function against potential impurities, good thin-film processing compatibility, and hillock prevention in an underlying aluminium conductor.

Abstract: A method for forming a gate dielectric having regions with different dielectric constants. A dummy dielectric layer is formed over a semiconductor structure. The dummy dielectric layer is patterned to form a gate opening. A high-K dielectric layer is formed over the dummy dielectric and in the gate opening. A low-K dielectric layer is formed on the high-K dielectric layer. Spacers are formed on the low-K dielectric layer at the edges of the gate opening. The low-K dielectric layer is removed from the bottom of the gate opening between the spacers. The spacers are removed to form a stepped gate opening. The stepped gate opening has both a high-K dielectric layer and a low-K dielectric layer on the sidewalls and at the edges of the bottom of the gate opening and only a high-k dielectric layer in the center of the bottom of the stepped gate opening. A gate electrode is formed in the stepped gate opening.

Abstract: This invention relates to a TFT-LCD and a manufacturing method therefor which etches triple layer patterns in a single process step. As a result, the number of masking processes is reduced and a high quality device is produced with less defects.

Abstract: A method for opening resist in raised areas of a semiconductor device. In one aspect, a conductive layer is formed over a channel insulator layer to form a raised portion including a height above a substantially planar surrounding area, the channel insulator layer being aligned to a gate electrode. A photoresist layer is formed over the raised portion and the surrounding area, and patterned by employing a gray scale light mask to reduce exposure light on the photoresist over the raised portion. Then, the photoresist is etched to thin it such that a gap is formed in the photoresist down to the conductive layer over the raised portion, but the photoresist remains everywhere else, and the conductive layer is etched in accordance with the photoresist to form source and drain electrodes which are self aligned to the channel insulator layer.

Abstract: A simplified tri-layer process for forming a thin film transistor matrix for a liquid crystal display is disclosed. By using a backside exposure technique, the masking step for patterning an etch stopper layer can be omitted. After forming an active region including a gate electrode and a scan line on the front side of a substrate, and sequentially applying an etch stopper layer and a photoresist layer over the resulting structure, the backside exposure is performed by exposing from the back side of the substrate. A portion of photoresist is shielded by the active region from exposure so that an etch stopper structure having a shape similar to the shape of the active region is formed without any photo-masking and lithographic procedure. Therefore, the above self-aligned effect allows one masking step to be reduced so as to simplify the process.

Abstract: There is provided a structure of a pixel TFT (n-channel type TFT) in which an off current value is sufficiently low. In impurity regions, a concentration distribution of an impurity element imparting one conductivity type is made to have a concentration gradient, the concentration is made low at a side of a channel formation region, and the concentration is made high at the side of an end portion of a semiconductor layer.

Abstract: To provide a technique required for purifying the interface between an active layer and an insulating film. On a substrate (101), a gate wiring (103) is formed and the surface thereof is covered with a gate oxide film (104). Then, a first insulating film (105a), a second insulating film (105b), a semiconductor film (106) and a protective film (107) are sequentially formed and layered without exposing them to the air. Further, the semiconductor film (106) is irradiated with laser light through the protective film (107). In this way, a TFT may be given good characteristics by completely purifying the interface of the semiconductor film.

Abstract: A gate electrode is formed on the substrate, and a gate insulating layer is formed over the gate electrode. An amorphous silicon layer and a doped amorphous silicon layer is formed in sequence. On the doped amorphous silicon layer, a source and a drain electrode made of molybdenum or molybdenum-tungsten alloy is formed and the doped amorphous silicon layer is dry etched. When the doped amorphous silicon layer is dry etched, the source/drain electrodes or the photoresist pattern used to form the source/drain electrodes is used as a mask, and a HCl+CF4 gas system is used for dry etching gas. After dry etching the doped amorphous silicon layer, in-situ He plasma treatment is performed. If HCl+CF4+O2 dry etching gas is used to etch the doped amorphous silicon layer, the characteristics of TFT may be improved with one dry etch process without the additional plasma treatment.

Abstract: The present invention discloses a TFT array substrate that is fabricated using a four-mask process and a method of manufacturing that TFT array substrate. The gate line and gate electrode of the array substrate is surrounded by the metallic oxide after finishing a first mask process using thermal treatment. As a result, the gate line and gate electrode are not eroded and damaged by the etchant and stripper during a fourth mask process. Further, buffering layer can optionally be formed between the substrate and the gate line and gate electrode. Thus, silicon ions and oxygen ions included in the substrate are not diffused into the gate line and electrode. Accordingly, the line defect such as a line open of the gate line and gate electrode is prevented, thereby preventing inferior goods while increasing the manufacturing yield.

Abstract: A method for fabricating a BCE type TFT array by using reduced number of masks and devices formed are disclosed. In the method, only five masks are required for forming the BCE type TFT array which is less than that normally required in a typical TFT fabrication process, i.e., at least six masks. The five masks required in the present invention process are a first mask for gate busline patterning, a second mask for island and S/D data line patterning, a third mask for the data line, TFT channel and Cst patterning, a fourth mask for the passivation layer patterning and a fifth mask for the conductive electrode layer patterning. The present invention novel method produces a TFT that has improved contact resistance between the S/D metal and the n+ amorphous silicon layer.

Abstract: On a transparent substrate where a gate electrode is formed, an amorphous silicon film is deposited by plasma CVD with a gate insulating film interposed therebetween. The silicon film is heated in an nitrogen atmosphere at 430±20° C. for an hour or longer to discharge hydrogen remaining in the film when it is formed. The silicon film is then melted by laser irradiation to crystallize, to thereby form a polycrystalline silicon film serving as an active region. Thus, when amorphous silicon is crystallized to form a polycrystalline silicon film, it is made possible to prevent creation of a rough film surface and penetration of impurity ions in the atmosphere into the polycrystalline silicon.

Abstract: A semiconductor device comprising a substrate having an insulating surface layer and an active layer comprising a semiconductor thin film formed thereon, wherein the substrate and the insulating surface layer in contact with the substrate each has at least one concave part, and the influence of the concave part is removed by conducting a flattening treatment and heat treatment of the undercoat film of the semiconductor thin film.

Abstract: The present invention discloses a method of manufacturing a thin film transistor, including: depositing an amorphous silicon layer, an insulating layer, and a gate metal layer on a substrate sequentially; patterning the insulating layer and the gate metal layer to form a gate insulating layer and a gate electrode; treating an impurity and a catalyst metal on the amorphous silicon layer using the gate electrode as a mask; and applying a DC voltage to both terminals of the amorphous silicon layer to form a polysilicon layer, the polysilicon layer having source and drain regions and an active area.

Abstract: A pair of thin film transistors formed in adjacent layers of polysilicon. The gate of the first TFT and the source, drain and channel regions of the second TFT are formed in the first polysilicon layer. The source, drain and channel regions of the first TFT and the gate of the second TFT are formed in the second polysilicon layer. A dielectric layer is interposed between the first and second polysilicon layers. The first TFT gate overlaps the second TFT drain region in the first polysilicon layer and the second TFT gate overlaps the first TFT drain region in the second polysilicon layer. In another aspect of the invention, two TFTs are incorporated into a SRAM memory cell.

Abstract: A method for manufacturing a thin film transistor array panel for a liquid crystal display is disclosed. The present invention enables to manufacture a thin film transistor array panel in lesser steps than the conventional method by fabricating certain film layers on the panel in one photolithography process. For this purpose, a mask that has parts of different light transmittance is used to fabricate multiple film layers in one photolithography process. The method according to the present invention can increase the productivity and yield by reducing the number of photolithography steps, which are expensive and time consuming.

Abstract: A process sequence is disclosed for fabricating arrays of Thin Film Transistors by printing metallic conductors for the gate and data lines and possibly the Indium Tin Oxide Pixel electrode as well. The process eliminates conventional step-and-repeat photolithographic patterning, and provides high conductivity metallization for large arrays. These arrays may be used in displays, detectors and scanners.

Abstract: A thin film transistor includes a substrate, a gate electrode formed on the substrate, and including opposing edge portions and a middle portion. An insulating film is formed on the surface of the gate electrode having a greater thickness on one of the gate edge portions. An active region is formed on the surface of the insulating film and the exposed substrate. The active region includes an off-set region, a channel region, a source region, and a drain region.

Abstract: An additional high quality insulating layer is grown over the substrate after the formation of the gate electrode of a thin film transistor (TFT). The growth temperature of the insulating layer can be higher than conventional method and the insulating layer is more free of pin-holes. After the insulating layer in the thin oxide region of the TFT is etched away, conventional fabrication processes are followed. The dielectric of the thin film oxide region is the same as that of the conventional TFT; but the dielectric in the vicinity of the thin oxide region, the crossovers of the data lines and the scan lines, and the gate dielectric layer of the TFT are now composed of the high quality insulating layer. The TFT structure can improve the yield of fabrication by confining the channel region in the shadow of the gate electrode to reduce the leakage photo-current, and by reducing the steps at crossovers steps and interconnections to avoid open-circuit.

Abstract: A method for forming a TFT device comprises the following steps. First, a first metal layer, a first insulating layer, a active layer and a contact layer are formed on the substrate in sequence. Next, a first photomask is used to define the contact layer, the active layer, the first insulating layer, and the first metal layer. Then, a second insulating layer and a transparent conducting layer are formed on the contact layer and the substrate in sequence. A second photomask is used to define the second insulating layer and the transparent conducting layer to expose a surface of the contact layer. A second metal layer is formed on the transparent conducting layer and contact layer. A third photomask is used to define the second metal layer to form the S/D structures. Then, the S/D structures are used to serve as a mask for etching the contact layer.