Abstract: A normally-off transistor includes a channel layer, an electron supply layer overlaying the channel layer, a source electrode and a drain electrode on the electron supply layer, an area in the electrode supply layer between the source electrode and the drain electrode treated with a fluoride based plasma followed by a chlorine based plasma treatment, a gate insulator overlaying the area, and a gate electrode overlaying the gate insulator.

Abstract: A vertical type GaN series field effect transistor having excellent pinch-off characteristics is provided. A compound semiconductor device includes a conductive semiconductor substrate, a drain electrode formed on a bottom surface of the conductive semiconductor substrate, a current blocking layer formed on a top surface of the conductive semiconductor substrate, made of high resistance compound semiconductor or insulator, and having openings, an active layer of compound semiconductor burying the openings and extending on an upper surface of the current blocking layer, a gate electrode formed above the openings and above the active layer, and a source electrode formed laterally spaced from the gate electrode and formed above the active layer.

Abstract: According to one disclosed embodiment, an enhancement mode high electron mobility transistor (HEMT) comprises a heterojunction including a group III-V barrier layer situated over a group III-V semiconductor body, and a gate structure formed over the group III-V barrier layer and including a P type group III-V gate layer. The P type group III-V gate layer prevents a two dimensional electron gas (2 DEG) from being formed under the gate structure. One embodiment of a method for fabricating such an enhancement mode HEMT comprises providing a substrate, forming a group III-V semiconductor body over the substrate, forming a group III-V barrier layer over the group III-V semiconductor body, and forming a gate structure including the P type group III-V gate layer over the group III-V barrier layer.

Abstract: An improved pseudomorphic high electron mobility transistor (pHEMT) and heterojunction bipolar transistor (HBT) integrated epitaxial structure and the fabrication method thereof, in which the structure comprises a substrate, a pHEMT structure, an etching-stop spacer layer, and an HBT structure. The pHEMT's structure comprises a buffer layer, a barrier layer, a first channel spacer layer, a channel layer, a second channel spacer layer, a Schottky barrier layer, an etching-stop layer, and at least one cap layer. The fabrication method of an HBT and a pHEMT are also included.

Abstract: Embodiments of the present disclosure describe apparatuses, methods, and systems of an integrated circuit (IC) device. The IC device may include a buffer layer disposed on a substrate, the buffer layer including gallium (Ga) and nitrogen (N), a barrier layer disposed on the buffer layer, the barrier layer including aluminum (Al) and nitrogen (N), wherein the barrier layer includes an oxidized portion of the barrier layer, a gate dielectric disposed on the oxidized portion of the barrier layer, and a gate electrode disposed on the gate dielectric, wherein the oxidized portion of the barrier layer is disposed in a gate region between the gate electrode and the buffer layer.

Abstract: Provided is an epitaxial substrate for semiconductor device that is capable of achieving a semiconductor device having high reliability in reverse characteristics of schottky junction. An epitaxial substrate for semiconductor device obtained by forming, on a base substrate, a group of group III nitride layers by lamination such that a (0001) crystal plane of each layer is approximately parallel to a substrate surface includes: a channel layer formed of a first group III nitride having a composition of Inx1Aly1Gaz1N (x1+y1+z1=1, z1>0); and a barrier layer formed of a second group III nitride having a composition of Inx2Aly2N (x2+y2=1, x2>0, y2>0), wherein the second group III nitride is a short-range-ordered mixed crystal having a short-range order parameter ? satisfying a range where 0???1.

Abstract: A III-N semiconductor device that includes a substrate and a nitride channel layer including a region partly beneath a gate region, and two channel access regions on opposite sides of the part beneath the gate. The channel access regions may be in a different layer from the region beneath the gate. The device includes an AlXN layer adjacent the channel layer wherein X is gallium, indium or their combination, and a preferably n-doped GaN layer adjacent the AlXN layer in the areas adjacent to the channel access regions. The concentration of Al in the AlXN layer, the AlXN layer thickness and the n-doping concentration in the n-doped GaN layer are selected to induce a 2DEG charge in channel access regions without inducing any substantial 2DEG charge beneath the gate, so that the channel is not conductive in the absence of a switching voltage applied to the gate.

Abstract: A high electron mobility field effect transistor (HEMT) includes a two dimensional electron gas (2DEG) in the drift region between the gate and the drain that has a non-uniform lateral 2DEG distribution that increases in a direction in the drift region from the gate to the drain.

Abstract: Methods for forming a HEMT device are provided. The method includes forming an ultra-thin barrier layer on the plurality of thin film layers. A dielectric thin film layer is formed over a portion of the ultra-thin barrier layer to leave exposed areas of the ultra-thin barrier layer. A SAG S-D thin film layer is formed over the exposed areas of the ultra-thin barrier layer while leaving the dielectric thin film layer exposed. The dielectric thin film layer is then removed to expose the underlying ultra-thin barrier layer. The underlying ultra-thin barrier layer is treating with fluorine to form a treated area. A source and drain is added on the SAG S-D thin film layer, and a dielectric coating is deposited over the ultra-thin barrier layer treated with fluorine such that the dielectric coating is positioned between the source and the drain.

Abstract: Embodiments of the present disclosure describe apparatuses, methods, and systems of a device such as a transistor. The device includes a buffer layer disposed on a substrate, the buffer layer being configured to serve as a channel of a transistor and including gallium (Ga) and nitrogen (N), a barrier layer disposed on the buffer layer, the barrier layer being configured to supply mobile charge carriers to the channel and including aluminum (Al), gallium (Ga), and nitrogen (N), a charge-inducing layer disposed on the barrier layer, the charge-inducing layer being configured to induce charge in the channel and including aluminum (Al) and nitrogen (N), and a gate terminal disposed in the charge-inducing layer and coupled with the barrier layer to control the channel. Other embodiments may also be described and/or claimed.

Abstract: A HEMT device has a substrate; a buffer layer disposed above the substrate; a carrier supplying layer disposed above the buffer layer; a gate element penetrating the carrier supplying layer; and a drain element disposed on the carrier supplying layer. The carrier supplying layer has a non-uniform thickness between the gate element and the drain element, the carrier supplying layer having a relatively greater thickness adjacent the drain element and a relatively thinner thickness adjacent the gate element. A non-uniform two-dimensional electron gas conduction channel is formed in the carrier supplying layer, the two-dimensional electron gas conduction channel having a non-uniform profile between the gate and drain elements.

Abstract: A method includes forming a first epitaxial layer over a semiconductor substrate and etching the first epitaxial layer to form multiple separated first epitaxial regions. The method also includes forming a second epitaxial layer over the etched first epitaxial layer. Each epitaxial layer includes at least one Group III-nitride, and the epitaxial layers collectively form a buffer. The method further includes forming a device layer over the buffer and fabricating a semiconductor device using the device layer. The second epitaxial layer could include second epitaxial regions substantially only on the first epitaxial regions. The second epitaxial layer could also cover the first epitaxial regions and the substrate, and the second epitaxial layer may or may not be etched. The device layer could be formed during the same operation used to form the second epitaxial layer.

Abstract: A transistor includes a first semiconductor layer formed on a substrate, a second semiconductor layer formed on the first semiconductor layer and has a band gap larger than that of the first semiconductor layer, a control layer formed on the second semiconductor layer and contains p-type impurities, a gate electrode formed in contact with at least part of the control layer and a source electrode and a drain electrode formed on both sides of the control layer, respectively. A third semiconductor layer made of material having a lower etch rate than that of the control layer is formed between the control layer and the second semiconductor layer.

Abstract: A HEMT comprising a plurality of active semiconductor layers formed on a substrate. Source electrode, drain electrode, and gate are formed in electrical contact with the plurality of active layers. A spacer layer is formed on at least a portion of a surface of said plurality of active layers and covering the gate. A field plate is formed on the spacer layer and electrically connected to the source electrode, wherein the field plate reduces the peak operating electric field in the HEMT.

Abstract: Disclosed is a semiconductor device. More specifically, disclosed are a nitride-based heterojunction semiconductor device and a method for producing the same. The nitride-based heterojunction semiconductor device includes a nitride semiconductor buffer layer, a barrier layer disposed on the buffer layer, a cap layer discontinuously disposed on the barrier layer, a source electrode and a drain electrode that contact at least one of the barrier layer and the cap layer, and a gate electrode that Schottky-contacts at least one of the barrier layer and the cap layer and is disposed between the source electrode and the drain electrode.

Abstract: A nitride semiconductor device includes a substrate, an electron transit layer and an electron supply layer that are sequentially formed above the substrate, where the electron supply layer has a different band gap energy than the electron transit layer, a drain electrode, a gate electrode, and a source electrode that is formed on the opposite side of the drain electrode with the gate electrode being sandwiched between the drain electrode and the source electrode. Here, a plurality of lower concentration regions are formed so as to be spaced away from each other on the surface of the electron transit layer between the gate electrode and the drain electrode. In the lower concentration regions, the concentration of a two-dimensional electron gas is lower than in other regions.

Abstract: A method for growing high mobility, high charge Nitrogen polar (N-polar) or Nitrogen face (In, Al, Ga)N/GaN High Electron Mobility Transistors (HEMTs). The method can provide a successful approach to increase the breakdown voltage and reduce the gate leakage of the N-polar HEMTs, which has great potential to improve the N-polar or N-face HEMTs' high frequency and high power performance.

Abstract: According to example embodiments, High electron mobility transistors (HEMTs) may include a discontinuation region in a channel region. The discontinuation region may include a plurality of 2DEG unit regions that are spaced apart from one another. The discontinuation region may be formed at an interface between two semiconductor layers or adjacent to the interface. The discontinuation region may be formed by an uneven structure or a plurality of recess regions or a plurality of ion implantation regions. The plurality of 2DEG unit regions may have a nanoscale structure. The plurality of 2DEG unit regions may be formed in a dot pattern, a stripe pattern, or a staggered pattern.

Abstract: Disclosed herein are embodiments of a normally-off compound semiconductor tunnel field effect transistor having a drive current above 100 mA per mm of gate length and a sub-threshold slope below 60 mV per decade at room temperature, and methods of manufacturing such a normally-off compound semiconductor tunnel transistor. The compound semiconductor tunnel field effect transistor is fast-switching and can be used for high voltage applications e.g. 30V up to 600V and higher.

Abstract: A dual-gate normally-off nitride transistor that includes a first gate structure formed between a source electrode and a drain electrode for controlling a normally-off channel region of the dual-gate normally-off nitride transistor. A second gate structure is formed between the first gate structure and the drain electrode for modulating a normally-on channel region underneath the second gate structure. The magnitude of the threshold voltage of the second gate structure is smaller than the drain breakdown of the first gate structure for proper operation of the dual-gate normally-off nitride transistor.

Abstract: An embodiment of a compound semiconductor device includes: a substrate; a compound semiconductor stacked structure formed over the substrate; and a gate electrode, a source electrode and a drain electrode formed on or above the compound semiconductor stacked structure. The compound semiconductor stacked structure includes: an electron channel layer; and a nitride semiconductor layer which includes an electron supply layer formed over the electron channel layer. An indium (In) fraction at a surface of the nitride semiconductor layer in each of a region between the gate electrode and the source electrode and a region between the gate electrode and the drain electrode is lower than an indium (In) fraction at a surface of the nitride semiconductor layer in a region below the gate electrode.

Abstract: A compound semiconductor device is provided with a first nitride semiconductor layer of a first conductivity type, a second nitride semiconductor layer of the first conductivity type which is formed over the first nitride semiconctor layer and being in contact with the first nitride semiconductor layer, a third nitride semiconductor layer of a second conductivity type being in contact with the second nitride semiconductor layer, a fourth nitride semiconductor layer of the first conductivity type being in contact with the third nitride semiconductor layer, and an insulating film insulating the first nitride semiconductor layer and the fourth nitride, semiconductor layer from each other. A source electrode is positioned inside an Outer edge of the insulating film in planar view.

Abstract: A semiconductor device includes a semiconductor body including a plurality of compound semiconductor layers and a two-dimensional charge carrier gas channel region formed in one of the compound semiconductor layers. The semiconductor device further includes a contact structure disposed in the semiconductor body. The contact structure includes a metal region and a doped region. The metal region extends into the semiconductor body from a first side of the semiconductor body to at least the compound semiconductor layer which includes the channel region. The doped region is formed in the semiconductor body between the metal region and the channel region so that the channel region is electrically connected to the metal region through the doped region.

Abstract: A high electron mobility transistor (HEMT) includes a substrate, an HEMT stack spaced apart from the substrate, and a pseudo-insulation layer (PIL) disposed between the substrate and the HEMT stack. The PIL layer includes at least two materials having different phases. The PIL layer defines an empty space that is wider at an intermediate portion than at an entrance of the empty space.

Abstract: Two layers of protection films are formed such that a sheet resistance at a portion directly below the protection film is higher than that at a portion directly below the protection film. The protection films are formed, for example, of SiN film, as insulating films. The protection film is formed to be higher, for instance, in hydrogen concentration than the protection film so that the protection film is higher in refractive index the protection film. The protection film is formed to cover a gate electrode and extend to the vicinity of the gate electrode on an electron supplying layer. The protection film is formed on the entire surface to cover the protection film. According to this configuration, the gate leakage is significantly reduced by a relatively simple configuration to realize a highly-reliable compound semiconductor device achieving high voltage operation, high withstand voltage, and high output.

Abstract: According to one embodiment, a nitride semiconductor device has an electroconductive substrate, a first nitride semiconductor layer provided directly on the electroconductive substrate or provided on the electroconductive substrate through a buffer layer and formed of a non-doped nitride semiconductor, a second nitride semiconductor layer provided on the first nitride semiconductor layer and formed of a non-doped or n-type nitride semiconductor having a band gap wider than that of the first nitride semiconductor layer, a heterojunction field effect transistor having a source electrode, a drain electrode, and a gate electrode, a Schottky barrier diode having an anode electrode and a cathode electrode, first and second element isolation insulating layers, and a frame electrode. The frame electrode is electrically connected to the source electrode and the electroconductive substrate, and surrounds outer peripheries of the heterojunction field effect transistor and the Schottky barrier diode.

Abstract: Disclosed are a GaN (gallium nitride) compound power semiconductor device and a manufacturing method thereof. The gallium nitride compound power semiconductor device includes: a gallium nitride compound element formed by being grown on a wafer; a contact pad including a source, a drain, and a gate connecting with the gallium nitride compound element; a module substrate to which the nitride gallium compound element is flip-chip bonded; a bonding pad formed on the module substrate; and a bump formed on the bonding pad of the module substrate so that the contact pad and the bonding pad are flip-chip bonded.

Abstract: In a high electron mobility transistor, with a normally-off operation maintained, on-resistance can be sufficiently reduced, so that the performance of a semiconductor device including the high electron mobility transistor is improved. Between a channel layer and an electron supply layer, a spacer layer whose band gap is larger than the band gap of the electron supply layer is provided. Thereby, due to the fact that the band gap of the spacer layer is large, a high potential barrier (electron barrier) is formed in the vicinity of an interface between the channel and the electron supply layer.

Abstract: According to one exemplary embodiment, a group III-V semiconductor device includes at least one transition layer situated over a substrate. The group III-V semiconductor device further includes a first strain-relieving interlayer situated over the at least one transition layer and a second strain-relieving interlayer situated over the first strain-relieving interlayer. The group III-V semiconductor device further includes a first group III-V semiconductor body situated over the second strain-relieving interlayer. The first and second strain-relieving interlayers comprise different semiconductor materials so as to reduce a strain in the first group III-V semiconductor body. The second strain-relieving interlayer can be substantially thinner than the first strain-relieving interlayer.

Abstract: A semiconductor device includes a compound semiconductor substrate; a first conductivity type-channel field-effect transistor region formed on the compound semiconductor substrate, and that includes a first channel layer; a first conductivity type first barrier layer that forms a heterojunction with the first channel layer, and supplies a first conductivity type charge to the first channel layer; and a second conductivity type gate region that has a pn junction-type potential barrier against the first conductivity type first barrier layer; and a second conductivity type-channel field-effect transistor region formed on the compound semiconductor substrate, and that includes a second conductivity type second channel layer, and a first conductivity type gate region that has a pn junction-type potential barrier against the second conductivity type second channel layer.

Abstract: This invention provides methods for fabricating substantially continuous layers of a group III nitride semiconductor material having low defect densities and optionally having a selected crystal polarity. The methods include epitaxial growth nucleating and/or seeding on the upper portions of a plurality of pillars/islands of a group III nitride material that are irregularly arranged on a template structure. The upper portions of the islands have low defect densities and optionally have a selected crystal polarity. The invention also includes template structures having a substantially continuous layer of a masking material through which emerge upper portions of the pillars/islands. The invention also includes such template structures. The invention can be applied to a wide range of semiconductor materials, both elemental semiconductors, e.g., combinations of Si (silicon) with strained Si (sSi) and/or Ge (germanium), and compound semiconductors, e.g.

Abstract: An Enhancement-mode (E-mode) high electron mobility transistor (HEMT) includes a channel layer with a 2-Dimensional Electron Gas (2DEG), a barrier layer inducing the 2DEG in the channel layer, source and drain electrodes on the barrier layer, a depletion layer on the barrier layer between the source and drain electrodes, and a gate electrode on the depletion layer. The barrier layer is recessed below the gate electrode and the depletion layer covers a surface of the recess and extends onto the barrier layer around the recess.

Abstract: A group III-N nanowire is disposed on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first group III-N material, a source region electrically coupled with a first end of the channel region, and a drain region electrically coupled with a second end of the channel region. A second group III-N material on the first group III-N material serves as a charge inducing layer, and/or barrier layer on surfaces of nanowire. A gate insulator and/or gate conductor coaxially wraps completely around the nanowire within the channel region. Drain and source contacts may similarly coaxially wrap completely around the drain and source regions.

Abstract: Transistors for high voltage and high frequency operation. A non-planar, polar crystalline semiconductor body having a top surface disposed between first and second opposite sidewalls includes a channel region with a first crystalline semiconductor layer disposed over the first and second sidewalls. The first crystalline semiconductor layer is to provide a two dimensional electron gas (2DEG) within the channel region. A gate structure is disposed over the first crystalline semiconductor layer along at least the second sidewall to modulate the 2DEG. First and second sidewalls of the non-planar polar crystalline semiconductor body may have differing polarity, with the channel proximate to a first of the sidewalls. The gate structure may be along a second of the sidewalls to gate a back barrier. The polar crystalline semiconductor body may be a group III-nitride formed on a silicon substrate with the (10 10) plane on a (110) plane of the silicon.

Abstract: A semiconductor device includes a substrate, a carrier transit layer disposed above the substrate, a compound semiconductor layer disposed on the carrier transit layer, a source electrode disposed on the compound semiconductor layer, a first groove disposed from the back of the substrate up to the inside of the carrier transit layer while penetrating the substrate, a drain electrode disposed in the inside of the first groove, a gate electrode located between the source electrode and the first groove and disposed on the compound semiconductor layer, and a second groove located diagonally under the source electrode and between the source electrode and the first groove and disposed from the back of the substrate up to the inside of the carrier transit layer while penetrating the substrate.

Abstract: Systems, methods, and apparatus described herein are associated with devices including hybrid electrodes. A heterostructure semiconductor transistor can include a III-N-type semiconductor heterostructure including a barrier layer overlying an active layer and a hybrid electrode region including a hybrid drain electrode region. Further, a heterostructure semiconductor rectifier can include a III-N-type semiconductor heterostructure and a hybrid electrode region including a hybrid cathode electrode region. Furthermore, the hybrid electrode region of the transistor and rectifier can include permanently trapped charge located under a Schottky contact of the hybrid electrode region.

Abstract: Embodiments of a strained semiconductor device are provided, as are embodiments of a method for fabricating such a strained semiconductor device. In one embodiment, the method includes providing a partially-fabricated semiconductor device including a semiconductor substrate having a source side and a drain side, a gate stack formed on the semiconductor substrate, and a channel region formed within the semiconductor substrate beneath the gate stack and extending from the source side to the drain side of the semiconductor substrate. A cavity is produced in only one of the source side and the drain side of the semiconductor substrate, and a strain-inducing material is formed within the cavity to create an asymmetric heterojunction structure within the semiconductor substrate.

Abstract: A method of forming a semiconductor device, the method comprising providing a semiconductor layer, and providing a first layer of a first metal on the semiconductor layer. A second layer may be provided on the first layer of the first metal. The second layer may include a layer of silicon and a layer of a second metal, and the first and second metals may be different. The first metal may be titanium and the second metal may be nickel. Related devices, structures, and other methods are also discussed.

Abstract: To suppress adverse affect caused by dopant in a conductive semiconductor layer in a GaN-based device having a structure in which the conductive semiconductor layer is inserted between a substrate and an active layer. In an HEMT device 10, n-GaN (n-type GaN wafer) is used as a substrate 11. A p-type GaN layer (conductive semiconductor layer) 12 is formed on the substrate 11 for the purpose of reducing a leak current and suppressing current collapse, etc. A non-doped AlN layer (semi-insulating semiconductor layer) 13 is formed on the p-type GaN layer 12, and a channel layer (active layer) 14 formed of semi-insulating GaN and an electron supply layer (active layer) 15 formed of n-AlGaN are sequentially formed by the MBE method, MOVPE method, or the like.

Abstract: A method for fabricating a gate structure for a field effect transistor having a buffer layer on a substrate, a channel layer and a barrier layer over the channel layer includes forming a gate including silicon, forming first sidewalls of a first material on either side and adjacent to the gate, selectively etching into the buffer layer to form a mesa for the field effect transistor, depositing a material layer over the mesa, planarizing the material layer over the mesa to form a planarized surface such that a top of the gate, tops of the first sidewalls, and a top of the material layer over the mesa are on the same planarized surface, depositing metal on the planzarized surface, annealing to form the gate into a metal silicided gate, and etching to remove excess non-silicided metal.

Abstract: According to one disclosed embodiment, a monolithic vertically integrated composite device comprises a double sided semiconductor substrate having first and second sides, a group IV semiconductor layer formed over the first side and comprising at least one group IV semiconductor device, and a group III-V semiconductor body formed over the second side and comprising at least one group III-V semiconductor device electrically coupled to the at least one group IV semiconductor device. The composite device may further comprise a substrate via and/or a through-wafer via providing electric coupling. In one embodiment, the group IV semiconductor layer may comprise an epitaxial silicon layer, and the at least one group IV semiconductor device may be a combined FET and Schottky diode (FETKY) fabricated on the epitaxial silicon layer. In one embodiment, the at least one group III-V semiconductor device may be a III-nitride high electron mobility transistor (HEMT).

Abstract: The present invention relates to an enhancement normally off nitride semiconductor device and a method of manufacturing the same. The method includes the steps of: forming a buffer layer on a substrate; forming a first nitride semiconductor layer on the buffer layer; forming a second nitride semiconductor layer on the first nitride semiconductor layer; etching a gate region above the second nitride semiconductor layer up to a predetermined depth of the first nitride semiconductor layer; forming an insulating film on the etched region and the second nitride semiconductor layer; patterning a source/drain region, etching the insulating film in the source/drain region, and forming electrodes in the source/drain region; and forming a gate electrode on the insulating film in the gate region. In this manner, the present invention provides a method of easily implementing a normally off enhancement semiconductor device by originally blocking 2DEG which is generated under a gate region.

Abstract: A compound semiconductor device includes: a substrate; an electron transit layer and electron supply layer formed over the substrate; a gate electrode, source electrode, and drain electrode formed over the electron supply layer; and a first Fe-doped layer provided between the substrate and the electron transit layer in a region corresponding to the position of the gate electrode in plan view, the first Fe-doped layer being doped with Fe to reduce two dimensional electron gas generated below the gate electrode.

Abstract: A transistor device includes a compound semiconductor body, a drain disposed in the compound semiconductor body and a source disposed in the compound semiconductor body and spaced apart from the drain by a channel region. A gate is provided for controlling the channel region. The transistor device further includes a gate overvoltage protection device connected between the source and the gate, the gate overvoltage protection device including p-type and n-type silicon-containing semiconductor material.

Abstract: According to an embodiment, a semiconductor device includes a first layer including a first nitride semiconductor, a second layer provided on the first layer and including a second nitride semiconductor having a wider bandgap than the first nitride semiconductor. The device also includes a source electrode and a drain electrode provided on the second layer; and a gate electrode provided on the second layer and located between the source electrode and the drain electrode. The second layer includes a first region between the gate electrode and the drain electrode, the first region being selectively provided in a surface of the second layer and contains fluorine. A concentration of fluorine in the first region is higher than a concentration of fluorine in a portion underneath the gate electrode in the second layer.

Abstract: A semiconductor device includes: a gate electrode that is provided on a semiconductor layer, and contains a Ni-containing layer; an insulating film that covers the gate electrode, and has a step; a covering layer that is provided between the gate electrode and the insulating film, and is arty one of a metal which has a melting point equal to or more than 1,600 degrees, and an oxide and a nitride of the metal; and a metal layer that is provided on the step.

Abstract: A III-nitride semiconductor device which includes a charged gate insulation body.

Abstract: A compound semiconductor device includes a substrate; a buffer layer formed on the substrate; an electron transit layer and an electron donating layer formed on the buffer layer; a gate electrode, a source electrode, and a drain electrode formed on the electron donating layer; and an embedded electrode to which a potential independent of the gate electrode, the source electrode, and the drain electrode is supplied to control a potential of the buffer layer.

Abstract: An embodiment of a compound semiconductor device includes: a substrate; an electron transport layer and an electron supply layer formed over the substrate; a gate electrode, a source electrode and a drain electrode formed over the electron supply layer; a p-type semiconductor layer formed between the electron supply layer and the gate electrode; and a hole canceling layer formed between the electron supply layer and the p-type semiconductor layer, the hole canceling layer containing a donor or a recombination center and canceling a hole.

Abstract: An embodiment of a compound semiconductor device includes: a substrate; an electron transport layer formed over the substrate; an electron supply layer formed over the electron transport layer; a source electrode and a drain electrode formed over the electron supply layer; a gate electrode formed over the electron supply layer between the source electrode and the drain electrode; a p-type compound semiconductor layer formed between the electron supply layer and the gate electrode; and a compound semiconductor layer containing an n-type impurity formed between the electron supply layer and the p-type compound semiconductor layer.