Abstract: A lateral thin-film Silicon-On-Insulator (SOI) device includes a semiconductor substrate, a buried insulating layer on the substrate and a lateral transistor device in an SOI layer on the buried insulating layer and having a source region of a first conductivity type formed in a body region of a second conductivity type opposite to that of the first. A lateral drift region of a first conductivity type is provided adjacent the body region, and a drain region of the first conductivity type is provided laterally spaced apart from the body region by the drift region. A gate electrode is provided over a part of the body region in which a channel region is formed during operation and extending over a part of the lateral drift region adjacent the body region, with the gate electrode being at least substantially insulated from the body region and drift region by an insulation region.

Abstract: The object of this invention is to provide a method of manufacturing diodes, said method being a method of manufacturing semiconductor devices whereby an insulating film as the upper layer of the diode can be removed without causing film peeling or leakage. A photodiode is formed by forming a semiconductor layer of a second conduction type 12 upon the surface layer of a semiconductor layer of a first conduction type 11, and next forming a removable mask layer 30 which has etching selectivity with respect to the semiconductor layer of a second conduction type, or alternately, forming an anti-reflection film AR upon the top layer of the semiconductor layer of a second conduction type and then forming a removable mask layer which has etching selectivity with respect to the anti-reflection film. Next, a removable insulating layer I which has etching selectivity with respect to the mask layer is formed upon the top layer of the mask layer.

Abstract: P-type impurities in a gate electrode is positively made to diffuse into a p-type impurity diffusion layer and an electrical p-n junction face in a gate electrode region is formed either within or on the bottom face of the p-type impurity diffusion layer, and thereby the effect that an interface state arising on a regrowth interface has over the p-n junction face can be well suppressed. This results in an improvement in high frequency characteristic of the JFET.

Abstract: An integrated circuit device is provided comprising an integrated circuit pad, an internal integrated circuit, and an ESD protection circuit. The internal integrated circuit is conductively coupled to the integrated circuit pad so as to define a primary electrical path from the integrated circuit pad to the internal integrated circuit. The ESD protection circuit is conductively coupled to the integrated circuit pad so as to define a secondary electrical path from the integrated circuit pad to the ESD protection circuit. The ESD protection circuit comprises a semiconductor structure arranged to define a doped silicon substrate, a drain region, a source region, an electrically insulating region, and a gate structure. The drain region is formed in the silicon substrate and is conductively coupled to the integrated circuit pad via the secondary electrical path. The source region is formed in the silicon substrate and is conductively coupled to a relatively low electrical potential.

Abstract: In a channel well of a semiconductive substrate, source, drain and gate electrodes are formed. Below the gate electrode region, a plurality of partial regions of the second conductive type are arranged next to each other in the direction of the extension of the gate electrode region and in a mutually spaced relationship, said partial regions bordering on the gate electrode region and extending through the channel well region into the region of the substrate bordering on the channel well region from below.

Abstract: This invention discloses the present invention discloses a junction field effect transistor UFET) device supported on a substrate. The JFET device includes a gate surrounded by a depletion region. As the distance between the gates is large enough, there is a gap between the depletion regions surrounding adjacent gates. Depletion mode JFET transistor which is normally on is provided. The normally on transistors respond to negative bias applied to the gates to shut of the current path in the substrate. The current path in the substrate is normally available with a zero gate bias. As the distance between the gates is reduced, the JFET transistor is normally off because the depletion regions surround the gates shut of the current channel. The depletion region responding to a positive bias applied to the gate to open a current path in the substrate wherein the current path in the substrate is shut off when the gate is zero biased.

Abstract: A method for crystallizing an amorphous layer into a polycrystalline layer. The method uses a substrate under the amorphous layer and a nickel film on the amorphous layer, which are subjected to a heat treatment. The nickel film is formed by a coating step that uses a nickel-containing solution. Alternatively, a nickel and gold, or a nickel and palladium, solution can be used. The method eliminates contamination with metal in the polycrystalline silicon layer and reduces its growth temperature.

Abstract: The SiC semiconductor structure contains at least three semiconductor regions. The surface area of the third semiconductor region encompasses that of the second semiconductor region as a second partial area, which in turn encloses the surface of the first semiconductor region as a first partial area. The contour of the edge of the second partial area is determined by the contour of the edge of the first partial area to the effect that the second partial area can be represented essentially as a specially enlarged mapping of the first partial area, the deviation of the contour of the edge of the second partial area from the exact contour that results in the course of the mapping being at most ±10 nm.

Abstract: A lateral bipolar field effect transistor having a drift region of a first conductivity formed on a silicon-on insulation substrate with a buried insulation layer, a gate region of a second conductivity formed over and from the buried insulation layer separated by a channel depth, in the drift region, a source region of the first conductivity contacting with the gate region and formed on the buried insulation layer, and a drain region of the first conductivity opposite to the source region, the drain region separated from the gate region by a selected distance. The gate region comprises a plurality of cells arranged parallel to an extension of the source region, each cell separated from adjacent cell by a channel width.

Abstract: A process for forming a metal suicide interconnect includes applying a layer of polysilicon over a semiconductor layer. A layer of amorphous silicon is formed over the layer of polysilicon followed by a layer of metal, such as titanium, over the layer of amorphous silicon. The layer of titanium is reacted with the layer of amorphous silicon to form a small grain C49 layer of titanium silicide. The layer of polysilicon and the layer of titanium silicide are etched to form a desired interconnect structure. The small grain C49 layer of titanium silicide is then converted to the C54 phase.

Abstract: An all-ion implanted gallium-nitride (GaN) junction field-effect transistor (JFET) and method of making the same. Also disclosed are various ion implants, both n- and p-type, together with or without phosphorous co-implantation, in selected III-V semiconductor materials.

Abstract: A silicon carbide gate turn off thyristor (GTO) has a silicon carbide junction field effect transistor (JFET) connected between the gate of the GTO and one of its anode or cathode electrodes thereby minimizing cooling requirements while providing for rapid switching.

Abstract: An implant mask (14) and an etch mask (16) are utilized in forming a silicon carbide JFET (10). A source opening (17) and a drain opening (18) are formed in the masks (14,16). The etch mask (16) is removed, and a source area (19) and a drain area 21 are implanted through the openings (17,18) and source and drain contact (23, 24) are formed. A protective layer (26) is used to form source and drain contacts (23,24). A gate contact (27) is utilized to ensure the gate (28) is self-aligned to the gate contact (27).