Abstract: A junction field effect transistor (JFET) is fashioned where a channel of transistor is buried deeply within the workpiece within which the JFET is formed. Burying the channel below the surface of the workpiece and/or away from overlying conductive materials distances a current that flows in the channel from outside influences, such as the effects of the overlying conductive materials. The deep channel also provides a more regular path for the current flowing therein by moving the channel away from non-uniformities on or near the surface of the workpiece, where said non-uniformities or irregularities would interrupt or otherwise disturb current flowing in a channel that is not as deep. These aspects of the deep channel serve to reduce noise and allow the transistor to operate in a more repeatable and predictable manner, among other things.

Abstract: A method for manufacturing a silicon carbide semiconductor device includes the steps of: forming a trench mask on an upper surface of a semiconductor substrate; forming the trench such that the trench having an aspect ratio equal to or larger than 2 and having a trench slanting angle equal to or larger than 80 degrees is formed; and removing a damage portion in such a manner that the damage portion disposed on an inner surface of the trench formed in the semiconductor substrate in the step of forming the trench is etched and removed in hydrogen atmosphere under decompression pressure at a temperature equal to or higher than 1600° C.

Abstract: The present invention is directed toward field effect transistors (FETs) and thin film transistors (TFTs) comprising carbon nanotubes (CNTs) and to methods of making such devices using solution-based processing techniques, wherein the CNTs within such devices have been fractionated so as to be concentrated in semiconducting CNTs. Additionally, the relatively low-temperature solution-based processing achievable with the methods of the present invention permit the use of plastics in the fabricated devices.

Abstract: In a semiconductor device having a multi-bridge-channel, and a method for fabricating the same, the device includes first and second semiconductor posts protruding from a surface of a semiconductor substrate and having a source and a drain region, respectively, in upper side portions thereof, channel semiconductor layers connecting upper side portions of the first and second semiconductor posts, a gate insulation layer on the channel semiconductor layers and the semiconductor substrate, the gate insulation layer surrounding at least a portion of the channel semiconductor layers, a gate electrode layer on the gate insulation layer to enclose at least a portion of a region between the channel semiconductor layers, and junction auxiliary layers formed between the channel semiconductor layers, the junction auxiliary layers contacting the gate electrode layer and upper side portions of the first and second semiconductor posts, and having a same width as the channel semiconductor layers.

Abstract: A normally off JFET is formed by the implantation of a P base; and a shallower P island atop the P base, forming a narrow lateral conduction channel between the two and a shallow gate implant in the device top surface which forms a second lateral conduction channel with the island. The two channels are each less than 0.5 microns thick and have an impurity concentration such that the channels are depleted at zero gate voltage and are turned on when the gate is forward biased. The gate surrounds a source implant region and a remote drain is provided which is connected to the top surface of the device for a lateral JFET or the bottom of the device for a vertical conduction JFET.

Abstract: A silicon carbide semiconductor device that includes J-FETs has a drift layer of epitaxially grown silicon carbide having a lower impurity concentration level than a substrate on which the drift layer is formed. Trenches are formed in the surface of the drift layer, and first gate areas are formed on inner walls of the trenches. Second gate areas are formed in isolation from the first gate areas. A source area is formed on channel areas, which are located between the first and second gate areas in the drift layer. A method of manufacturing the device ensures uniform channel layer quality, which allows the device to have a normally-off characteristic, small size, and a low likelihood of defects.

Abstract: A method for fabricating a spacer structure includes: forming a gate insulation layer having a gate deposition-inhibiting layer, a gate layer and a covering deposition-inhibiting layer on a semiconductor substrate, and patterning the gate layer and the covering deposition-inhibiting layer in order to form gate stacks. An insulation layer is deposited selectively using the deposition-inhibiting layers, thereby permitting highly accurate formation of the spacer structure.

Abstract: A semiconductor device which is capable of operating with a single positive power supply and has a low gate resistance, and a process for production thereof. The semiconductor device includes a channel layer (which constitutes a current channel), a first semiconductor layer formed on said channel layer, a second semiconductor layer in an island-like shape doped with a conductive impurity and formed on said first semiconductor layer, and a gate electrode formed on said second semiconductor layer, wherein said first and second semiconductor layers under said gate electrode have a conductive impurity region formed therein to control the threshold value of current flowing through said channel layer, and the conductive impurity region formed in second semiconductor layer is doped with a conductive impurity more heavily than in the conductive impurity region formed in said first semiconductor layer.

Abstract: A power metal oxide semiconductor transistor layout is disclosed. The power metal oxide semiconductor transistor layout uses network of conductive lead line as a connection or a network connection to connect source and drain regions thereby achieves advantages of a high uniformity of current, low Rds_on, much less power loss, an actual line density two times larger than that of conventional layouts and a strengthened resistance to electron migration.

Abstract: In one embodiment, a method for fabricating a compound semiconductor vertical FET device includes forming a first trench in a body of semiconductor material, and forming a self-aligned second trench within the first trench to define a channel region. A doped gate region is then formed on the sidewalls and the bottom surface of the second trench. Source regions are formed on opposite sides of the trench structure. Localized gate contact regions couple individual doped gate regions together. Contacts are then formed to the localized gate contact regions, the source regions, and an opposing surface of the body of semiconductor material. The method provides a compound semiconductor vertical FET structure having enhanced blocking capability.

Abstract: To provide a semiconductor device that permits free setting of characteristics of individual semiconductor elements which are mixedly mounted and have different characteristics, and is free of steps between formed semiconductor elements, in a manufacturing method for the semiconductor device, an n-type silicon layer is deposited on a p-type silicon substrate by epitaxial growth, and then an SOI layer is deposited thereon through the intermediary of a BOX layer. A junction transistor using a part of the n-type silicon layer as a channel region and a MOS transistor using the SOI layer are produced.

Abstract: JFET and MESFET structures, and processes of making same, for low voltage, high current and high frequency applications. The structures may be used in normally-on (e.g., depletion mode) or normally-off modes. The structures include an oxide layer positioned under the gate region which effectively reduces the junction capacitance (gate to drain) of the structure. For normally off modes, the structures reduce gate current at Vg in forward bias. In one embodiment, a silicide is positioned in part of the gate to reduce gate resistance. The structures are also characterized in that they have a thin gate due to the dipping of the spacer oxide, which can be below 1000 angstroms and this results in fast switching speeds for high frequency applications.

Abstract: A method for fabricating a junction field effect transistor (JFET) with a double dose gate structure. A trench is etched in the surface of a semiconductor substrate, followed by a low dose implant to form a first gate region. An anneal may or may not be performed after the low dose implant. A gate definition spacer is then formed on the wall the trench to establish the lateral extent of a second, high dose implant gate region. After the second implant, the gate is annealed. The double dose gate structure produced by the superposition of two different and overlapping regions provides an additional degree of flexibility in determining the ultimate gate region doping profile. A further step comprises using the gate definition spacer to define the walls of a second etched trench that is used to remove a portion of the p-n junction, thereby further reducing the junction capacitance.

Abstract: The invention provides a method of manufacturing a fin-type field effect transistor (FinFET) that forms a unique FinFET that has a first fin with a central channel region and source and drain regions adjacent the channel region, a gate intersecting the first fin and covering the channel region, and a second fin having only a channel region.

Abstract: Silicon carbide semiconductor devices and methods of fabricating silicon carbide semiconductor devices have a silicon carbide DMOSFET and an integral silicon carbide Schottky diode configured to at least partially bypass a built in diode of the DMOSFET. The Schottky diode may be a junction barrier Schottky diode and may have a turn-on voltage lower than a turn-on voltage of a built-in body diode of the DMOSFET. The Schottky diode may have an active area less than an active area of the DMOSFET.

Abstract: A power control system (25) uses two separate currents to control a startup operation of the power control system (25). The two currents are shunted to ground to inhibit operation of the power control system (25) and one of the two currents is disabled to minimize power dissipation. The two independently controlled currents are generated by a multiple output current high voltage device (12) responsively to two separate control signals (23, 24).

Abstract: The invention concerns a low-capacity vertical diode designed to be mounted by a front surface made in a semiconductor substrate (1), comprising a first zone projecting relative to the surface of the substrate including at least a semiconductor layer (3) doped with a type of conductivity opposite to that of the substrate, the upper surface of the semiconductor layer bearing a first solder bump (23). The diode comprises a second zone including on the substrate a thick strip conductor (16) bearing at least second solder bumps (24), said first and second solder bumps defining a plane parallel to the substrate plane.

Abstract: JFET and MESFET structures, and processes of making same, for low voltage, high current and high frequency applications. The structures may be used in normally-on (e.g., depletion mode) or normally-off modes. The structures include an oxide layer positioned under the gate region which effectively reduces the junction capacitance (gate to drain) of the structure. For normally off modes, the structures reduce gate current at Vg in forward bias. In one embodiment, a silicide is positioned in part of the gate to reduce gate resistance. The structures are also characterized in that they have a thin gate due to the dipping of the spacer oxide, which can be below 1000 angstroms and this results in fast switching speeds for high frequency applications.

Abstract: A process to make a low voltage (under 200 volts) superjunction device employs spaced P type implants into the generally central depth region of an epitaxially formed N layer. The wafer is then placed in a diffusion furnace and the spaced implants are driven upward and downward by 4 to 8 microns to form spaced P pylons in an N type epitaxial body. MOSgated structures are then formed atop each of the P pedestals. The total P charge of each pedestal is at least partially matched to the total N charge of the surrounding epitaxial material. The initial implant may be sandwiched between two discrete epitaxial layers.

Abstract: Various circuit devices incorporating junction-traversing dislocation regions and methods of making the same are provided. In one aspect, a method of processing is provided that includes forming an impurity region in a device region of a semiconductor-on-insulator substrate. The impurity region defines a junction. A dislocation region is formed in the device region that traverses the junction. The dislocation region provides a pathway to neutralize charge lingering in a floating body of a device.

Abstract: A new gate-controlled, negative resistance diode device is achieved. The device comprises, first, a semiconductor layer in a substrate. The semiconductor layer contains an emitter region and a barrier region. The barrier region is in contact with the emitter region and is laterally adjacent to the emitter region. The semiconductor layer contains a collector region. A drift region comprises the semiconductor layer between the barrier region and the collector region. Finally, a gate comprises a conductor layer overlying the drift region, the barrier region, and at least a part of the emitter region with an insulating layer therebetween. A method of manufacture is achieved.

Abstract: An apparatus and method for a semiconductor device with reduced gate capacitance. Specifically, an n-channel or p-channel junction field effect transistor (JFET) is described including an appropriately doped substrate forming a drain region, an epitaxial layer formed on top of the substrate, a control structure including a gate region implanted into the epitaxial layer, a source region sharing a p-n junction with the gate region, and an altered epitaxial region. The altered epitaxial region is formed by implanting either n− or p− dopants directly below the gate region of either the n-channel or p-channel JFET for widening a depletion region surrounding the gate region. The enlarged depletion region reduces the gate capacitance of the JFET between the gate and drain regions.

Abstract: Insulated gate field effect transistors having gate electrodes with at least two layers of materials provide gate electrode work function values that are similar to those of doped polysilicon, eliminate the poly depletion effect and also substantially prevent impurity diffusion into the gate dielectric. Bi-layer stacks of relatively thick Al and thin TiN for n-channel FETs and bi-layer stacks of relatively thick Pd and thin TiN, or relatively thick Pd and thin TaN for p-channel FETs are disclosed. Varying the thickness of the thin TiN or TaN layers between a first and second critical thickness may be used to modulate the work function of the gate electrode and thereby obtain the desired trade-off between channel doping and drive currents in FETs.

Abstract: A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state resistance.

Abstract: A method for making a high voltage insulated gate field-effect transistor with multiple JFET conduction channels comprises successively implanting a dopant of a first conductivity type in a first substrate of a second conductivity type so as to form a first plurality of buried layers disposed at a different vertical depths. The first substrate is flipped over and then bonded to a second substrate of the first conductivity type. After the first substrate has been thinned, another set of implants are successively performed so as to form a second plurality of buried layers in stacked parallel relationship to the first plurality of buried layers.

Abstract: A high frequency semiconductor device includes a ground plate, an insulating layer, a power-supply conductor, an insulating interlayer, and a strip line as a line conductor. The power-supply conductor is disposed above the ground plate, with the insulating layer provided therebetween. The ground plate and the power-supply conductor have a capacitance formed therebetween. Thus, the line conductor regards the power-supply conductor as having a potential identical to that of the ground plate. This makes it possible to lay out the line conductor without considering the arrangement of the power-supply conductor. In other words, by two-dimensionally overlapping a microstrip line and a power-supply conductor in an MMIC, the degree of freedom in the device layout can be increased.

Abstract: This invention provides a structure and method for improved transmission line operation on integrated circuits. One method of the invention includes forming transmission lines in an integrated circuit. The method includes forming a first layer of electrically conductive material on a substrate. A first layer of insulating material is formed on the first layer of the electrically conductive material. A pair of high permeability metal lines are formed on the first layer of insulating material. The pair of high permeability metal lines include composite hexaferrite films. A transmission line is formed on the first layer of insulating material and between and parallel with the pair of high permeability metal lines. A second layer of insulating material is formed on the transmission line and the pair of high permeability metal lines. And, the method includes forming a second layer of electrically conductive material on the second layer of insulating material.

Abstract: This invention provides a structure and method for improved transmission line operation on integrated circuits. One method of the invention includes forming transmission lines in an integrated circuit. The method includes forming a first layer of electrically conductive material on a substrate. A first layer of insulating material is formed on the first layer of the electrically conductive material. A pair of high permeability metal lines are formed on the first layer of insulating material. The pair of high permeability metal lines include composite hexaferrite films. A transmission line is formed on the first layer of insulating material and between and parallel with the pair of high permeability metal lines. A second layer of insulating material is formed on the transmission line and the pair of high permeability metal lines. And, the method includes forming a second layer of electrically conductive material on the second layer of insulating material.

Abstract: This invention provides a structure and method for improved transmission line operation on integrated circuits. One method of the invention includes forming transmission lines in an integrated circuit. The method includes forming a first layer of electrically conductive material on a substrate. A first layer of insulating material is formed on the first layer of the electrically conductive material. A pair of high permeability metal lines are formed on the first layer of insulating material. The pair of high permeability metal lines include composite hexaferrite films. A transmission line is formed on the first layer of insulating material and between and parallel with the pair of high permeability metal lines. A second layer of insulating material is formed on the transmission line and the pair of high permeability metal lines. And, the method includes forming a second layer of electrically conductive material on the second layer of insulating material.

Abstract: This invention provides a structure and method for improved transmission line operation on integrated circuits. One method of the invention includes forming transmission lines in an integrated circuit. The method includes forming a first layer of electrically conductive material on a substrate. A first layer of insulating material is formed on the first layer of the electrically conductive material. A pair of high permeability metal lines are formed on the first layer of insulating material. The pair of high permeability metal lines include composite hexaferrite films. A transmission line is formed on the first layer of insulating material and between and parallel with the pair of high permeability metal lines. A second layer of insulating material is formed on the transmission line and the pair of high permeability metal lines. And, the method includes forming a second layer of electrically conductive material on the second layer of insulating material.

Abstract: This invention provides a structure and method for improved transmission line operation on integrated circuits. One method of the invention includes forming transmission lines in an integrated circuit. The method includes forming a first layer of electrically conductive material on a substrate. A first layer of insulating material is formed on the first layer of the electrically conductive material. A pair of high permeability metal lines are formed on the first layer of insulating material. The pair of high permeability metal lines include composite hexaferrite films. A transmission line is formed on the first layer of insulating material and between and parallel with the pair of high permeability metal lines. A second layer of insulating material is formed on the transmission line and the pair of high permeability metal lines. And, the method includes forming a second layer of electrically conductive material on the second layer of insulating material.

Abstract: This invention provides a structure and method for improved transmission line operation on integrated circuits. One method of the invention includes forming transmission lines in an integrated circuit. The method includes forming a first layer of electrically conductive material on a substrate. A first layer of insulating material is formed on the first layer of the electrically conductive material. A pair of high permeability metal lines are formed on the first layer of insulating material. The pair of high permeability metal lines include composite hexaferrite films. A transmission line is formed on the first layer of insulating material and between and parallel with the pair of high permeability metal lines. A second layer of insulating material is formed on the transmission line and the pair of high permeability metal lines. And, the method includes forming a second layer of electrically conductive material on the second layer of insulating material.

Abstract: A method of forming a thin, high-quality relaxed SiGe-on-insulator substrate material is provided which first includes forming a SiGe or pure Ge layer on a surface of a first single crystal Si layer which is present atop a barrier layer that is resistant to the diffusion of Ge. Optionally forming a Si cap layer over the SiGe or pure Ge layer, and thereafter heating the various layers at a temperature which permits interdiffusion of Ge throughout the first single crystal Si layer, the optional Si cap and the SiGe or pure Ge layer thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer. Additional SiGe regrowth and/or formation of a strained epi-Si layer may follow the above steps. SiGe-on-insulator substrate materials as well as structures including at least the SiGe-on-insulator substrate materials are also disclosed herein.

Abstract: The present invention relates to a method for reducing low-frequency noise in a cooled circuit wherein low-frequency noise in a cryogenic semiconductor device is reduced by carrying out thermal cure. The semiconductor device is turned on at a first temperature, and the temperature of the semiconductor device is temporarily raised, while flowing current in the semiconductor device, to a second temperature that is higher than the first temperature, and then cooling the temperature of the semiconductor device from the second temperature to a cryogenic temperature, at which the semiconductor device can operate.

Abstract: Semiconductor structures are provided with high quality epitaxial layers of monocrystalline materials grown over monocrystalline substrates such as large silicon wafers utilizing a compliant substrate. One way to achieve the formation of a compliant substrate includes first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and an overlying monocrystalline material layer. With laser assisted fabrication, a laser energy source is used to preclean the accommodating buffer layer, to excite the accommodating buffer layer to higher energy to promote two-dimensional growth, and to amorphize the accommodating buffer layer, without requiring transport of the semiconductor structure from one environment to another. When chemical vapor deposition is utilized, the laser radiation source can also be employed to crack volatile chemical precursors and to enable selective deposition.

Abstract: A method for making a high voltage insulated gate field-effect transistor with one or more JFET conduction channels comprises successively implanting a dopant of a first conductivity type in a first epitaxial layer of a second conductivity type so as to form a first plurality of buried layers disposed at a different vertical depths. A second epitaxial layer is formed on the first epitaxial layer and the implant process repeated to form a second plurality of buried layers in stacked parallel relationship to the first plurality of buried layers. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: A method for manufacturing an integrated circuit structure is disclosed. The method includes providing a layer of porous silicon, and epitaxially growing a high resistivity layer on the layer of porous silicon. Devices are then formed on the high resistivity layer to produce the integrated circuit structure. The integrated circuit structure is attached to a silica substrate, such that the silica substrate is coupled to the devices. Further, surface contacts are provided on the structure. The layer of porous silicon is then removed.

Abstract: A process for integrating the fabrication of an N type, junction field effect transistor (NJFET), device, with the fabrication and a high voltage, P channel metal oxide semiconductor (PMOS), device, has been developed. The process includes the formation of a deep N well region for accommodation of the high voltage, PMOS device, while a shallow N well region is used to contain the NJFET device. Featured in the integrated fabrication sequence is the simultaneous formation of P type source/drain regions for the high voltage PMOS device, and the P type gate structure of the NJFET device.

Abstract: This invention discloses the present invention discloses a junction field effect transistor (JFET) device supported on a substrate. The JFET device includes a gate surrounded by a depletion region. As the distance between the gates is large enough, there is a gap between the depletion regions surrounding adjacent gates. Depletion mode JFET transistor which is normally on is provided. The normally on transistors respond to negative bias applied to the gates to shut of the current path in the substrate. The current path in the substrate is normally available with a zero gate bias. As the distance between the gates is reduced, the JFET transistor is normally off because the depletion regions surround the gates shut of the current channel. The depletion region responding to a positive bias applied to the gate to open a current path in the substrate wherein the current path in the substrate is shut off when the gate is zero biased.

Abstract: A method for making a high voltage insulated gate field-effect transistor with multiple JFET conduction channels comprises successively implanting a dopant of a first conductivity type in a first substrate of a second conductivity type so as to form a first plurality of buried layers disposed at a different vertical depths. The first substrate is flipped over and then bonded to a second substrate of the first conductivity type. After the first substrate has been thinned, another set of implants are successively performed so as to form a second plurality of buried layers in stacked parallel relationship to the first plurality of buried layers.

Abstract: A high frequency semiconductor device includes a ground plate, an insulating layer, a power-supply conductor, an insulating interlayer, and a strip line as a line conductor. The power-supply conductor is disposed above the ground plate, with the insulating layer provided therebetween. The ground plate and the power-supply conductor have a capacitance formed therebetween. Thus, the line conductor regards the power-supply conductor as having a potential identical to that of the ground plate. This makes it possible to lay out the line conductor without considering the arrangement of the power-supply conductor. In other words, by two-dimensionally overlapping a microstrip line and a power-supply conductor in an MMIC, the degree of freedom in the device layout can be increased.

Abstract: A gate structure is patterned on a substrate. An ion implantation is performed to form the LDD. Then, a thin liner layer is deposited on the feature of the substrate. A disposable spacer is successively formed attached on the side of the linear layer. The source and drain is next created in the substrate by ion implantation. The disposable spacer is then stripped by wet dip technique. A borderless layer is formed on the surface of the linear layer. A dielectric layer is formed on the gate structure and the dielectric layer can be composed of silicon dioxide, BPSG, SOG. Then, a photoresist is patterned on the dielectric layer to define the contact hole.

Abstract: An integrated circuit is composed of a substrate, a first conductor formed on the substrate, an insulating film formed on the first conductor and the substrate, a second conductor formed on the insulating film, a first interconnection formed in the insulating film and a second interconnection formed on the insulating film. The first conductor and the second conductor constitute a pair of transmission lines. The first interconnection and the second interconnection constitute a circuit. The pair of transmission lines and the circuit are separated such that the circuit does not substantially interfere electrically with the pair of transmission lines.

Abstract: The present invention relates a method of forming a gate electrode in semiconductor devices by which given regions of the hard mask layer, the tungsten film and the tungsten nitride film, and a given thickness of the polysilicon film are etched to form the spacer at the sidewall of the first pattern, a spacer is formed at the sidewall of the first pattern and the remaining polysilicon film and gate oxide film are etched using the first pattern at the sidewall of which the spacer is formed as a mask to form a dual gate electrode. Therefore. the present invention can prevent oxidization of a tungsten film without implementing a selective oxidization process. Further, the present invention can prevent intrusion of boron ions implanted into a polysilicon film into a gate oxide film by not performing the selective oxidization process.

Abstract: A process is provided for manufacturing a semiconductor device. A lower polycrystalline silicon layer is deposited on a substrate surface and on one or more structures that protrude from the substrate surface. A dielectric layer is formed on the lower polycrystalline silicon layer. An upper polycrystalline silicon layer is deposited on the dielectric layer. The upper polycrystalline silicon layer is patterned to form one or more upper capacitor plates. Next, the exposed portions of the dielectric layer not covered by the one or more upper capacitor plates are removed. After the steps of patterning the upper polycrystalline silicon area and removing the exposed portions of the dielectric layer, the lower polycrystalline silicon layer is patterned to form at least one or more lower capacitor plates. Each lower capacitor plate underlies a corresponding one of the upper capacitor plates and a portion of the dielectric layer covered by the corresponding upper capacitor plate.

Abstract: The new fluorocarbon-functionalized polythiophenes, in particular, &agr;,&ohgr;-diperfluorohexylsexithiophene DFH-6T (1) can be straightforwardly prepared in high yield and purified by gradient sublimation. Introduction of perfluorocarbon chains on the thiophene core affords enhanced thermal stability and volatility, and increased electron affinity versus the fluorine-free analog 2. Evaporated films of 1, for example, behave as n-type semiconductors, and can be used to fabricate thin film transistors with FET mobilities on the order of ˜0.01 cm2/Vs—some of the highest reported to date for n-type organic semiconductors.

Abstract: An electropolishing process for high resolution patterning of noble metals, such as platinum, for forming various semiconductor devices, such as capacitors or wiring patterns is disclosed.

Abstract: The present invention provides a method for manufacturing a semiconductor device having a junction area formed by doping with a first conductive and a second conductive dopant. According to the method of the present invention, a surface of the semiconductor device is irradiated by electron beams or charged particles having energy of 100 to 500 keV. After the irradiation by electron beams or charged particles, annealing in a hydrogen atmosphere is performed for the irradiated semiconductor device.

Abstract: A semiconductor device efficiently providing the DC currents required in both discrete and integrated circuits operated at low DC supply voltages. The device disclosed in the present invention is an asymmetrical, enhancement mode, Junction Field Effect Transistor (JFET). The device consists of an epitaxial layer on the surface of a substrate, both of which are doped with the same polarity. The epitaxial layer has a graded doping profile with doping density increasing with distance from the substrate. A grill-like structure is constructed within the upper and lower bounds of, and extending throughout the length and width of the epitaxial layer, and is doped with a polarity opposite to that of the epitaxial layer. A first electrical connection made to the exposed side of the substrate is defined as the drain electrode. A second electrical connection made to the exposed surface of the epitaxial layer is defined as the source electrode.

Abstract: A method for forming and using silicide test structures to monitor and evaluate the quality of a semiconductive junction after the formation of a silicide layer over the junction is described. Two specially designed test structures are formed for in-line testing in the kerf of an integrated circuit wafer. The test structures comprise a silicide region formed over a diffusion region which is formed concurrently with diffusion and silicide regions which form contacts of the integrated circuit dice. The test structures are fitted with probe pads connected to semiconductive element of the junction region. A first structure is designed to measure bulk junction leakages, has the silicide contact layer spaced away from the junction edge. A second structure, designed to measure edge related junction leakage phenomena, has a serpentine edge to which the silicide layer extends and a plurality of interior openings which serve as EMMI windows.