Vertical Channel Insulated Gate Field Effect Transistor Patents (Class 438/206)
  • Patent number: 10002962
    Abstract: Techniques relate to forming a vertical field effect transistor (FET). One or more fins are formed on a bottom source or drain of a substrate, and one or more fins extend in a vertical direction. Gate material is formed to be positioned on sides of the one or more fins. Gate encapsulation material is formed on sides of the gate material to form a trench, such that top portions of the one or more fins are exposed in the trench. A top source or drain is formed on top of the one or more fins such that the top source or drain is laterally confined by the trench in a lateral direction that is parallel to the one or more fins.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: June 19, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent A. Anderson, Huiming Bu, Fee Li Lie, Edward J. Nowak, Junli Wang
  • Patent number: 9673199
    Abstract: A method of gate cutting for a device with multiple vertical transistors is provided. The method includes memorizing an initial structure of the device to identify a location for a gate strap to connect a portion of the multiple vertical transistors, building a bilayer hard mask over the device with a photoresist (PR) opening at the location, removing successive layers of the bilayer hard mask to identify first and second sections of the device based on a position of the PR opening and removing remaining layers of the bilayer hard mask and the first section of the device while preserving the second section of the device to form the gate strap.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: June 6, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent A. Anderson, Sivananda K. Kanakasabapathy, Stuart A. Sieg, John R. Sporre, Junli Wang
  • Patent number: 9620291
    Abstract: A thin film capacitor including a lower electrode layer, a dielectric layer provided on the lower electrode layer, and an upper electrode layer formed on the dielectric layer, wherein the dielectric layer includes a recessed portion in a portion on the upper face thereof, a cross-sectional structure perpendicular to the dielectric layer of the recessed portion has a cross-sectional taper angle of 1 degree or more and 25 degrees or less, and the distance between the bottom portion center and an outermost portion of the recessed portion is 20 times or more and 150 times or less a thickness of the dielectric layer.
    Type: Grant
    Filed: July 14, 2015
    Date of Patent: April 11, 2017
    Assignee: TDK CORPORATION
    Inventors: Junji Aotani, Shigeaki Tanaka, Katsuyuki Kurachi, Tatsuo Namikawa, Yuuki Aburakawa
  • Patent number: 9543434
    Abstract: A device including a drain, a channel, and a gate. The channel surrounds the drain and has a channel length to width ratio. The gate is situated over the channel to provide an active channel region that has an active channel region length to width ratio that is greater than the channel length to width ratio.
    Type: Grant
    Filed: May 19, 2011
    Date of Patent: January 10, 2017
    Assignee: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventor: Trudy Benjamín
  • Patent number: 9543411
    Abstract: A lateral double diffusion metal-oxide-semiconductor (LDMOS) transistor is provided. The LDMOS transistor includes a semiconductor substrate having a well region and a drain region in the well region. The LDMOS transistor also includes at least one drifting region in the well region and an annular source region in the drifting region surrounding the drain region. Further, the LDMOS transistor includes at least one annular isolation structure surrounding the drain region in the drifting region. Further, the LDMOS transistor also includes an annular gate dielectric layer on the well region and an annular gate on the annular gate dielectric layer.
    Type: Grant
    Filed: October 23, 2013
    Date of Patent: January 10, 2017
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Jian Xiang Cai, Juilin Lu, Ty Chiu
  • Patent number: 9252134
    Abstract: An Integrated Circuit device, including: a base wafer including single crystal, the base wafer including a plurality of first transistors; at least one metal layer providing interconnection between the plurality of first transistors; a second layer including a plurality of second transistors, the second layer overlying the at least one metal layer, where the plurality of second transistors include single crystal, and where the second layer includes a through layer via with a diameter of less than 250 nm; a plurality of conductive pads, where at least one of the conductive pads overlays at least one of the second transistors; and at least one I/O circuit, where the at least one I/O circuit is adapted to interface with external devices through at least one of the plurality of conductive pads, where the at least one I/O circuit includes at least one of the first transistors.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: February 2, 2016
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Brian Cronquist
  • Patent number: 9153687
    Abstract: A semiconductor device includes a plurality of epitaxial layers stacked over a supportive substrate, a first buried impurity region formed to share the supportive substrate with a lowermost epitaxial layer among the multiple epitaxial layers, one or more second buried impurity regions formed to be coupled with the first buried impurity region and share an Nth epitaxial layer and an (N+1)th epitaxial layer among the multiple epitaxial layers, where N is a natural number, a body region formed in an uppermost epitaxial layer among the multiple epitaxial layers and a deep well formed in the uppermost epitaxial layer to surround the body region and to be coupled with the second buried impurity regions that share the uppermost epitaxial layer.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: October 6, 2015
    Assignee: SK Hynix Inc.
    Inventors: Kwang-Sik Ko, Kuem-Ju Lee, Joo-Won Park
  • Patent number: 9117687
    Abstract: An integrated circuit containing a first plurality of MOS transistors operating in a low voltage range, and a second plurality of MOS transistors operating in a mid voltage range, may also include a high-voltage MOS transistor which operates in a third voltage range significantly higher than the low and mid voltage ranges, for example 20 to 30 volts. The high-voltage MOS transistor has a closed loop configuration, in which a drain region is surrounded by a gate, which is in turn surrounded by a source region, so that the gate does not overlap field oxide. The integrated circuit may include an n-channel version of the high-voltage MOS transistor and/or a p-channel version of the high-voltage MOS transistor. Implanted regions of the n-channel version and the p-channel version are formed concurrently with implanted regions in the first and second pluralities of MOS transistors.
    Type: Grant
    Filed: October 29, 2012
    Date of Patent: August 25, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Binghua Hu, Pinghai Hao, Sameer Pendharkar, Seetharaman Sridhar, Jarvis Jacobs
  • Patent number: 9093304
    Abstract: The present invention is a semiconductor device comprising a semiconducting low doped vertical super-thin body (VSTB) formed on Dielectric Body Wall (such as STI-wall as isolating substrate) having the body connection to bulk semiconductor wafer on the bottom side, isolation on the top side, and the channel, gate dielectric, and gate electrode on opposite to STI side surface. The body is made self-aligned to STI hard mask edge allowing tight control of body thickness. Source and Drain are made by etching holes vertically in STI at STI side of the body and filling with high doped crystalline or poly-Si appropriately doped with any appropriate silicides/metal contacts or with Schottky barrier Source/Drain. Gate first or Gate last approaches can be implemented. Many devices can be fabricated in single active area with body isolation between the devices by iso-plugs combined with gate electrode isolation by iso-trenches.
    Type: Grant
    Filed: July 11, 2013
    Date of Patent: July 28, 2015
    Assignee: Finscale Inc.
    Inventors: Viktor Koldiaev, Rimma Pirogova
  • Patent number: 9018702
    Abstract: A semiconductor device according an aspect of the present disclosure may include an isolation layer formed within a substrate and formed to define an active region, a junction formed in the active region, well regions formed under the isolation layer, and a plug embedded within the substrate between the junction and the well regions and formed extend to a greater depth than the well regions.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: April 28, 2015
    Assignee: SK Hynix Inc.
    Inventor: Wan Cheul Shin
  • Patent number: 9006067
    Abstract: A method of fabricating a semiconductor device includes forming first gate patterns on a semiconductor substrate using an etch mask pattern, forming a trench in the semiconductor substrate between the first gate patterns, forming an insulating layer in the trench, such that the insulating layer fills the trench and is disposed on the etch mask pattern, planarizing the insulating layer until a top surface of the etch mask pattern is exposed, etching a portion of the planarized insulating layer to form a device isolation layer in the trench, forming a second gate layer covering the etch mask pattern and disposed on the device isolation pattern, and planarizing the second gate layer until the top surface of the etch mask pattern is exposed, such that a second gate pattern is formed.
    Type: Grant
    Filed: January 2, 2014
    Date of Patent: April 14, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bo Kyeong Kang, Jaeseok Kim, Boun Yoon, Hoyoung Kim, Ilyoung Yoon
  • Patent number: 8962425
    Abstract: A semiconductor device has a substrate and trench formed partially through the substrate. A drain region is formed in the substrate as a second surface of the substrate. An epitaxial region is formed in the substrate over the drain region. A vertical drift region is formed along a sidewall of the trench. An insulating material is deposited within the trench. A channel region is formed along the sidewall of the trench above the insulating material. The channel region is separated from the insulating material. A gate structure is formed within the trench adjacent to the channel region. The gate structure includes an insulating layer formed along the sidewall of the trench adjacent to the channel region and polysilicon layer formed within the trench over the insulating layer. A source region is formed in a first surface of the substrate contacting the channel region.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: February 24, 2015
    Assignee: Great Wall Semiconductor Corporation
    Inventors: Zheng John Shen, Patrick M. Shea, David N. Okada
  • Patent number: 8883587
    Abstract: A method of manufacturing a semiconductor device includes forming silicon line patterns in a semiconductor substrate, forming an insulating layer over the silicon line patterns, forming a conductive pattern between the silicon line patterns, forming a spacer over the substrate, forming an interlayer insulating layer between the silicon line patterns, removing the spacer on one side of the silicon line patterns to expose the conductive pattern, forming a bit line contact open region by removing the interlayer insulating layer, forming a polysilicon pattern to cover the bit line contact open region, and forming a junction region diffused to the silicon line pattern through the bit line contact open region. Thereby, a stacked structure of a titanium layer and a polysilicon layer are stably formed when forming a buried bit line and a bit line contact is formed using diffusion of the polysilicon layer to prevent leakage current.
    Type: Grant
    Filed: July 20, 2011
    Date of Patent: November 11, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Seung Hwan Kim
  • Patent number: 8847327
    Abstract: A layout data creation device includes a transistor adjustment unit. The transistor adjustment unit divides a pillar-type transistor including a plurality of unit pillar-type transistors into the unit pillar-type transistors groups. The unit pillar-type transistors can be placed in a placement area. The number of the unit pillar-type transistors in each group is an integer. The transistor adjustment unit generates sub-pillar-type transistors that are placed in the placement area.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: September 30, 2014
    Assignee: PS4 Luxco S.A.R.L.
    Inventors: Shinji Kato, Kazuteru Ishizuka, Kiyotaka Endo, Mitsuki Koda
  • Patent number: 8829641
    Abstract: In one general aspect, a method of forming a field effect transistor can include forming a well region in a semiconductor region of a first conductivity type where the well region is of a second conductivity type and has an upper surface and a lower surface. The method can include forming a gate trench extending into the semiconductor region to a depth below a depth of the lower surface of the well region, and forming a stripe trench extending through the well region and into the semiconductor region to a depth below the depth of the gate trench. The method can also include forming a contiguous source region of the first conductivity type in the well region where the source region being in contact with the gate trench and in contact with the stripe trench.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: September 9, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Bruce D. Marchant
  • Patent number: 8791507
    Abstract: A layout of a semiconductor device is capable of reliably reducing a variation in gate length due to the optical proximity effect, and enables flexible layout design to be implemented. Gate patterns (G1, G2, G3) of a cell (C1) are arranged at the same pitch, and terminal ends (e1, e2, e3) of the gate patterns are located at the same position in the Y direction, and have the same width in the X direction. A gate pattern (G4) of a cell (C2) has protruding portions (4b) protruding toward the cell (C1) in the Y direction, and the protruding portions (4b) form opposing terminal ends (eo1, eo2, eo3). The opposing terminal ends (eo1, eo2, eo3) are arranged at the same pitch as the gate patterns (G1, G2, G3), are located at the same position in the Y direction, and have the same width in the X direction.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: July 29, 2014
    Assignee: Panasonic Corporation
    Inventors: Kazuyuki Nakanishi, Masaki Tamaru
  • Patent number: 8780099
    Abstract: An organic light emitting diode (OLED) display and a method of manufacturing the same are provided. The OLED display includes: a first substrate; a second substrate; a thin film transistor and a driving driver on the first substrate; an organic light emitting element including a pixel electrode, an organic emission layer, and a common electrode; a pixel defining layer; a thermal conductive layer covering the driving driver; and a first sealant along an outer edge of the first substrate and the second substrate.
    Type: Grant
    Filed: March 29, 2011
    Date of Patent: July 15, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventor: Jung-Mi Choi
  • Patent number: 8765609
    Abstract: A process for fabricating a tapered field plate dielectric for high-voltage semiconductor devices is disclosed. The process may include depositing a thin layer of oxide, depositing a polysilicon hard mask, depositing a resist layer and etching a trench area, performing deep silicon trench etch, and stripping the resist layer. The process may further include repeated steps of depositing a layer of oxide and anisotropic etching of the oxide to form a tapered wall within the trench. The process may further include depositing poly and performing further processing to form the semiconductor device.
    Type: Grant
    Filed: July 25, 2012
    Date of Patent: July 1, 2014
    Assignee: Power Integrations, Inc.
    Inventors: Vijay Parthasarathy, Sujit Banerjee, Wayne B. Grabowski
  • Patent number: 8753942
    Abstract: Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other.
    Type: Grant
    Filed: December 1, 2010
    Date of Patent: June 17, 2014
    Assignee: Intel Corporation
    Inventors: Kelin J. Kuhn, Seiyon Kim, Rafael Rios, Stephen M. Cea, Martin D. Giles, Annalisa Cappellani, Titash Rakshit, Peter Chang, Willy Rachmady
  • Patent number: 8748247
    Abstract: A method for fabricating a semiconductor structure includes providing a semiconductor substrate having a first region and a second region, and doping top of the semiconductor substrate to form a doped layer at top surface of the semiconductor substrate over the first region and the second region. The method also includes etching the doped layer to form a first sub-fin in the first region and a first sub-fin in the second region, and forming an insulating layer over the semiconductor substrate including the first sub-fin in the first region and the first sub-fin in the second region. Further, the method includes removing top portions of the first sub-fin in the first region and the first sub-fin in the second region and forming corresponding second sub-fins.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: June 10, 2014
    Assignee: Semiconductor Manufacturing International Corp
    Inventor: Mieno Fumitake
  • Patent number: 8735967
    Abstract: A semiconductor memory device includes a lower select transistor formed within a semiconductor substrate, memory cells stacked over the lower select transistors, and an upper select transistor formed over the memory cells.
    Type: Grant
    Filed: February 15, 2012
    Date of Patent: May 27, 2014
    Assignee: SK Hynix Inc.
    Inventors: Se Yun Lim, Eun Seok Choi
  • Patent number: 8679903
    Abstract: A method is provided for fabricating a vertical insulated gate transistor. A horizontal isolation region is formed in a substrate to separate and electrically isolate upper and lower portions of the substrate. A vertical semiconductor pillar with one or more flanks and a cavity is formed so as to rest on the upper portion, and a dielectrically isolated gate is formed so as to include an internal portion within the cavity and an external portion resting on the flanks and on the upper portion. One or more internal walls of the cavity are coated with an isolating layer and the cavity is filled with a gate material so as to form the internal portion of the gate within the cavity and the external portion of the gate that rests on the flanks, and to form two connecting semiconductor regions extending between source and drain regions of the transistor.
    Type: Grant
    Filed: July 27, 2007
    Date of Patent: March 25, 2014
    Assignee: STMicroelectronics, Inc.
    Inventor: Richard A. Blanchard
  • Patent number: 8643094
    Abstract: A method of forming a contact opening in a semiconductor substrate is presented. A plurality of trench gates each having a projecting portion are formed in a semiconductor substrate, and a stop layer is deposited over the semiconductor substrate extending over the projecting portions, wherein each portion of the stop layer along each of the sidewalls of the projecting portions is covered by a spacer. By removing the portions of the stop layer not covered by the spacers by utilizing a relatively higher etching selectivity of the stop layer to the spacers, the openings between adjacent projecting portions with an L-type shape on each sidewall can be formed, and a lithography process can be performed to form self-aligned contact openings thereafter.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: February 4, 2014
    Assignee: Sinopower Semiconductor, Inc.
    Inventors: Sung-Shan Tai, Teng-hao Yeh, Chia-Hui Chen
  • Patent number: 8633082
    Abstract: A method of fabrication of an analog, asymmetric Metal-Oxide-Semiconductor-Field-Effect-Transistor (MOSFET) is provided. The method may comprise forming a first gate oriented in a first direction over an active region of a semiconductor substrate, forming a second gate extending perpendicular to the first gate over a second active region, using a dual-directional implant process to form a reduced-HALO doped area on a drain side of the first gate and also for a HALO doped area for the second gate, while the source side of the first gate is covered by a resist. Additionally, the method may comprise forming a HALO doped area on the source side of the first gate using a quad-directional implant process using the mask also used for HALO implants of other digital-logic devices on the substrate, while the drain side of the gate is blocked by a resist.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: January 21, 2014
    Assignee: International Business Machines Corporation
    Inventors: Sebastien Lasserre, John J. Pekarik
  • Patent number: 8574974
    Abstract: Forming a photoresist on a region other than a region on a trench gate electrode for a mask, a third gate insulating film on the trench gate electrode is etched and removed. After that, a non-doped polycrystalline silicon layer is formed on second and third gate insulating films and also on the trench gate electrode, and, N-type and P-type high concentration impurities are introduced by an ion implantation with the use of separate masks on the polycrystalline silicon layer of NMOS transistors and PMOS transistors with a low breakdown voltage and a high breakdown voltage. Then, a second gate electrode is formed by anisotropic etching. With the steps as described above, a first gate electrode inside the trench and the second gate electrode to be used in the lateral MOS transistor are laminated, to thereby reduce fluctuations due to the etching.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: November 5, 2013
    Assignee: Seiko Instruments Inc.
    Inventor: Yukimasa Minami
  • Patent number: 8536004
    Abstract: A method for fabricating a semiconductor power device includes the following steps. First, a substrate having at least a semiconductor layer and a pad layer thereon is provided. At least a trench is etched into the pad layer and the semiconductor layer. Then, a dopant source layer is deposited in the trench and on the pad layer followed by thermally driving in dopants of the dopant source layer into the semiconductor layer. A polishing process is performed to remove the dopant source layer from a surface of the pad layer and a thermal oxidation process is performed to eliminate micro-scratches formed during the polishing process. Finally, the pad layer is removed to expose the semiconductor layer.
    Type: Grant
    Filed: August 17, 2011
    Date of Patent: September 17, 2013
    Assignee: Anpec Electronics Corporation
    Inventors: Yung-Fa Lin, Shou-Yi Hsu, Yi-Lin Sun
  • Patent number: 8536003
    Abstract: A method for fabricating a semiconductor power device includes the following steps. First, a substrate having thereon at least a semiconductor layer and a pad layer is provided. Then, at least a trench is etched into the pad layer and the semiconductor layer followed by depositing a dopant source layer in the trench and on the pad layer. A process is carried out thermally driving in dopants of the dopant source layer into the semiconductor layer. A rapid thermal process is performed to mend defects in the dopant source layer and defects between the dopant source layer and the semiconductor layer. Finally, a polishing process is performed to remove the dopant source layer from a surface of the pad layer.
    Type: Grant
    Filed: August 17, 2011
    Date of Patent: September 17, 2013
    Assignee: Anpec Electronics Corporation
    Inventors: Yung-Fa Lin, Shou-Yi Hsu, Yi-Lin Sun
  • Patent number: 8518769
    Abstract: A semiconductor device of an embodiment includes: an insulating film including: a first region extending in a first direction; second and third regions arranged at a distance from each other; and fourth and fifth regions each having a concave shape, the fourth and fifth regions each having a smaller film thickness than a film thickness of each of the first through third regions; a semiconductor layer formed in a direction from the fourth region toward the fifth region, the semiconductor layer having a smaller width than a width of each of source and drain regions, the semiconductor layer being connected to the source and drain regions; a gate electrode placed on the opposite side of a gate insulating film from the semiconductor layer on the first region; and a gate sidewall formed on a side face of the gate electrode.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: August 27, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kensuke Ota, Toshinori Numata, Masumi Saitoh, Chika Tanaka
  • Patent number: 8486784
    Abstract: A vertical semiconductor device with improved junction profile and a method of manufacturing the same are provided. The vertical semiconductor device includes a pillar vertically extended from a surface of a semiconductor substrate, a silicon layer formed in a bit line contact region of one sidewall of the pillar, and a junction region formed within a portion of the pillar contacting with the silicon layer.
    Type: Grant
    Filed: December 27, 2010
    Date of Patent: July 16, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Hyun Jung Kim
  • Patent number: 8482062
    Abstract: A semiconductor device includes a first trench and a second trench extending into a semiconductor body from a surface. A body region of a first conductivity type adjoins a first sidewall of the first trench and a first sidewall of the second trench, the body region including a channel portion adjoining to a source structure and being configured to be controlled in its conductivity by a gate structure. The channel portion is formed at the first sidewall of the second trench and is not formed at the first sidewall of the first trench. An electrically floating semiconductor zone of the first conductivity type adjoins the first trench and has a bottom side located deeper within the semiconductor body than the bottom side of the body region.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: July 9, 2013
    Assignee: Infineon Technologies Austria AG
    Inventors: Frank Pfirsch, Maria Cotorogea, Franz Hirler, Franz-Josef Niedernostheide, Thomas Raker, Hans-Joachim Schulze, Hans Peter Felsl
  • Patent number: 8470657
    Abstract: An ion implantation method for semiconductor sidewalls includes steps of: forming a trench on a substrate, and the trench having a lower reflecting layer and two sidewalls adjacent to a bottom section; performing a plasma doping procedure to sputter conductive ions to the lower reflecting layer and the conductive ions being rebounded from the lower reflecting layer to adhere to the sidewalls to respectively form an adhesion layer thereon; and performing an annealing procedure to diffuse the conductive ions of the adhesion layer into the substrate to form a conductive segment. Thus, without damaging the substrate, the conductive segment having a high conductive ion doping concentration is formed at a predetermined region to satisfy semiconductor design requirements.
    Type: Grant
    Filed: June 25, 2012
    Date of Patent: June 25, 2013
    Assignee: Rexchip Electronics Corporation
    Inventor: Chih-Hsin Lo
  • Patent number: 8445343
    Abstract: Methods of fabricating a semiconductor device include alternatingly and repeatedly stacking sacrificial layers and first insulating layers on a substrate, forming an opening penetrating the sacrificial layers and the first insulating layers, and forming a spacer on a sidewall of the opening, wherein a bottom surface of the opening is free of the spacer. A semiconductor layer is formed in the opening. Related devices are also disclosed.
    Type: Grant
    Filed: February 18, 2011
    Date of Patent: May 21, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung Ho Kim, Kihyun Hwang, Sangryol Yang, Yong-Hoon Sang, Ju-Eun Kim
  • Patent number: 8426277
    Abstract: A semiconductor process includes the following steps. A substrate is provided. At least a fin-shaped structure is formed on the substrate and an oxide layer is formed on the substrate without the fin-shaped structure forming thereon. A thermal treatment process is performed to form a melting layer on at least a part of the sidewall of the fin-shaped structure.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: April 23, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Chien-Liang Lin, Shih-Hung Tsai, Chun-Hsien Lin, Te-Lin Sun, Shao-Wei Wang, Ying-Wei Yen, Yu-Ren Wang
  • Patent number: 8409948
    Abstract: Some embodiments include methods of forming vertical transistors. A construction may have a plurality of spaced apart fins extending upwardly from a semiconductor substrate. Each of the fins may have vertical transistor pillars, and each of the vertical transistor pillars may have a bottom source/drain region location, a channel region location over the bottom source/drain region location, and a top source/drain region location over the channel region location. Electrically conductive gate material may be formed along the fins while using oxide within spaces along the bottoms of the fins to offset the electrically conductive gate material to be above the bottom source/drain region locations of the vertical transistor pillars. The oxide may be an oxide which etches at a rate of at least about 100 ?/minute with dilute HF at room temperature. In some embodiments the oxide may be removed after the electrically conductive gate material is formed.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: April 2, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Mark Fischer, Sanh D. Tang
  • Patent number: 8399319
    Abstract: A semiconductor device includes a substrate and a plurality of unit cells vertically arranged on the substrate.
    Type: Grant
    Filed: July 19, 2010
    Date of Patent: March 19, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sang Soo Lee
  • Patent number: 8395208
    Abstract: It is an object to provide an SGT production method capable of obtaining a structure for reducing a resistance of a gate, a desired gate length, desired source and drain configurations and a desired diameter of a pillar-shaped semiconductor.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: March 12, 2013
    Assignee: Unisantis Electronics Singapore Pte Ltd.
    Inventors: Fujio Masuoka, Shintaro Arai, Hiroki Nakamura, Tomohiko Kudo
  • Patent number: 8372708
    Abstract: This invention discloses a semiconductor power device. The trenched semiconductor power device includes a trenched gate, opened from a top surface of a semiconductor substrate, surrounded by a source region encompassed in a body region near the top surface above a drain region disposed on a bottom surface of a substrate. The semiconductor power device further includes an implanting-ion block disposed above the top surface on a mesa area next to the body region having a thickness substantially larger than 0.3 micron for blocking body implanting ions and source ions from entering into the substrate under the mesa area whereby masks for manufacturing the semiconductor power device can be reduced.
    Type: Grant
    Filed: October 4, 2011
    Date of Patent: February 12, 2013
    Inventors: Anup Bhalla, François Hébert, Sung-Shan Tai, Sik K Lui
  • Patent number: 8367499
    Abstract: A semiconductor device and a method for manufacturing the same are provided. The method includes forming a cell structure where a storage node contact is coupled to a silicon layer formed over a gate, thereby simplifying the manufacturing process of the device. The semiconductor device includes a bit line buried in a semiconductor substrate; a plurality of gates disposed over the semiconductor substrate buried with the bit line; a first plug disposed in a lower portion between the gates and coupled to the bit line; a silicon layer disposed on the upper portion and sidewalls of the gate; and a second plug coupled to the silicon layer disposed over the gate.
    Type: Grant
    Filed: December 15, 2010
    Date of Patent: February 5, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Hyung Jin Park
  • Patent number: 8343820
    Abstract: A method for fabricating a vertical channel type non-volatile memory device including a plurality of memory cells stacked along channels protruding from a substrate includes: alternately forming a plurality of first material layers and a plurality of second material layers over the substrate; forming a buffer layer over the substrate with the plurality of the first material layers and the plurality of the second material layers formed thereon; forming trenches by etching the buffer layer, the plurality of the second material layers, and the plurality of the first material layers; forming a material layer for channels over the substrate to fill the trenches; and forming the channels by performing a planarization process until a surface of the buffer layer is exposed.
    Type: Grant
    Filed: November 24, 2009
    Date of Patent: January 1, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Young-Kyun Jung
  • Patent number: 8338261
    Abstract: A semiconductor device includes a gate insulator and a gate electrode stacked on a substrate, a source/drain pattern which fills a recess region formed at opposite sides adjacent to the gate electrode, the source/drain pattern being made of silicon-germanium doped with dopants and a metal germanosilicide layer disposed on the source/drain pattern. The metal germanosilicide layer is electrically connected to the source/drain pattern. Moreover, a proportion of germanium amount to the sum of the germanium amount and silicon amount in the metal germanosilicide layer is lower than that of germanium amount to the sum of the germanium amount and silicon amount in the source/drain pattern.
    Type: Grant
    Filed: August 6, 2010
    Date of Patent: December 25, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Myung-Sun Kim, Hwa-Sung Rhee, Tetsuji Ueno, Ho Lee, Ji-Hye Yi
  • Patent number: 8309417
    Abstract: In a vertical-type memory device and a method of manufacturing the vertical-type memory device, the vertical memory device includes an insulation layer pattern of a linear shape provided on a substrate, pillar-shaped single-crystalline semiconductor patterns provided on both sidewalls of the insulation layer pattern and transistors provided on a sidewall of each of the single-crystalline semiconductor patterns. The transistors are arranged in a vertical direction of the single-crystalline semiconductor pattern, and thus the memory device may be highly integrated.
    Type: Grant
    Filed: October 12, 2011
    Date of Patent: November 13, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Hoon Son, Jong-Wook Lee, Jong-Hyuk Kang
  • Patent number: 8304305
    Abstract: A method for producing a semiconductor component is proposed. The method includes providing a semiconductor body having a first surface; forming a mask on the first surface, wherein the mask has openings for defining respective positions of trenches; producing the trenches in the semiconductor body using the mask, wherein mesa structures remain between adjacent trenches; introducing a first dopant of a first conduction type using the mask into the bottoms of the trenches; carrying out a first thermal step; introducing a second dopant of a second conduction type, which is complementary to the first conduction type, at least into the bottoms of the trenches; and carrying out a second thermal step.
    Type: Grant
    Filed: June 8, 2011
    Date of Patent: November 6, 2012
    Assignee: Infineon Technologies Austria AG
    Inventors: Davide Chiola, Carsten Schaeffer
  • Patent number: 8298889
    Abstract: An electronic device can include a first layer having a primary surface, a well region lying adjacent to the primary surface, and a buried doped region spaced apart from the primary surface and the well region. The electronic device can also include a trench extending towards the buried doped region, wherein the trench has a sidewall, and a sidewall doped region along the sidewall of the trench, wherein the sidewall doped region extends to a depth deeper than the well region. The first layer and the buried region have a first conductivity type, and the well region has a second conductivity type opposite that of the first conductivity type. The electronic device can include a conductive structure within the trench, wherein the conductive structure is electrically connected to the buried doped region and is electrically insulated from the sidewall doped region. Processes for forming the electronic device are also described.
    Type: Grant
    Filed: December 10, 2008
    Date of Patent: October 30, 2012
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Jaume Roig-Guitart, Peter Moens, Marnix Tack
  • Patent number: 8264033
    Abstract: A semiconductor device includes a first trench and a second trench extending into a semiconductor body from a surface. A body region of a first conductivity type adjoins a first sidewall of the first trench and a first sidewall of the second trench, the body region including a channel portion adjoining to a source structure and being configured to be controlled in its conductivity by a gate structure. The channel portion is formed at the first sidewall of the second trench and is not formed at the first sidewall of the first trench. An electrically floating semiconductor zone of the first conductivity type adjoins the first trench and has a bottom side located deeper within the semiconductor body than the bottom side of the body region.
    Type: Grant
    Filed: July 21, 2009
    Date of Patent: September 11, 2012
    Assignee: Infineon Technologies Austria AG
    Inventors: Frank Pfirsch, Maria Cotorogea, Franz Hirler, Franz-Josef Niedernostheide, Thomas Raker, Hans-Joachim Schulze, Hans Peter Felsl
  • Patent number: 8242555
    Abstract: Methods, devices and systems for a FinFET are provided. One method embodiment includes forming a FinFET by forming a relaxed silicon germanium (Si1-XGeX) body region for a fully depleted Fin field effect transistor (FinFET) having a body thickness of at least 10 nanometers (nm) for a process design rule of less than 25 nm. The method also includes forming a source and a drain on opposing ends of the body region, wherein the source and the drain are formed with halo ion implantation and forming a gate opposing the body region and separated therefrom by a gate dielectric.
    Type: Grant
    Filed: February 5, 2010
    Date of Patent: August 14, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Hussein I. Hanafi
  • Patent number: 8222110
    Abstract: A method for fabricating a semiconductor device includes forming a plurality of first active pillars by etching a substrate using a hard mask layer as an etching barrier, forming a gate conductive layer surrounding sidewalls of the first active pillars and the hard mask layer, forming a word line conductive layer filling gaps defined by the gate conductive layer, forming word lines and vertical gates by simultaneously removing portions of the word line conductive layer and the gate conductive layer on the sidewalls of the hard mask layer, forming an inter-layer dielectric layer filling gaps formed by removing the word line conductive layer and the gate conductive layer, exposing surfaces of the first active pillars by removing the hard mask layer, and growing second active pillars over the first active pillars.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: July 17, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Eun-Jeong Kim, Sang-Tae Ahn
  • Patent number: 8222076
    Abstract: A process for fabricating a semiconductor layer of an electronic device including: liquid depositing one or more zinc oxide precursor compositions and forming at least one semiconductor layer of the electronic device comprising predominately amorphous zinc oxide from the liquid deposited one or more zinc oxide precursor compositions.
    Type: Grant
    Filed: August 2, 2006
    Date of Patent: July 17, 2012
    Assignee: Xerox Corporation
    Inventors: Yiliang Wu, Yuning Li, Beng S. Ong
  • Patent number: 8211758
    Abstract: It is an object to provide an SGT production method capable of obtaining a structure for reducing a resistance of a gate, a desired gate length, desired source and drain configurations and a desired diameter of a pillar-shaped semiconductor.
    Type: Grant
    Filed: February 3, 2010
    Date of Patent: July 3, 2012
    Assignee: Unisantis Electronics Singapore PTE Ltd.
    Inventors: Fujio Masuoka, Shintaro Arai, Hiroki Nakamura, Tomohiko Kudo
  • Patent number: 8207032
    Abstract: Some embodiments include methods of forming vertical transistors. A construction may have a plurality of spaced apart fins extending upwardly from a semiconductor substrate. Each of the fins may have vertical transistor pillars, and each of the vertical transistor pillars may have a bottom source/drain region location, a channel region location over the bottom source/drain region location, and a top source/drain region location over the channel region location. Electrically conductive gate material may be formed along the fins while using oxide within spaces along the bottoms of the fins to offset the electrically conductive gate material to be above the bottom source/drain region locations of the vertical transistor pillars. The oxide may be an oxide which etches at a rate of at least about 100 ?/minute with dilute HF at room temperature. In some embodiments the oxide may be removed after the electrically conductive gate material is formed.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: June 26, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Mark Fischer, Sanh D. Tang
  • Patent number: 8207566
    Abstract: A vertical channel transistor includes a plurality of active pillar patterns extending perpendicularly from the top surface of the substrate toward an upper part. A gate insulating layer is deposited on the side wall of the active pillar pattern and serves as an ion diffusion barrier between the pillar patterns and surrounding lower gate electrodes. The resultant pillar pattern structure is encapsulated with a metal. The resultant pillar pattern is surrounded on all sides by a specified height by a sacrificial layer of Spin-On Dielectric (SOD). The metal layer is etched-back to the height of the sacrificial layer, thus forming the lower gate electrodes. A spacer layer of an insulating mater is deposited surrounding the upper part of the pillar patterns and the sacrificial layer is removed exposing a part of the lower gate electrodes. The exposed gate electrode is etched to facilitate semiconductor integration.
    Type: Grant
    Filed: March 24, 2011
    Date of Patent: June 26, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Chun-Hee Lee