Abstract: The gate region of a field effect transistor comprises at least one through hole wherein a nanoelement is provided which is electrically coupled to the source and the drain. The nanoelement may have the conductance thereof controlled by means of the gate, such that the nanoelement forms a channel region of the field effect transistor.

Abstract: A field effect transistor has an inverse-T gate conductor having a thicker center portion and thinner wings. The wings may be of a different material different than the center portion. In addition, gate dielectric may be thicker along edges than in the center. Doping can also be different under the wings than along the center portion or beyond the gate. Regions under the wings may be doped differently than the gate conductor. With a substantially vertical implant, a region of the channel overlapped by an edge of the gate is implanted without implanting a center portion of the channel, and this region is blocked from receiving at least a portion of the received by thick portions of the gate electrode.

Abstract: A semiconductor device is disclosed. The semiconductor device includes one or more charge control electrodes a plurality of charge control electrodes. The one or more charge control electrodes may control the electric field within the drift region of a semiconductor device.

Abstract: The present invention provides a method of forming a vertical replacement gate (VRG) device on a semiconductor substrate. The method includes depositing an epitaxial layer over a first source/drain region, implanting a layer within the epitaxial layer wherein the thickness of the layer substantially defines a channel length of the device and replacing the layer with a gate layer.

Abstract: A SRAM memory cell including an access device formed on a storage device is described. The storage device has at least two stable states that may be used to store information. In operation, the access device is switched ON to allow a signal representing data to be coupled to the storage device. The storage device switches to a state representative of the signal and maintains this state after the access device is switched OFF. When the access device is switched ON, the state of the storage device may be sensed to read the data stored in the storage device. The memory cell may be formed to be unusually compact and has a reduced power supply requirements compared to conventional SRAM memory cells. As a result, a compact and robust SRAM having reduced standby power requirements is realized.

Abstract: A trench capacitor with an expanded area for use in a memory cell and a method for making the same are provided. The trench capacitor includes a vertical trench formed in a semiconductor, a doping region formed around a low portion of the trench, a collar isolation layer formed on an inner sidewall of an upper portion of the trench, a doped silicon liner layer formed on a surface of the collar isolation layer, wherein the doped silicon liner layer is electrically connected to the doping region, a dielectric layer formed on a surface of the doped silicon liner layer and inner sidewall of the lower portion of the trench, and a doped silicon material formed inside the trench.

Abstract: The present invention provides a process for fabricating a metal oxide semiconductor field effect transistor (MOSFET) having a double-gate and a double-channel wherein the gate region is self-aligned to the channel regions and the source/drain diffusion junctions. The present invention also relates to the FIN MOSFFET structure which is formed using method of the present invention.

Abstract: P-type active regions (1) and n-type active regions (2) are provided on a semiconductor substrate (not shown). Three gate interconnect lines (3, 4, 5) are arranged on the p-type active regions (1) and the n-type active regions (2). The p-type active regions (1) are provided with protruding parts for holding therein contact holes (6, 7). The contact holes (6, 7) are each arranged on the side opposite to that facing the n-type active regions (2) (in FIG. 1, on the upper part of the p-type active region (1)). The contact hole (6) in one protruding part is provided between the gate interconnect lines (3) and (4). The contact hole (7) in other protruding part is formed between the gate interconnect lines (4) and (5).

Abstract: A method of producing a semiconductor device having an SOI transistor and a multi-layer wiring, including: preparing a silicon substrate having a front face and a back face; forming an inter-layer insulation layer on the front face of the silicon substrate; forming a multi-layer wiring in the inter-layer insulation layer; fixing a substrate on the inter-layer insulation layer; thinning the silicon substrate from the back face into a thin film so that the silicon substrate becomes an SOI layer; and forming a channel layer and a gate electrode on a back of the channel layer in the SOI layer, and further forming a source and a drain facing each other having the channel layer in between so that an SOI transistor is obtained.

Abstract: A CMOS process for double vertical channel thin film transistor (DVC TFT). This process fabricates a CMOS with a double vertical channel (DVC) structure and defines the channel without an additional mask. The DVC structure of the CMOS side steps the photolithography limitation because the deep-submicrometer channel length is determined by the thickness of gate, thereby decreasing the channel length of the CMOS substantially.

Abstract: There are contained the steps of forming a first conductive film, a ferroelectric film, and a second conductive film on an insulating film, forming a hard mask on the second conductive film, forming a capacitor upper electrode by etching the second conductive film in an area exposed from the hard mask at a first temperature, forming a capacitor dielectric film by etching the ferroelectric film in the area exposed from the hard mask at a second temperature, and forming a capacitor lower electrode by etching the first conductive film in the area exposed from the hard mask at a third temperature that is higher than the second temperature.

Abstract: An improved method for making an integrated circuit. That method includes forming a first dielectric layer on a substrate, etching a trench into that layer, then filling the trench with a conductive material. The conductive material is then electropolished to form a recessed conductive layer within the first dielectric layer.

Abstract: A process for fabricating a CMOS integrated circuit with vertical MOSFET devices is disclosed. In the process, at least three layers of material are formed sequentially on a semiconductor substrate. The three layers are arranged such that the second layer is interposed between the first and third layers. The second layer is sacrificial, that is, the layer is completely removed during subsequent processing. The thickness of the second layer defines the physical gate length of the vertical MOSFET devices. After the at least three layers of material are formed on the substrate, the resulting structure is selectively doped to form an n-type region and a p-type region in the structure. Windows or trenches are formed in the layers in both the n-type region and the p-type region. The windows terminate at the surface of the silicon substrate in which one of either a source or drain region is formed. The windows or trenches are then filled with a semiconductor material.

Abstract: A semiconductor device is disclosed, which includes a semiconductor substrate, drain and source regions of a MOS transistor, a gate electrode formed on a surface of a channel region of the MOS transistor trench type element isolation regions in each of which an insulating film is formed on a surface of a trench formed in the surface of the semiconductor substrate, the element isolation regions sandwiching the channel region from opposite sides thereof in a channel width direction, and a conductive material layer for a back gate electrode, which is embedded in a trench of at least one of the element isolation regions, configured to be supplied with a predetermined voltage to make an depletion layer in a region of the semiconductor substrate under the channel region of the MOS transistor or to voltage-control the semiconductor substrate region.

Abstract: A dual gate transistor device and method for fabricating the same. First, a doped substrate is prepared with a patterned oxide layer on the doped substrate defining a channel. Next, a silicon layer is deposited to form the channel, with a gate oxide layer then grown adjacent the channel. Subsequently, a plurality of gate electrodes are formed next to the gate oxide layer and a drain is formed on the channel. After the drain is formed, an ILD layer is deposited. This ILD layer is etched to form a source region contact, a drain region contact, a first gate electrode contact, and a second gate electrode contact.

Abstract: A vertical power transistor trench-gate semiconductor device has an active area (100) accommodating transistor cells and an inactive area (200) accommodating a gate electrode (25) (FIG. 6). While an n-type layer (14) suitable for drain regions still extends to the semiconductor body surface (10a), gate material (11) is deposited in silicon dioxide insulated (17) trenches (20) and planarised to the top of the trenches (20) in the active (100) and inactive (200) areas. Implantation steps then provide p-type channel-accommodating body regions (15A) in the active area (100) and p-type regions (15B) in the inactive area (200), and then source regions (13) in the active area (100). Further gate material (111) is then provided extending from the gate material (11) in the inactive area (200) and onto a top surface insulating layer (17B) for contact with the gate electrode (25).

Abstract: In a process for manufacturing deep trench memory cells, a method of forming a nitride spacer so as to avoid shorts resulting from poly filling voids in said nitride spacer. The voids occur because of nitride filament overhangs from the nitride pad.

Abstract: An improved and novel semiconductor device including an amorphous carbon layer for improved adhesion of photoresist and method of fabrication. The device includes a substrate having a surface, a carbon layer, formed on the surface of the substrate, and a resist layer formed on a surface of the carbon layer. The device is formed by providing a substrate having a surface, depositing a carbon layer on the surface of the substrate using plasma enhanced chemical vapor deposition (PECVD) or sputtering, and forming a resist layer on a surface of the carbon layer.

Abstract: A vertical thin film transistor formed in a single grain of polysilicon having few or no grain boundaries for use in memory, logic and display applications. The transistor is formed from a thin film of polysilicon having large columnar grains, in which source and drain regions have been formed. The large grain size and columnar grain orientation of the thin film are provided by recrystallizing a thin amorphous silicon film, or by specialized deposition of the thin film. Use of a thin film permits the transistor to be formed on an insulating substrate such as glass, quartz, or inexpensive silicon rather than a semiconductor chip, thereby significantly decreasing device cost.

Abstract: The present invention provide a vertical nano-sized transistor using carbon nanotubes capable of achieving high-density integration, that is, tera-bit scale integration, and a manufacturing method thereof, wherein in the vertical nano-sized transistor using carbon nanotubes, holes having diameters of several nanometers are formed in an insulating layer and are spaced at intervals of several nanometers. Carbon nanotubes are vertically aligned in the nano-sized holes by chemical vapor deposition, electrophoresis or mechanical compression to be used as channels. A gate is formed in the vicinity of the carbon nanotubes using an ordinary semiconductor manufacturing method, and then a source and a drain are formed at lower and upper parts of each of the carbon nanotubes thereby fabricating the vertical nano-sized transistor having an electrically switching characteristic.

Abstract: A process for making an integrated circuit is described wherein sequence of mask steps is applied to a substrate or epitaxial layer of p-type material.

Abstract: A method of manufacturing a vertical transistor. A doped region is formed in a substrate. We form sequentially on the substrate: a first spacer dielectric layer, a first gate electrode, a second spacer dielectric layer, a second gate electrode and a third spacer dielectric layer. A trench is formed through the first spacer dielectric layer, the first gate electrode, the second spacer dielectric layer, the second gate electrode and the third spacer dielectric layer. The trench has sidewalls. A gate dielectric layer is formed over the sidewalls of the trench. We form sequentially, in the trench: a first doped layer, a first channel layer, a second doped layer, a third doped layer, a second channel layer, and a fourth doped layer. A cap layer is formed over the structure. Contacts are preferably formed to the doped region, doped layers and gate electrodes.

Abstract: A MOS transistor includes an upper source/drain region, a channel region, and a lower source/drain region that are stacked as layers one above the other and form a projection of a substrate. A gate dielectric adjoins a first lateral area of the projection. A gate electrode adjoins the gate dielectric. A conductive structure adjoins a second lateral area of the projection in the region of the channel region. The conductive structure adjoins the gate electrode.

Abstract: A method for a memory cell has a trench capacitor and a vertical transistor adjacent to the capacitor. The vertical transistor has a gate conductor above the trench capacitor. The upper portion of the gate conductor is narrower than the lower portion of the gate conductor. The memory cell further includes spacers adjacent the upper portion of the gate conductor and a bitline contact adjacent to the gate conductor. The spacers reduce short circuits between the bitline contact and the gate conductor. The gate contact above the gate conductor has an insulator which separates the gate contact from the bitline. The difference between the width of the upper and lower portions of the gate conductor reduces short circuits between the bitline contact and the gate conductor.

Abstract: A method of fabricating an isolated vertical transistor comprising the following steps. A wafer having a first implanted region selected from the group comprising a source region and a drain region is provided. The wafer further includes STI areas on either side of a center transistor area. The wafer is patterned down to the first implanted region to form a vertical pillar within the center transistor area using a patterned hardmask. The vertical pillar having side walls. A pad dielectric layer is formed over the wafer, lining the vertical pillar. A nitride layer is formed over the pad dielectric layer. The structure is patterned and etched through the nitride layer and the pad dielectric layer; and into the wafer within the STI areas to form STI trenches within the wafer. The STI trenches are filled with insulative material to form STIs within STI trenches. The patterned nitride and pad dielectric layers are removed. The patterned hardmask is removed.

Abstract: Using current technology, the only way to further increase device density is to decrease device pitch. The present invention achieves this by introducing a sidewall doping process that effectively reduces the source width, and hence the pitch. This sidewall doping process also eliminates the need for a source implantation mask while the sidewall spacer facilitates silicide formation at the source, the P body contact, and the polysilicon gate simultaneously. Since the source and P body are fully covered by silicide, the contact number and contact resistance can be minimized. The silicided polysilicon gate has a low sheet resistance of about 4-6 ohm/square, resulting in a higher operating frequency.

Abstract: A SRAM memory cell including an access device formed on a storage device is described. The storage device has at least two stable states that may be used to store information. In operation, the access device is switched ON to allow a signal representing data to be coupled to the storage device. The storage device switches to a state representative of the signal and maintains this state after the access device is switched OFF. When the access device is switched ON, the state of the storage device may be sensed to read the data stored in the storage device. The memory cell may be formed to be unusually compact and has a reduced power supply requirements compared to conventional SRAM memory cells. As a result, a compact and robust SRAM having reduced standby power requirements is realized.

Abstract: A method for a memory cell has a trench capacitor and a vertical transistor adjacent to the capacitor. The vertical transistor has a gate conductor above the trench capacitor. The upper portion of the gate conductor is narrower than the lower portion of the gate conductor. The memory cell further includes spacers adjacent the upper portion of the gate conductor and a bitline contact adjacent to the gate conductor. The spacers reduce short circuits between the bitline contact and the gate conductor. The gate contact above the gate conductor has an insulator which separates the gate contact from the bitline. The difference between the width of the upper and lower portions of the gate conductor reduces short circuits between the bitline contact and the gate conductor.

Abstract: The device is constituted by an N+ substrate, by an N− layer on the substrate, by a metal contact for a collector, by a buried P− base region, by a P+ base contact and insulation region within which an insulated N region is defined, by a metal contact on the base contact region for a base, by an N+ emitter region buried in the insulated region and forming a pn junction with the buried base region, by a P+ body region in the insulated region, by an N+ source region in the P+ region, by a metal contact for a source, and by a gate electrode. In order to achieve a low resistance Ron, the P+ body region extends as far as the buried N+ emitter region and an additional N+ region is provided within the body region and constitutes a drain region, defining, with the source region, the channel of a lateral MOSFET transistor.

Abstract: A multi-function semiconductor device is provided. The device includes a bipolar transistor and an FET formed in parallel. A semiconductor substrate is provided on an insulating layer. A source/emitter region and a drain region are formed in the semiconductor substrate and border first opposite sides of a body region therebetween. A gate is formed above the substrate between the source/emitter region and the drain region to form an FET having three terminals including the gate, the source/emitter region, and the drain region. A collector region is formed in the substrate abutting the drain region and extending further under the gate and the drain region. A bipolar transistor having three terminals is formed including a base region, the source/emitter, and the collector region. A shortest distance between the collector region and the source/emitter region defines a base width.

Abstract: A semiconductor substrate is provided, and a gate oxide layer is formed on said semiconductor substrate. Next, a poly film is deposited on said gate oxide layer, and a photo-resist is formed on the poly film for defining a length of poly gate. Then, proceeding with an ion implant of the lightly doped drain (LDD) through the poly film into the structure by the photo-resist as a mask, so as to form a lightly doped drain region in the semiconductor substrate. Next, the width of the photo-resist layer is added to be as an ion-implanted mask. The poly film is etched to form a poly gate. Then, a source/drain region is formed in the semiconductor by a ion implanting, wherein the photo-resist can be treated by thermal method or resolution enhancement lithography assisted by chemical shrink (RELACS) process to control the profile width of the photo-resist.

Abstract: A method for a vertical transistor by selective epi deposition to form the conductive source, drain, and channel layers. The conductive source, drain, and channel layers are preferably formed by a selective epi process. Dielectric masks define the conductive layers and make areas to form vertical contacts to the conductive S/D and channel layers.

Abstract: A nonvolatile semiconductor memory, including a ferroelectric capacitor connected to the gate of a MOSFET, comprises a silicon thin film formed in stripes on an insulated substrate and having an n+-region, a p-region and an n+-region layered in its thickness direction, a hole formed in a portion of the silicon thin film and extending to the lower n+-region, a gate electrode provided on the side walls of the hole with a gate insulting film interposed therebetween, and a ferroelectric capacitor formed on the silicon thin film and having its lower electrode connected to the gate electrode.

Abstract: An embodiment of the instant invention is a method of making a transistor having a silicided gate structure insulatively disposed over a semiconductor substrate, the method comprising the steps of: forming a conductive structure insulatively disposed over the semiconductor substrate (step 302 of FIG. 3); introducing a silicide enhancing substance into the conductive structure (step 304 of FIG. 3); amorphizing a portion of the conductive structure; forming a metal layer on the conductive structure (step 310 of FIG. 3); and wherein the metal layer interacts with the silicide enhancing substance in the amorphized portion of the conductive structure so as to form a lower resistivity silicide on the conductive structure. The conductive structure is, preferably, comprised of: doped polysilicon, undoped polysilicon, epitaxial silicon, or any combination thereof. Preferably, the silicide enhancing substance is comprised of: molybdenum, Co, W, Ta, Nb, Ru, Cr, any refractory metal, and any combination thereof.

Abstract: The n-channel VDMOS transistor is formed in an n-type active region of an integrated circuit with junction isolation. To prevent over-voltages between source and gate which could damage or destroy the gate dielectric, a p-channel MOS transistor is formed in the same active region and has its gate electrode connected to the gate electrode of the VDMOS transistor, its source region in common with the source region of the VDMOS transistor, and its drain region connected to the p-type junction-isolation region. The p-channel MOS transistor has a threshold voltage below the breakdown voltage of the gate dielectric of the VDMOS transistor so that it acts as a voltage limiter.

Abstract: A method of defining at least two different field effect transistor channel lengths includes forming a channel defining layer over a substrate, the semiconductor substrate having a mean global outer surface extending along a plane. First and second openings are etched into the channel defining layer. The first and second openings respectively have a pair of opposing sidewalls having substantially straight linear segments which are angled from the plane. The straight linear segments of the opposing sidewalls of the first opening are angled differently from the plane than the straight linear segments of the opposing sidewalls of the second opening and are thereby of different lengths. Integrated circuitry includes a first field effect transistor and a second field effect transistor. The first and second field effect transistors have respective channel lengths defined along their gate dielectric layers and respectively have at least some portion which is substantially straight linear.

Abstract: A method for fabricating a gate device includes forming a discrete post on a substrate. The discrete post protrudes from a surrounding area of the substrate and includes an access channel for the gate device. A first terminal and a second terminal are formed and coupled to the access channel in the discrete post. A gate structure is formed and operable to control the access channel to selective couple the first terminal to the second terminal.

Abstract: A SRAM memory cell including an access device formed on a storage device is described. The storage device has at least two stable states that may be used to store information. In operation, the access device is switched ON to allow a signal representing data to be coupled to the storage device. The storage device switches to a state representative of the signal and maintains this state after the access device is switched OFF. When the access device is switched ON, the state of the storage device may be sensed to read the data stored in the storage device. The memory cell may be formed to be unusually compact and has a reduced power supply requirements compared to conventional SRAM memory cells. As a result, a compact and robust SRAM having reduced standby power requirements is realized.

Abstract: A power MOSFET or other semiconductor device contains a layer of silicon combined with germanium to reduce the on-resistance of the device. The proportion of germanium in the layer is typically in the range of 1-40%. To achieve desired characteristics the concentration of germanium in the Si-Ge layer can be uniform, stepped or graded. In many embodiments it is desirable to keep the germanium below the surface of the semiconductor material to prevent germanium atoms from being incorporated into a gate oxide layer. This technique can be used in vertical DMOS and trench-gated MOSFETs, quasi-vertical MOSFETs and lateral MOSFETs, as well as insulated gate bipolar transistors, thyristors, Schottky diodes and conventional bipolar transistors.

Abstract: A method of fabricating an SRAM cell having a first conductivity type substrate includes the steps of forming a well of a second conductivity type in the first conductivity type substrate, forming a first active region of a first access transistor and a second active region of a second access transistor in the well, the first and second active regions being in parallel with each other, forming a first trench in the first active region and a second trench in the second active region, wherein the first and second trenches extend into the substrate through the well, forming gate electrodes of the first and second access transistors on the active regions, forming gate electrodes of first and second drive transistors in the first and second trenches, respectively, implanting first conductivity type impurity ions into the active regions of the first and second access transistors, respectively, forming first and second load devices on the substrate, the first and second load devices electrically contacting first ter

Abstract: A method for fabricating a transistor device on a semiconductor substrate, comprising the following steps. A semiconductor substrate having a silicon surface with an overlying insulating dielectric layer is provided. The insulating dielectric layer is patterned to define hole/channel regions having predetermined widths. An amorphous silicon layer is formed having a predetermined thickness over the dielectric layer and the hole/channel regions, filling the hole/channel regions. Heating (grain growth) the amorphous silicon layer to form a planar silicon layer, comprising at least a portion of epitaxial-silicon, having a predetermined thickness, over the dielectric layer and through the hole/channel regions, filling the hole/channel regions. The planar silicon layer is patterned to expose the hole/channel regions and define transistor regions. Trenches are formed in the silicon surface adjacent the transistor regions.

Abstract: A thin film transistor and a fabrication method thereof in which a desired device characteristic is achieved by adjusting the lengths of a channel region and an offset region. The transistor includes a substrate in which a trench is formed, a gate electrode formed in one side in the interior of the trench, a gate insulation film formed in the substrate including the gate electrode, an active layer formed on the gate insulation film, and impurity regions formed on the active layer corresponding to the substrate. The length of the channel and offset regions are adjusted by adjusting the length and width of the trench within the substrate.

Abstract: A thin film transistor includes a first insulating layer and a first conductive layer formed on a semiconductor substrate, a second insulating layer, a second conductive layer and a third insulating layer sequentially formed on the first conductive layer, a contact hole formed in the second insulating layer, second conductive layer and third insulating layer, a gate insulating layer formed along the sidewall of the contact hole, and a third conductive layer formed on the contact hole formed with the gate insulating layer thereon and surface of the third insulating layer to be used as a channel region and a source region by implanting an impurity, in which a drain region, a gate electrode and the source region are stacked, or vertically aligned, on the substrate to allow a cell to occupy a small area for accomplishing high packing density of the cell and permit the gate electrode to encircle the channel region for improving a characteristic of the transistor, thereby stabilizing the cell.

Abstract: An integrated device in an emitter-switching configuration comprises a first bipolar transistor having a base region, an emitter region, and a collector region, a second transistor having a charge-collection terminal connected to an emitter terminal of the first transistor, and a quenching element having a terminal connected to a base terminal of the first transistor. The quenching element is formed within the base region or the emitter region of the first transistor.

Abstract: A field effect transistor occupying a small area and a semiconductor device using the same can be obtained. A gate electrode is provided on a substrate on which a source region is provided with a first interlayer insulating film interposed therebetween. The gate electrode is covered with a second interlayer insulating film. A contact hole for exposing a part of the surface of the source region is provided so as to penetrate through the first interlayer insulating film, the gate electrode, and the second interlayer insulating film. A sidewall surface of the contact hole is covered with a gate insulating film. A first semiconductor layer of a first conductivity type is provided on the surface of the source region in contact therewith up to the lower surface of the gate electrode. A channel semiconductor layer is provided on the surface of the first semiconductor layer up to the upper surface of the gate electrode.

Abstract: A trench MOSFET is formed in a structure which includes a P-type epitaxial layer overlying an N+ substrate. An N drain region is implanted through the bottom of the trench into the P-epitaxial layer, and after a diffusion step extends between the N+ substrate and the bottom of the trench. The junction between the N drain region and the P-epitaxial layer extends between the N+ substrate and a sidewall of the trench. In some embodiments the epitaxial layer can have a stepped doping concentration or a threshold voltage adjust implant can be added. Alternatively, the drain region can be omitted, and the trench can extend all the way through the P-epitaxial layer into the N+ substrate. A MOSFET constructed in accordance with this invention can have a reduced threshold voltage and on-resistance and an increased punchthrough breakdown voltage.

Abstract: This invention discloses a DMOS power device supported on a substrate of a first conductivity type functioning as a drain. The DMOS power device includes a polysilicon-over-double-gate-oxide gate disposed on the substrate includes a polysilicon layer disposed over a double-gate-oxide structure having a central thick-gate-oxide segment surrounded by a thin-gate-oxide layer with a thickness of about one-fourth to one-half of a thickness of the thick-gate-oxide segment. The DMOS power device further includes a body region of a second conductivity type disposed in the substrate underneath the thin-gate-oxide layer around edges of the central thick-gate-oxide segment the body region extending out laterally to a neighboring device circuit element. The DMOS power device further includes a source region of the first conductivity type disposed in the substrate encompassed in the body region having a portion extending laterally underneath the thin-gate-oxide layer.

Abstract: A semiconductor apparatus comprising a vertical type semiconductor device having a first conducting type semiconductor substrate, a drain layer formed on the surface of the semiconductor substrate, a drain electrode formed on the surface of the drain layer, a second conducting type base layer selectively formed on the surface of the semiconductor substrate opposite to the drain layer, a first conducting type source layer selectively formed on the surface of the second conducting type base layer, a source electrode formed on the first conducting type source layer and the second conducting type base layer, and a gate electrode formed in contact with the first conducting type source layer, the second conducting type base layer and the semiconductor substrate through a gate insulating film and a lateral semiconductor device having an insulating layer formed in a region of the surface of the semiconductor substrate different from the second conducting type base layer, and a polycrystalline semiconductor layer form

Abstract: In the manufacture of an MOS gated semiconductor device, indentations are provided on a surface of a semiconductor wafer extending inwardly of respective spaced apart regions at the wafer surface having doping concentrations greater than that present in the remainder of the wafer. A layer of silicon having a doping concentration less than that of the substrate is conformally provided on the substrate surface whereby the indentations in the substrate surface are replicated on the surface of the silicon layer. Dopants in the substrate regions are then out-diffused into the silicon layer to provide highly doped buried regions within the layer. Then, using the silicon layer surface indentations as photomask alignment marks, gate electrode structures are formed on and within the silicon layer in preselected orientation relative to the buried regions. The buried regions provide low resistance paths for current through the resulting devices.

Abstract: Complementary LDMOS and MOS structures and vertical PNP transistors capable of withstanding a relatively high voltage may be realized in a mixed-technology integrated circuit of the so-called “smart power” type, by forming a phosphorus doped n-region of a similar diffusion profile, respectively in: The drain zone of the n-channel LDMOS transistors, in the body zone of the p-channel LDMOS transistors forming first CMOS structures; in the drain zone of n-channel MOS transistors belonging to second CMOS structures and in a base region near the emitter region of isolated collector, vertical PNP transistors, thus simultaneously achieving the result of increasing the voltage withstanding ability of all these monolithically integrated structures.