Plural Wells Patents (Class 438/228)
  • Patent number: 10985074
    Abstract: A CMOS transistor manufacturing method includes: forming a gate insulating film on a semiconductor substrate; forming a first gate electrode pattern on the gate insulating film in an NMOS transistor area; forming a second gate electrode pattern on the gate insulating film in a PMOS transistor area; forming a first photoresist pattern covering the NMOS transistor area to expose the second gate electrode pattern; performing a first ion injection process into the PMOS transistor area to form an n-type well region and a p-type LDD region; removing the first photoresist pattern; forming a second photoresist pattern covering the PMOS transistor area to expose the first gate electrode pattern; performing a second ion injection process into the NMOS transistor area to form a p-type well region and an n-type LDD region; removing the second photoresist pattern; and forming sidewall spacers at sidewalls of the first and second gate electrode patterns.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: April 20, 2021
    Assignee: Key Foundry Co., Ltd
    Inventors: Min Kuck Cho, Myeong Seok Kim, In Chul Jung
  • Patent number: 10643963
    Abstract: A semiconductor structure and its fabrication method are provided. The fabrication method includes: providing a base substrate including a wiring region and an isolation region. A patterned layer is formed on the isolation region of the base substrate and the patterned layer exposes the wiring region of the base substrate. After forming the patterned layer, a redistribution layer is formed on the wiring region of the based substrate exposed by the patterned layer. A protective layer is formed on the redistribution layer, and after forming the protective layer, the patterned layer is removed.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: May 5, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Feng Ping Cai
  • Patent number: 10134733
    Abstract: A semiconductor device includes a semiconductor substrate and a control electrode provided on a first surface side of the semiconductor substrate. The semiconductor substrate includes a first area on the first surface side and two second areas on the first surface side of the first area. The two second areas are arranged along the first surface. The control electrode provided above a portion of the first area between the two second areas. The first area includes a main portion and a peripheral edge portion extending outward from the main portion along the first surface. A depth of the peripheral edge portion from the first surface is shallower than a depth of the main portion from the first surface; and the peripheral edge portion has a concentration of second conductivity type impurities lower than a concentration of the second conductivity type impurities at a surface of the main portion.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: November 20, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Hiroyuki Kutsukake
  • Patent number: 9934975
    Abstract: An N-type MOSFET and a method for manufacturing the same are disclosed. In one aspect, the method comprises forming source/drain regions in a semiconductor substrate. The method also includes forming an interfacial oxide layer on the semiconductor substrate. The method also includes forming a high-k gate dielectric layer on the interfacial oxide layer. The method also includes forming a first metal gate layer on the high-k gate dielectric layer. The method also includes implanting dopants into the first metal gate layer through conformal doping. The method also includes annealing a gate stack to change an effective work function of the gate stack which includes the first metal gate layer, the high-k gate dielectric, and the interfacial oxide layer.
    Type: Grant
    Filed: September 23, 2014
    Date of Patent: April 3, 2018
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huilong Zhu, Qiuxia Xu, Yanbo Zhang, Hong Yang
  • Patent number: 9312187
    Abstract: The present invention discloses a semiconductor device, comprising a first MOSFET; a second MOSFET; a first stress liner covering the first MOSFET and having a first stress; a second stress liner covering the second MOSFET and having a second stress; wherein the second stress liner and/or the first stress liner comprise(s) a metal oxide. In accordance with the high-stress CMOS and method of manufacturing the same of the present invention, a stress layer comprising a metal oxide is formed selectively on PMOS and NMOS respectively by using a CMOS compatible process, whereby carrier mobility of the channel region is effectively enhanced and the performance of the device is improved.
    Type: Grant
    Filed: April 11, 2012
    Date of Patent: April 12, 2016
    Assignee: The Institute of Microelectronics, Chinese Academy of Science
    Inventors: Huaxiang Yin, Xiaolong Ma, Qiuxia Xu, Dapeng Chen
  • Patent number: 9190261
    Abstract: Methods for aligning layers more accurately for FinFETs fabrication. An embodiment of the method, comprises: forming a plurality of dummy line features and a plurality of spacer elements according to a first pattern; removing portions of the plurality of spacer elements and portions of the plurality of dummy line features according to a second pattern; defining a reference area by removing some unwanted spacer elements according to a third pattern; aligning a front-end-of-line (FEOL) layer in X direction with the reference area defined by the third pattern; and aligning the FEOL layer in Y direction with the plurality of spacer elements defined by the first pattern. The reference area may be an active area or an alignment mask. The plurality of dummy line features and the plurality of spacer elements are formed on a substrate. The FEOL layer may be a poly layer or a shield layer.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: November 17, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Feng Shieh, Kuei-Liang Lu
  • Patent number: 9012280
    Abstract: According to an embodiment, a super junction semiconductor device may be manufactured by introducing impurities of a first impurity type into an exposed surface of a first semiconductor layer of the first impurity type, thus forming an implant layer. A second semiconductor layer of the first impurity type may be provided on the exposed surface and trenches may be etched through the second semiconductor layer into the first semiconductor layer. Thereby first columns with first overcompensation zones obtained from the implant layer are formed between the trenches. Second columns of the second conductivity type may be provided in the trenches. The first and second columns form a super junction structure with a vertical first section in which the first overcompensation zones overcompensate a corresponding section in the second columns.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: April 21, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Armin Willmeroth, Franz Hirler, Uwe Wahl
  • Patent number: 8962397
    Abstract: At least one N-well implant having a different doping level is formed in a silicon substrate by first etching the substrate with an alignment target for aligning future process masks thereto. This alignment target is outside of any active device area. By using at least one N-well implant having a different doping level in combination with the substrate, a graded junction in the drift area of a metal oxide semiconductor (MOS) field effect transistor (FET) can be created and a pseudo Ldd structure may be realized thereby.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: February 24, 2015
    Assignee: Microchip Technology Incorporated
    Inventors: Gregory Dix, Leighton E. McKeen, Ian Livingston, Roger Melcher, Rohan Braithwaite
  • Patent number: 8921202
    Abstract: The invention provides a semiconductor device. A buried layer is formed in a substrate. A first deep trench contact structure is formed in the substrate. The first deep trench contact structure comprises a conductor and a liner layer formed on a sidewall of the conductor. A bottom surface of the first deep trench contact structure is in contact with the buried layer.
    Type: Grant
    Filed: January 7, 2011
    Date of Patent: December 30, 2014
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Geeng-Lih Lin, Kwang-Ming Lin, Shang-Hui Tu, Jui-Chun Chang
  • Patent number: 8901623
    Abstract: According to an embodiment, a super junction semiconductor device may be manufactured by introducing impurities of a first impurity type into an exposed surface of a first semiconductor layer of the first impurity type, thus forming an implant layer. A second semiconductor layer of the first impurity type may be provided on the exposed surface and trenches may be etched through the second semiconductor layer into the first semiconductor layer. Thereby first columns with first overcompensation zones obtained from the implant layer are formed between the trenches. Second columns of the second conductivity type may be provided in the trenches. The first and second columns form a super junction structure with a vertical first section in which the first overcompensation zones overcompensate a corresponding section in the second columns.
    Type: Grant
    Filed: February 18, 2013
    Date of Patent: December 2, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Armin Willmeroth, Franz Hirler, Uwe Wahl
  • Patent number: 8883645
    Abstract: Methods for fabrication of nanopillar field effect transistors are described. These transistors can have high height-to-width aspect ratios and be CMOS compatible. Silicon nitride may be used as a masking material. These transistors have a variety of applications, for example they can be used for molecular sensing if the nanopillar has a functionalized layer contacted to the gate electrode. The functional layer can bind molecules, causing an electrical signal in the transistor.
    Type: Grant
    Filed: July 12, 2013
    Date of Patent: November 11, 2014
    Assignee: California Institute of Technology
    Inventors: Chieh-Feng Chang, Aditya Rajagopal, Axel Scherer
  • Patent number: 8853026
    Abstract: Semiconductor devices and methods of fabricating the same are provided. An insulating film can be disposed on a semiconductor substrate, and insulating film patterns can be formed opening a plurality of areas with predetermined widths by patterning the insulating film. A plurality of ion implantation areas having a first conductivity type can be formed by implanting impurities into the plurality of open areas, and an oxide film pattern can be formed on each of the ion implantation areas. The insulating film patterns can be removed, and ion implantation areas having a second conductivity type can be formed by implanting impurities using the oxide film pattern as a mask. The semiconductor substrate can be annealed at a high temperature to form deep wells.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: October 7, 2014
    Assignee: Dongbu Hitek Co., Ltd.
    Inventor: Kyung Wook Kwon
  • Patent number: 8735238
    Abstract: Methods and devices for forming both high-voltage and low-voltage transistors on a common substrate using a reduced number of processing steps are disclosed. An exemplary method includes forming at least a first high-voltage transistor well and a first low-voltage transistor well on a common substrate separated by an isolation structure extending a first depth into the substrate, using a first mask and first implantation process to simultaneously implant a doping material of a first conductivity type into a channel region of the low-voltage transistor well and a drain region for the high-voltage transistor well.
    Type: Grant
    Filed: March 3, 2011
    Date of Patent: May 27, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: ChanSam Chang, Shigenobu Maeda, HeonJong Shin, ChangBong Oh
  • Patent number: 8710479
    Abstract: According to example embodiments, there is provided a semiconductor device including a substrate and an isolation layer structure. The substrate includes an active region having an upper active pattern and a lower active pattern on the upper active pattern. The active region has a first aspect ratio larger than about 13:1 and a second aspect ratio smaller than about 13:1. The first aspect ratio is defined as a ratio of a sum of heights of the upper active pattern and the lower active pattern with respect to a width of the upper active pattern. The second aspect ratio is defined as a ratio of the sum of the heights of the upper active pattern and the lower active pattern with respect to a width of the lower active pattern. The isolation layer structure is adjacent to the active region.
    Type: Grant
    Filed: July 9, 2012
    Date of Patent: April 29, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-Won Kim, Yong-Kwan Kim
  • Patent number: 8664741
    Abstract: Provided is a high voltage semiconductor device that includes a PIN diode structure formed in a substrate. The PIN diode includes an intrinsic region located between a first doped well and a second doped well. The first and second doped wells have opposite doping polarities and greater doping concentration levels than the intrinsic region. The semiconductor device includes an insulating structure formed over a portion of the first doped well. The semiconductor device includes an elongate resistor device formed over the insulating structure. The resistor device has first and second portions disposed at opposite ends of the resistor device, respectively. The semiconductor device includes an interconnect structure formed over the resistor device. The interconnect structure includes: a first contact that is electrically coupled to the first doped well and a second contact that is electrically coupled to a third portion of the resistor located between the first and second portions.
    Type: Grant
    Filed: June 14, 2011
    Date of Patent: March 4, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Ru-Yi Su, Fu-Chih Yang, Chun Lin Tsai, Chih-Chang Cheng, Ruey-Hsin Liu
  • Patent number: 8658503
    Abstract: A semiconductor device includes: a silicon carbide substrate having first and second main surfaces; a first silicon carbide layer provided on the first main surface of the silicon carbide substrate; first silicon carbide regions formed on a surface of the first silicon carbide layer; second and third silicon carbide regions formed on respective surfaces of the first silicon carbide regions; a fourth silicon carbide region formed between facing first silicon carbide regions with the first silicon carbide layer therebetween; a gate insulating film formed continuously on surfaces of the first silicon carbide regions, the first silicon carbide layer, and the fourth silicon carbide region; a gate electrode formed on the gate insulating film; an interlayer insulating film covering the gate electrode; a first electrode electrically connected to the second and third silicon carbide regions; and a second electrode formed on the second main surface of the silicon carbide substrate.
    Type: Grant
    Filed: December 5, 2012
    Date of Patent: February 25, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Kono, Takashi Shinohe
  • Patent number: 8617991
    Abstract: A method of manufacturing a semiconductor device includes forming an interlayer dielectric film that has first and second trenches on first and second regions of a substrate, respectively, forming a first metal layer along a sidewall and a bottom surface of the first trench and along a top surface of the interlayer dielectric film in the first region, forming a second metal layer along a sidewall and a bottom surface of the second trench and along a top surface of the interlayer dielectric film in the second region, forming a first sacrificial layer pattern on the first metal layer such that the first sacrificial layer fills a portion of the first trench, forming a first electrode layer by etching the first metal layer and the second metal layer using the first sacrificial layer pattern, and removing the first sacrificial layer pattern.
    Type: Grant
    Filed: June 19, 2012
    Date of Patent: December 31, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Chan Lee, Yoo-Jung Lee, Ki-Hyung Ko, Dae-Young Kwak, Seung-Jae Lee, Jae-Sung Hur, Sang-Bom Kang, Cheol Kim, Bo-Un Yoon
  • Patent number: 8592910
    Abstract: A semiconductor body includes a protective structure. The protective structure (10) includes a first and a second region (11, 12) which have a first conductivity type and a third region (13) that has a second conductivity type. The second conductivity type is opposite the first conductivity type. The first and the second region (11, 12) are arranged spaced apart in the third region (13), so that a current flow from the first region (11) to the second region (12) is made possible for the limiting of a voltage difference between the first and the second region (11, 12). The protective structure includes an insulator (14) that is arranged on the semiconductor body (9) and an electrode (16) that is constructed with floating potential and is arranged on the insulator (14).
    Type: Grant
    Filed: September 16, 2009
    Date of Patent: November 26, 2013
    Assignee: AMS AG
    Inventor: Hubert Enichlmair
  • Patent number: 8557653
    Abstract: A method of manufacturing a junction-field-effect-transistor (JFET) device, the method includes the steps of providing a substrate of a first-type impurity; forming a first well region of a second-type impurity in the substrate; forming a second well region and a third well region of the first-type impurity separated from each other in the first well region; forming a fourth well region of the first-type impurity between the second well region and the third well region; forming a first diffused region of the second-type impurity between the second well region and the fourth well region; forming a second diffused region of the second-type impurity between the third well region and the fourth well region; forming a pair of first doped regions of the second-type impurity in the first well region, and a pair of second doped regions of the first-type impurity in the second well region and the third well region respectively; forming a third doped region of the second-type impurity in the first well region between t
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: October 15, 2013
    Assignee: Macronix International Co., Ltd.
    Inventors: Chih-Min Hu, Chung Yu Hung, Wing Chor Chan, Jeng Gong
  • Patent number: 8507356
    Abstract: Semiconductor device manufacturing method includes forming a first mask, having a first opening to implant ion into semiconductor substrate and being used to form first layer well, on semiconductor substrate; forming first-layer well having first and second regions by implanting first ion into semiconductor substrate using first mask; forming second mask, having second opening to implant ion into semiconductor substrate and being used to form second layer well, on semiconductor substrate; and forming second-layer well below first layer well by implanting second ion into semiconductor substrate using second mask. First region is formed closer to an edge of first-layer well than second region. Upon implanting first ion, first ion deflected by first inner wall of first mask is supplied to first region. Upon implanting second ion, second ion deflected by second inner wall of second mask is supplied to second region.
    Type: Grant
    Filed: November 16, 2011
    Date of Patent: August 13, 2013
    Assignee: Elpida Memory, Inc.
    Inventor: Noriaki Ikeda
  • Patent number: 8501603
    Abstract: A method for fabricating a high voltage transistor includes the following steps. Firstly, a substrate is provided. A first sacrificial oxide layer and a hard mask layer are sequentially formed over the substrate. The hard mask layer is removed, thereby exposing the first sacrificial oxide layer. Then, a second sacrificial oxide layer is formed on the first sacrificial oxide layer. Afterwards, an ion-implanting process is performed to introduce a dopant into the substrate through the second sacrificial oxide layer and the first sacrificial oxide layer, thereby producing a high voltage first-type field region of the high voltage transistor.
    Type: Grant
    Filed: June 15, 2011
    Date of Patent: August 6, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Chih-Kuang Chang, Hsin-Hsueh Hsieh
  • Patent number: 8470674
    Abstract: A structure, method and system for complementary strain fill for integrated circuit chips. The structure includes a first region of an integrated circuit having multiplicity of n-channel and p-channel field effect transistors (FETs); a first stressed layer over n-channel field effect transistors (NFETs) of the first region, the first stressed layer of a first stress type; a second stressed layer over p-channel field effect transistors (PFETs) of the first region, the second stressed layer of a second stress type, the second stress type opposite from the first stress type; and a second region of the integrated circuit, the second region not containing FETs, the second region containing first sub-regions of the first stressed layer and second sub-regions of the second stressed layer.
    Type: Grant
    Filed: January 3, 2011
    Date of Patent: June 25, 2013
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Edward J. Nowak, Jed H. Rankin
  • Patent number: 8441070
    Abstract: A sinker layer is in contact with a first conductivity-type well, and is separated from a first conductivity-type collector layer and a second conductivity-type drift layer. A second conductivity-type diffusion layer (second second-conductivity-type high-concentration diffusion layer) is formed in the surface layer of the sinker layer. The second conductivity-type diffusion layer has a higher impurity concentration than that of the sinker layer. The second conductivity-type diffusion layer and the first conductivity-type collector layer are isolated from each other with an element isolation insulating film interposed therebetween.
    Type: Grant
    Filed: August 6, 2012
    Date of Patent: May 14, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Hiroki Fujii
  • Patent number: 8426265
    Abstract: A method of manufacturing a complementary metal oxide semiconductor (CMOS) circuit, in which the method includes a reactive ion etch (RIE) of a CMOS circuit substrate that forms recesses, the CMOS circuit substrate including: an n-type field effect transistor (n-FET) region; a p-type field effect transistor (p-FET) region; an isolation region disposed between the n-FET and p-FET regions; and a gate wire comprising an n-FET gate, a p-FET gate, and gate material extending transversely from the n-FET gate across the isolation region to the p-FET gate, in which the recesses are formed adjacent to sidewalls of a reduced thickness; growing silicon germanium (SiGe) in the recesses; depositing a thin insulator layer on the CMOS circuit substrate; masking at least the p-FET region; removing the thin insulator layer from an unmasked n-FET region and an unmasked portion of the isolation region; etching the CMOS circuit substrate with hydrogen chloride (HCl) to remove the SiGe from the recesses in the n-FET region; and g
    Type: Grant
    Filed: November 3, 2010
    Date of Patent: April 23, 2013
    Assignees: International Business Machines Corporation, GlobalFoundries, Inc.
    Inventors: Bo Bai, Linda Black, Abhishek Dube, Judson R. Holt, Viorel C. Ontalus, Kathryn T. Schonenberg, Matthew W. Stoker, Keith H. Tabakman
  • Patent number: 8409787
    Abstract: A method of forming a pattern in a semiconductor device is described. A substrate divided into cell and peripheral regions is provided, and an object layer is formed on a substrate. A buffer pattern is formed on the object layer in the cell region along a first direction. A spacer is formed along a sidewall of the buffer pattern in the cell region, and a hard mask layer remains on the object layer in the peripheral region. The buffer layer is removed, and the spacer is separated along a second direction different from the first direction, thereby forming a cell hard mask pattern. A peripheral hard mask pattern is formed in the peripheral region. A minute pattern is formed using the cell and peripheral hard mask patterns in the substrate. Therefore, a line width variation or an edge line roughness due to the photolithography process is minimized.
    Type: Grant
    Filed: March 7, 2011
    Date of Patent: April 2, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Choong-Ryul Ryou, Hee-Sung Kang
  • Patent number: 8410568
    Abstract: A substrate section that is at least partially fabricated to include contact elements and materials. The substrate section includes doped regions that have a heavily doped N-type region and a heavily doped P-type region adjacent to one another. An exterior surface of the substrate has a topography that includes a light-transparent region in which light, from a light source, is able to reach a surface of the substrate. An application of light onto the light transparent region is sufficient to cause a voltage potential to form across a junction of the heavily doped regions. The substrate section may further comprise one or more electrical contacts, positioned on the substrate section to conduct current, resulting from the voltage potential created with application of light onto the light transparent region, to a circuit on the semiconductor substrate.
    Type: Grant
    Filed: August 25, 2009
    Date of Patent: April 2, 2013
    Assignee: Tau-Metrix, Inc.
    Inventors: Gary Steinbrueck, James S. Vickers, Mario M. Pelella, Majid Aghababazadeh, Nader Pakdaman
  • Patent number: 8372703
    Abstract: A method for fabricating a CMOS integrated circuit (IC) and ICs therefrom includes the steps of providing a substrate having a semiconductor surface, wherein the semiconductor surface has PMOS regions for PMOS devices and NMOS regions for NMOS devices. A gate dielectric layer is formed on the PMOS regions and NMOS regions. An original gate electrode layer is formed on the gate dielectric layer. A gate masking layer is applied on the gate electrode layer. Etching is used to pattern the original gate electrode layer to simultaneously form original gate electrodes for the PMOS devices and NMOS devices. Source and drain regions are formed for the PMOS devices and NMOS devices. The original gate electrodes are removed for at least one of the PMOS devices and NMOS devices to form trenches using an etch process, such as a hydroxide-based solution, wherein at least a portion and generally substantially all of the gate dielectric layer is preserved.
    Type: Grant
    Filed: October 20, 2010
    Date of Patent: February 12, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Brian K. Kirkpatrick, Freidoon Mehrad, Shaofeng Yu
  • Patent number: 8325516
    Abstract: A split gate memory cell. First and second well regions of respectively first and second conductivity types are formed in the substrate. A floating gate is disposed on a junction of the first and second well regions and insulated from the substrate. A control gate is disposed over the sidewall of the floating gate and insulated from the substrate and the floating gate and partially extends to the upper surface of the floating gate. A doping region of the first conductivity type is formed in the second well region. The first well region and the doping region respectively serve as source and drain regions of the split gate memory cell.
    Type: Grant
    Filed: October 22, 2009
    Date of Patent: December 4, 2012
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yue-Der Chih, Shine Chung, Wen-Ting Chu
  • Patent number: 8324041
    Abstract: Electron mobility and hole mobility is improved in long channel semiconductor devices and resistors by employing complementary stress liners. Embodiments include forming a long channel semiconductor device on a substrate, and forming a complementary stress liner on the semiconductor device. Embodiments include forming a resistor on a substrate, and tuning the resistance of the resistor by forming a complementary stress liner on the resistor. Compressive stress liners are employed for improving electron mobility in n-type devices, and tensile stress liners are employed for improving hole mobility in p-type devices.
    Type: Grant
    Filed: February 9, 2011
    Date of Patent: December 4, 2012
    Assignee: Globalfoundries Inc.
    Inventors: Stefan Flachowsky, Jan Hoentschel, Thilo Scheiper
  • Patent number: 8264037
    Abstract: A sinker layer is in contact with a first conductivity-type well, and is separated from a first conductivity-type collector layer and a second conductivity-type drift layer. A second conductivity-type diffusion layer (second second-conductivity-type high-concentration diffusion layer) is formed in the surface layer of the sinker layer. The second conductivity-type diffusion layer has a higher impurity concentration than that of the sinker layer. The second conductivity-type diffusion layer and the first conductivity-type collector layer are isolated from each other with an element isolation insulating film interposed therebetween.
    Type: Grant
    Filed: January 20, 2012
    Date of Patent: September 11, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Hiroki Fujii
  • Patent number: 8252642
    Abstract: Semiconductor devices can be fabricated using conventional designs and process but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. Such semiconductor devices can include one or more parasitic isolation devices and/or buried layer structures disclosed in the present application. The introduction of design and/or process steps to accommodate these novel structures is compatible with conventional CMOS fabrication processes, and can therefore be accomplished at relatively low cost and with relative simplicity.
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: August 28, 2012
    Assignee: Silicon Space Technology Corp.
    Inventor: Wesley H. Morris
  • Patent number: 8243770
    Abstract: Emissive quantum photonic imagers comprised of a spatial array of digitally addressable multicolor pixels. Each pixel is a vertical stack of multiple semiconductor laser diodes, each of which can generate laser light of a different color. Within each multicolor pixel, the light generated from the stack of diodes is emitted perpendicular to the plane of the imager device via a plurality of vertical waveguides that are coupled to the optical confinement regions of each of the multiple laser diodes comprising the imager device. Each of the laser diodes comprising a single pixel is individually addressable, enabling each pixel to simultaneously emit any combination of the colors associated with the laser diodes at any required on/off duty cycle for each color. Each individual multicolor pixel can simultaneously emit the required colors and brightness values by controlling the on/off duty cycles of their respective laser diodes.
    Type: Grant
    Filed: October 21, 2011
    Date of Patent: August 14, 2012
    Assignee: Ostendo Technologies, Inc.
    Inventors: Hussein S. El-Ghoroury, Robert G. W. Brown, Dale A. McNeill, Huibert DenBoer, Andrew J. Lanzone
  • Patent number: 8120104
    Abstract: A sinker layer is in contact with a first conductivity-type well, and is separated from a first conductivity-type collector layer and a second conductivity-type drift layer. A second conductivity-type diffusion layer (second second-conductivity-type high-concentration diffusion layer) is formed in the surface layer of the sinker layer. The second conductivity-type diffusion layer has a higher impurity concentration than that of the sinker layer. The second conductivity-type diffusion layer and the first conductivity-type collector layer are isolated from each other with an element isolation insulating film interposed therebetween.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: February 21, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Hiroki Fujii
  • Patent number: 8071436
    Abstract: Methods and systems for monolithically fabricating a lateral double-diffused MOSFET (LDMOS) transistor having a source, drain, and a gate on a substrate, with a process flow that is compatible with a CMOS process flow are described. In some implementations, a method of fabricating a semiconductor device is provided that includes forming an LDMOS transistor having a first drain with a first drain-side n+ region, a first source with a first source-side n+ region and a first source-side p+ region, and a first gate between the first drain and the first source on the substrate. The method also includes forming an n-type CMOS transistor having a second drain having a second drain-side n+ region, a second source having a second source-side n+ region, and a second gate between the second drain and the second source. In so doing, the LDMOS transistor can be fabricated through a process that can be seamlessly integrated into a sub-micron CMOS process.
    Type: Grant
    Filed: March 1, 2010
    Date of Patent: December 6, 2011
    Assignee: Volterra Semiconductor Corporation
    Inventors: Budong You, Marco A. Zuniga
  • Patent number: 8053306
    Abstract: A PFET having tailored dielectric constituted in part by an NFET threshold voltage (Vt) work function tuning layer in a gate stack thereof, related methods and integrated circuit are disclosed. In one embodiment, the PFET includes an n-type doped silicon well (N-well), a gate stack including: a doped band engineered PFET threshold voltage (Vt) work function tuning layer over the N-well; a tailored dielectric layer over the doped band engineered PFET Vt work function tuning layer, the tailored dielectric layer constituted by a high dielectric constant layer over the doped band engineered PFET Vt work function tuning layer and an n-type field effect transistor (NFET) threshold voltage (Vt) work function tuning layer over the high dielectric constant layer; and a metal over the NFET Vt work function tuning layer.
    Type: Grant
    Filed: December 13, 2007
    Date of Patent: November 8, 2011
    Assignees: International Business Machines Corporation, Advanced Micro Devices, Inc.
    Inventors: Rick Carter, Michael P. Chudzik, Rashmi Jha, Naim Moumen
  • Patent number: 8049231
    Abstract: Emissive quantum photonic imagers comprised of a spatial array of digitally addressable multicolor pixels. Each pixel is a vertical stack of multiple semiconductor laser diodes, each of which can generate laser light of a different color. Within each multicolor pixel, the light generated from the stack of diodes is emitted perpendicular to the plane of the imager device via a plurality of vertical waveguides that are coupled to the optical confinement regions of each of the multiple laser diodes comprising the imager device. Each of the laser diodes comprising a single pixel is individually addressable, enabling each pixel to simultaneously emit any combination of the colors associated with the laser diodes at any required on/off duty cycle for each color. Each individual multicolor pixel can simultaneously emit the required colors and brightness values by controlling the on/off duty cycles of their respective laser diodes.
    Type: Grant
    Filed: March 19, 2010
    Date of Patent: November 1, 2011
    Assignee: Ostendo Technologies, Inc.
    Inventors: Hussein S. El-Ghoroury, Robert G. W. Brown, Dale A. McNeill, Huibert DenBoer, Andrew J. Lanzone
  • Patent number: 8026135
    Abstract: A process for forming diffused region less than 20 nanometers deep with an average doping dose above 1014 cm?2 in an IC substrate, particularly LDD region in an MOS transistor, is disclosed. Dopants are implanted into a source dielectric layer using gas cluster ion beam (GCIB) implantation, molecular ion implantation or atomic ion implantation resulting in negligible damage in the IC substrate. A spike anneal or a laser anneal diffuses the implanted dopants into the IC substrate. The inventive process may also be applied to forming source and drain (S/D) regions. One source dielectric layer may be used for forming both NLDD and PLDD regions.
    Type: Grant
    Filed: August 12, 2008
    Date of Patent: September 27, 2011
    Assignee: Texas Instruments Incorporated
    Inventor: Amitabh Jain
  • Patent number: 8013381
    Abstract: A semiconductor device has a semiconductor substrate of a first conductivity type; first to third high-voltage insulated-gate field effect transistors formed on a principal surface of the semiconductor substrate; a first device isolation insulating film that is formed in the semiconductor substrate and isolates the first high-voltage insulated-gate field effect transistor and the second high-voltage insulated-gate field effect transistor from each other; a second device isolation insulating film that is formed in the semiconductor substrate and isolates the first high-voltage insulated-gate field effect transistor and the third high-voltage insulated-gate field effect transistor from each other; a first impurity diffusion layer of the first conductivity type that is formed below the first device isolation insulating film; and a second impurity diffusion layer of the first conductivity type that is formed below the second device isolation insulating film.
    Type: Grant
    Filed: January 28, 2009
    Date of Patent: September 6, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Norio Magome, Toshifumi Minami, Tomoaki Hatano, Norihisa Arai
  • Patent number: 7999327
    Abstract: In a semiconductor substrate having a first well of a conductivity type opposite to that of the semiconductor substrate, formed on part of a main surface of the semiconductor substrate, a second well of the same conductivity type as the semiconductor substrate, formed on part of a surface region of the first well shallower than the first well, and a third well of a conductivity type opposite to that of the semiconductor substrate, formed in a surface region of the first well, in a region where the second well is not formed and shallower than the first well, by having a fourth well, formed in a region of the main surface of the semiconductor substrate where the first well is not formed and doped with impurities of the same conductivity type as the semiconductor substrate at a lower concentration than the third well, and controlling a reference voltage to be low, it is possible suppress the occurrence of a latch up phenomenon.
    Type: Grant
    Filed: November 30, 2005
    Date of Patent: August 16, 2011
    Assignee: Sanyo Electric Co., Ltd.
    Inventor: Akinao Kitahara
  • Patent number: 7998798
    Abstract: A method of cutting an electrical fuse including a first conductor and a second conductor, the first conductor including a first cutting target region, the second conductor branched from the first conductor and connected to the first conductor and including a second cutting target region, which are formed on a semiconductor substrate, the method includes flowing a current in the first conductor, causing material of the first conductor to flow outward near a coupling portion connecting the first conductor to the second conductor, and cutting the first cutting target region and the second cutting target region.
    Type: Grant
    Filed: March 2, 2010
    Date of Patent: August 16, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Takehiro Ueda
  • Patent number: 7972917
    Abstract: A method for manufacturing a semiconductor device is disclosed. The method includes: forming a LDMOS region, an offset drain MOS region, and a CMOS region; simultaneously forming a first well in the LDMOS region and the offset drain MOS region; simultaneously forming a second well in the first well of the LDMOS region and the CMOS region; and forming a second well in the CMOS region, wherein a depth of the first well is larger than a depth of the second well and the second well is a retrograde well formed by a high energy ion implantation method.
    Type: Grant
    Filed: June 25, 2009
    Date of Patent: July 5, 2011
    Assignee: Seiko Epson Corporation
    Inventors: Tomoyuki Furuhata, Hideyuki Akanuma, Hiroaki Nitta
  • Patent number: 7955924
    Abstract: Example embodiments disclose an image sensor capable of preventing or reducing image lag and a method of manufacturing the same. Example methods may include forming a gate insulating film and a gate conductive film doped with a first-conductive-type dopant on a semiconductor substrate; forming a transfer gate pattern by patterning the gate insulating film and the gate conductive film; and fabricating a transfer gate electrode by forming a first-conductive-type photodiode in the semiconductor substrate adjacent to one region of the transfer gate pattern, by forming a second-conductive-type photodiode on the first-conductive-type photodiode, and by forming a first-conductive-type floating diffusion region in the semiconductor substrate adjacent to the other region of the transfer gate pattern.
    Type: Grant
    Filed: January 10, 2007
    Date of Patent: June 7, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-ho Song, Chan Park, Young-hoon Park, Sang-il Jung, Jong-wook Hong, Keo-sung Park, Eun-soo Kim, Won-je Park, Jin-Hyeong Park, Dae-cheol Seong, Won-jeong Lee, Pu-ra Kim
  • Patent number: 7914973
    Abstract: A method of forming a pattern in a semiconductor device is described. A substrate divided into cell and peripheral regions is provided, and an object layer is formed on a substrate. A buffer pattern is formed on the object layer in the cell region along a first direction. A spacer is formed along a sidewall of the buffer pattern in the cell region, and a hard mask layer remains on the object layer in the peripheral region. The buffer layer is removed, and the spacer is separated along a second direction different from the first direction, thereby forming a cell hard mask pattern. A peripheral hard mask pattern is formed in the peripheral region. A minute pattern is formed using the cell and peripheral hard mask patterns in the substrate. Therefore, a line width variation or an edge line roughness due to the photolithography process is minimized.
    Type: Grant
    Filed: June 25, 2008
    Date of Patent: March 29, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Choong-Ryul Ryou, Hee-Sung Kang
  • Patent number: 7902020
    Abstract: A semiconductor device includes a first conductivity-type deep well formed in a substrate, a plurality of device isolation layers formed in the substrate in which the first conductivity-type deep well is formed, a second conductivity-type well formed on a portion of the first conductivity-type deep well between two of the device isolation layers, a first gate pattern formed over a portion of the second conductivity-type well, a second gate pattern formed over one of the device isolation layers, a source region formed in an upper surface of the second conductivity-type well to adjoin a first side of the first gate pattern, a first drain region formed to include the interface between an upper surface of the second conductivity-type well adjoining a second side of the first gate pattern and an upper surface of the first conductivity-type deep well adjoining the second side of the first gate pattern, and a second drain region formed in an upper surface of the first conductivity-type deep well to be spaced from th
    Type: Grant
    Filed: October 1, 2009
    Date of Patent: March 8, 2011
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Il-Yong Park
  • Patent number: 7892914
    Abstract: In a method for manufacturing a semiconductor device, an insulating film is formed on an entire surface of a substrate having a device isolation region and a first and a second conductive region. Then, a semiconductor device structure having a gate electrode forming region is formed on each of the conductive regions, the insulating film being disposed between the gate electrode forming region and each of the conductive regions. A gate electrode groove is formed in the gate electrode forming region of the semiconductor device structure, the insulating film being removed in the gate electrode groove. Thereafter, a gate insulating film and a film of metal gate electrode material are deposited on a bottom surface and a side surface of the gate electrode groove and an alloy is formed by alloying the film of metal gate electrode material deposited in a gate electrode groove of the first conductive region.
    Type: Grant
    Filed: February 9, 2007
    Date of Patent: February 22, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Genji Nakamura, Yasushi Akasaka
  • Patent number: 7868387
    Abstract: A high-voltage, low-leakage, bidirectional electrostatic discharge (ESD, or other electrical overstress) protection device includes a doped well disposed between the terminal regions and the substrate. The device includes an embedded diode for conducting current in one direction, and a transistor feedback circuit for conducting current in the other direction. Variations in the dimensions and doping of the doped well, as well as external passive reference via resistor connections, allow the circuit designer to flexibly adjust the operating characteristics of the device, such as trigger voltage and turn-on speed, to suit the required mixed-signal operating conditions.
    Type: Grant
    Filed: June 13, 2008
    Date of Patent: January 11, 2011
    Assignee: Analog Devices, Inc.
    Inventors: Javier A. Salcedo, Jean-Jacques Hajjar, Todd Thomas
  • Patent number: 7863688
    Abstract: Layout patterns for the deep well region to facilitate routing the body-bias voltage in a semiconductor device are provided and described. The layout patterns include a diagonal sub-surface mesh structure, an axial sub-surface mesh structure, a diagonal sub-surface strip structure, and an axial sub-surface strip structure. A particular layout pattern is selected for an area of the semiconductor device according to several factors.
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: January 4, 2011
    Inventors: Mike Pelham, James B. Burr
  • Patent number: 7847349
    Abstract: In accordance with exemplary embodiments, a Fast Fourier Transform (FFT) architecture includes elements that perform a radix-2 FFT butterfly in one processor clock cycle at steady state. Some exemplary implementations of the FFT architecture incorporate register and data path elements that relieve memory bandwidth limitations by pairing operands consumed by and results generated by two adjacent butterflies in the overall N-point FFT operation.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: December 7, 2010
    Assignee: Agere Systems Inc.
    Inventor: Matthew R. Henry
  • Patent number: 7833857
    Abstract: An ESD protecting circuit and a manufacturing method thereof are provided. The ESD protecting circuit includes a device isolation layer, first and second high-concentration impurity regions, a third high-concentration impurity region of a complementary type, first and second conductive wells, and a fourth conductive impurity region. The ESD protecting circuit is configured as a field transistor without a gate electrode, and the high breakdown voltage characteristics of the field transistor are lowered by implanting impurity ions, providing an ESD protecting circuit with a low breakdown voltage and low leakage current. Because the leakage current is reduced, the ESD protecting circuit can be used for an analog I/O device that is sensitive to current fluxes. Also, an N-type well may protect a junction of the field transistor.
    Type: Grant
    Filed: September 1, 2009
    Date of Patent: November 16, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: San Hong Kim
  • Patent number: 7825768
    Abstract: A resistor circuit includes first to Mth resistor circuit units. A (2j?1)th resistor circuit unit includes a (2j?1)th first fuse element and a (2j?1)th resistor provided in series between a (2j?1)th node and a 2jth node, and a (2j?1)th second fuse element provided in parallel with the (2j?1)th first fuse element and the (2j?1)th resistor between the (2j?1)th node and the 2jth node. A 2jth resistor circuit unit includes a 2jth first fuse element and a 2jth resistor provided in series between the 2jth node and a (2j+1)th node, and a 2jth second fuse element that is provided in parallel with the 2jth first fuse element and the 2jth resistor between the 2jth node and the (2j+1)th node. The (2j?1)th first fuse element, the (2j?1)th second fuse element, the 2jth first fuse element, and the 2jth second fuse element are disposed in a fuse region. The (2j?1)th resistor is disposed in a first resistor region formed in a first direction with respect to the fuse region.
    Type: Grant
    Filed: February 12, 2008
    Date of Patent: November 2, 2010
    Assignee: Seiko Epson Corporation
    Inventor: Kota Onishi