Abstract: A field emission display and a method for fabricating the same are disclosed. The method includes the steps of: forming a silicon mold; growing a diamond on the silicon mold, to form a diamond tip; forming a conductive layer on the diamond tip; bonding a first substrate to the conductive layer; removing the silicon mold; forming a gate insulating layer and gate electrode on the diamond tip; and etching the gate electrode and gate insulating layer to expose an electron emission portion of the tip, and thereby form a gate hole. By doing so, the operation voltage is reduced, compared with the diode-type display, and high-responsibility field emission display can be realized by applying (-) or (+) voltage to the gate electrode.

Abstract: Disclosed is a manufacturing method of semiconductor device which can simplify the manufacturing procedures for transistors with different gate insulation film thickness in the same substrate. According to the present invention, a manufacturing method for semiconductor device having NMOS and PMOS transistors with gate insulation films of different thickness from each other, is formed by the following processes. First, a semiconductor substrate in which a low voltage NMOS transistor region, a high voltage NMOS transistor region, a low voltage PMOS transistor region, and a high voltage PMOS transistor region are defined by isolation films, is provided. Next, a N well is formed in the low and high voltage PMOS transistor regions and threshold voltage adjustment ions for high voltage PMOS transistor are then implanted into the N well.

Abstract: The method of manufacturing a CMOS transistor according to the present invention comprises the steps of forming a field oxide at a selected region on a semiconductor substrate to isolate a first region for a NMOS transistor from a second region for a PMOS transistors; forming a P-well region and a N-well region in the first and second regions, respectively; forming a gate oxide film and a gate electrode on selected regions of the first and second regions; implanting low concentration N-type impurities ions to form low concentration impurity implantation regions within the first and second regions; forming spacers at said side walls of the gate electrode and the gate oxide film; forming a high concentration implantation region in the first and second regions; and implanting N-type impurity ions into the second region to form a punch stop doping layer below said low concentration impurity implantation region of the second region.

Abstract: A method of making semiconductor devices which enables control of the impurity concentration and fine patterning by making removal of residual stress due LOCOS oxidation compatible with the formation of deep wells. A selective oxide layer is formed for separating element regions on a principal plane of a semiconductor substrate, for example, a p.sup.- -type silicon substrate 1. A mask is formed (for example photoresist 47) on the surface including the selective oxide layer and impurities (for example phosphorous) of a conductivity type opposite that of the semiconductor substrate are introduced via an opening in the mask. Then the selective oxide film is annealed by a high-temperature treatment while a deep well (for example n-type deep well 50) is formed by introducing the impurities.

Abstract: A method of forming an isolation structure comprising forming n-type areas and/or p-type areas implanted respectively therein on a first surface of the substrate. A pad oxide film is grown on the substrate first surface covering the p-wells and/or n-wells. A diffusion barrier(s) is deposited on the substrate first surface and a substrate second surface to form an encapsulated structure. The encapsulated structure is annealed to activate the n-type and/or p-type areas. A mask material is applied over the diffusion barrier on the substrate first surface to define active device areas and a dry etch process is used to etch away the unmasked portions of the diffusion barrier. The mask material is stripped and a field oxide is grown on the substrate first surface. A portion of the field oxide and all of the diffusion barrier is removed, resulting in active areas surrounded by a field isolation structure.

Abstract: The present invention relates to a method for fabricating semiconductor devices having triple wells, the present invention has an effect as follows. The present invention provides carrying out N-well and P-well and R-well ion implantation using a mask for implanting two wells after forming an element isolation oxide film, defining an accurate well region by forming wells having an accurate profile due to activating impurity ions in accordance with the thermal process, and improving the punch characteristic between a well and a well.

Abstract: A semiconductor device include: a substrate of a conductivity type; a first well provided in the substrate and of the same conductivity type as the conductivity type of the substrate; a second well provided in the substrate and of an opposite conductivity type to the conductivity type of the substrate; and a buried well provided at a deep position in the substrate and of the opposite conductivity type to the conductivity type of the substrate. A buried well of the same conductivity type as the conductivity type of the substrate is further provided so as to be in contact with at least a part of a bottom portion of the first well so that the first well is at least partially electrically connected to the substrate.

Abstract: A method of fabricating a transistor is provided. According to the method, a heavy ion is implanted into a silicon substrate so as to amorphize at least a portion of the silicon substrate. The amorphized silicon is substantially free of channels. A dopant is subsequently implanted into the amorphized silicon, and the amorphized silicon substantially contains the implanted dopant. Thereafter, a silicon implanting step is performed to create an excess of vacancies to interstitials within a predetermined range. Enhanced diffusion of the dopant within the predetermined range is mitigated because of the excess of vacancies to interstitials within this predetermined range.

Abstract: An IC comprises a tub of a first conductivity type, at least one transistor embedded in the tub, and a first pair of isolating regions defining therebetween a tub-tie region coupled to the tub. The tub-tie region comprises a cap portion of the first conductivity type and an underlying buried pedestal portion of a second conductivity type. At least a top section of the pedestal portion is surrounded by the cap portion so that a conducting path is formed between the cap portion and the tub. In a CMOS IC tub-ties of this design are provided for both NMOS and PMOS transistors. In a preferred embodiment, the cap portion of each tub-tie comprises a relatively heavily doped central section and more lightly doped peripheral sections, both of the same conductivity type.

Abstract: According to one embodiment, a memory device comprises a bit line operable to access a memory cell. The bit line has a first end and a second end. A first equilibration circuit is coupled to the first end of the bit line, and a second equilibration circuit is coupled to the second end of the bit line. The first and second equilibration circuits cooperate to pre-charge the bit line. According to another embodiment, an embedded-process memory device comprises a p-well and a deep n-well formed into a substrate. A retrograde well is formed into the deep n-well. An equilibration circuit for pre-charging a bit line is formed into the retrograde well.

Abstract: A method for fabricating a CMOS integrated circuit device with less masking steps than a conventional device. The present method includes a step of providing a semiconductor substrate with a well region, a gate dielectric layer, and a polysilicon gate electrode. The gate dielectric layer is overlying the well region, and the polysilicon gate electrode is overlying the gate dielectric layer. The present method also includes forming a first thermal oxide thickness overlying the polysilicon gate electrode layer and a second thermal oxide thickness overlying exposed regions. The first thermal oxide thickness is greater than the second thermal oxide thickness, and both layers are defined during the same step. A mask exposes first LDD regions and first source drain regions.

Abstract: A twin tub integrated circuit and method for its formation are disclosed. A portion of the substrate is covered by photoresist while an n region is formed, illustratively, by ion implantation. Then the n region is covered with a protective material, illustratively a spin on glass or another photoresist. The previously-formed photoresist is removed and a p-type implant is performed to create an p region. When all the protective layers are removed, both regions have upper surfaces which are co-planar. The co-planar surfaces, a departure from previous practice, make submicron lithography easier. The regions are annealed to form twin tubs.

Abstract: A method of improving latch-up immunity and interwell isolation in a semiconductor device is provided. In one embodiment, an implant mask which has a variable permeability to implanted impurities is formed on the surface of a substrate having a first dopant region. A first portion of the implant mask overlies a first portion of the first dopant region. The structure is subjected to high energy implantation which forms a heavily doped region. A first portion of the heavily doped region is located along the lower boundary of the first dopant region. A second portion of the heavily doped region which extends along a side boundary of the first dopant region is formed by impurity ions which pass through the first portion of the implant mask. The heavily doped region improves latch-up immunity and interwell isolation without degrading threshold voltage tolerance.

Abstract: The present invention provide a method for forming a triple well. The triple well includes an n-well, a first p-well surrounded with the n-well and a second p-well apart from the first p-well and adjacent to the n-well. According to the present invention, only one conductivity type of impurities are implanted in each well. Therefore, it is possible to prevent the decrease of the carrier mobility and increase of the leakage current.

Abstract: A method was achieved for fabricating field oxide regions (shallow trench isolation) having raised portions which are self-aligned and extend over edges of device areas. This results in FETs with improved sub-threshold characteristics and lower sub-threshold leakage currents. The method consists of forming a pad oxide and depositing a doped polysilicon layer and a hard mask layer on a silicon substrate. Shallow trenches are etched through the hard mask, doped polysilicon layer and partially into the silicon substrate. A thermal oxidation is used to form a liner oxide in the trenches and to oxidize, at a higher oxidation rate, the sidewalls of the doped polysilicon layer to form an oxide over the edges of the device areas. A gap-fill oxide is deposited in the trenches and chemical mechanical polished (CMP) back to the polysilicon layer. The remaining polysilicon layer over the device areas is selectively removed to provide a field oxide having raised portions formed over the edges of the device areas.

Abstract: The present invention includes forming an oxide layer, nitride on a substrate. An ion implantation is performed. A LPD-oxide is formed on P well. Subsequently, an ion implantation to dope phosphorus into the substrate to form N well. Then, the LPD-oxide is removed. The oxide layer and the silicon nitride layer are respectively removed. Subsequently, a thin gate oxide is regrown on the surface of the substrate. A polysilicon layers, a second nitride are deposited on the oxide layer. Polysilicon gates are patterned. An ion implantation is carried out to implant arsenic into the P well. A thin LPD-oxide is forged along the surface of the gate, the substrate on the P well. A thermal anneal process is used to condense the LPD-oxide. Simultaneously, an ultra thin silicon oxynitride layer is formed on the surface of N well. Next, BSG side wall spacers are formed on the side walls of the gates. The silicon nitride layer is removed.

Abstract: A twin well forming method for a semiconductor device includes the steps of forming a first insulation layer on a semiconductor substrate, selectively etching the first insulation layer to obtain a first insulation layer pattern and a first buffer insulation, ion-implanting first impurities through the first buffer insulation layer into the semiconductor substrate, forming a second insulation layer on the first insulation layer pattern and the first buffer insulation layer, spreading a planarizing material on the second insulation layer and applying the planarizing material to an annealing treatment to obtain a planarizing material layer, etching back the planarizing material layer and the second insulation layer to expose an upper surface of the first insulation layer pattern, forming a second buffer insulation layer by partially etching the first insulation layer pattern, ion-implanting second impurities through the second buffer insulation layer into the semiconductor substrate, removing the second insulat

Abstract: A triple-well structure for semiconductor IC devices such as an SRAM IC device and a process for its fabrication, that allows for improved data storage stability as well as improved immunity capability against interference from device I/O bouncing and alpha particles. The triple-well structure includes at least one P-well in a P-type substrate, a number of N-wells, and a retrograde P-well formed within one of the N-wells. The process for fabricating the triple-well structure includes first implanting boron ions in the P-type substrate. A photomask is subsequently formed for the implantation of phosphorous ions in the region where a P-type MOS transistor is to be fabricated. A high temperature drive-in procedure is then employed to form a P-well and a number of N-wells. A selected area of one of the N-wells where an N-type MOS transistor is defined is then subjected to boron ion implantation, which is followed by an annealing procedure to form the retrograde P-well.

Abstract: A method for forming wells of a semiconductor device, comprising the steps of forming a plurality of field insulating layers on a field region of a semiconductor substrate; forming first impurity regions of a first conductive type at a first depth beneath a surface of the semiconductor substrate; forming first impurity regions of a second conductive type beneath the surface of the semiconductor substrate at a second depth between the field insulating layers; selectively forming second impurity regions of the second conductive type in the first impurity regions of the first conductive type between adjacent field insulating layers; forming second impurity regions of the first conductive type in the first impurity regions of the second conductive type at both sides of the second impurity regions of the second conductive type; and diffusing the first and second impurity regions of the first conductive type and the first and second impurity regions of the second conductive type by a drive-in process to form a firs

Abstract: A method for fabricating a high-bias device compatible with a low-bias device is provided. The method of the invention includes using a doped well as a drift region of the high-bias device so that the drift region can be formed simultaneously when a well for a low-bias device is formed. The method of the invention also fabricates the high-bias device and the low-bias device simultaneously, using a commonly used photomask. Several ion implantation processes are also performed simultaneously. There is no need of some extra fabrication of photomasks and ion implantation processes separately used for forming the high-bias device.

Abstract: A method for fabricating high-voltage semiconductor devices is disclosed, in which a P-well and a N-well are first formed over the substrate, where a plurality of P-wells and N-wells used as isolation regions and drift regions are further formed therein. More shallot P-type and N-type regions are subsequently formed in the drift regions and isolation regions, so as to increase the breakdown voltage and enhance the current-driving performance. In addition, a deepened isolation doping, can also increase the latch up capability, resulting in less area required for fabricating a device.

Abstract: A method of forming a self-aligned halo-isolated well with a single mask is disclosed. First, a layer of resist is disposed over at least a portion of a substrate's surface. Then, an impurity of a first polarity type is implanted at an angle into the substrate through a gap in the layer of resist, thus forming a well having the impurity of the first polarity, which extends beneath the layer of resist. An impurity of a second polarity type is also implanted, using the same mask as previously used. The second implantation forms a well of the impurity of the second polarity disposed within the well of to impurity of the first polarity.

Abstract: The invention provides a trench isolation structure comprising a semiconductor region, a first insulation film formed on a top surface of the semiconductor region, a trench groove extending vertically from the first insulation film into the semiconductor region so that a bottom of the trench groove lies below an interface between the first insulation film and the semiconductor region, and an inter-layer insulator being formed which resides not only on the first insulation film but also within the trench groove so that the inter-layer insulator fills up the trench groove.The present invention still further provides a method for forming a trench isolation in a semiconductor region. The method comprises the following steps. A first insulation film is formed on a top surface of a semiconductor region.

Abstract: A method for fabricating a semiconductor device in a substrate. Active regions are defined within the substrate using a thin oxide layer and a silicon nitride layer with portions of the silicon nitride layer being etched away to expose the thin oxide layer. Field oxide regions are formed over regions other than the defined active regions. These field oxide regions are located between the active regions. The remaining portions of the silicon nitride layer and the thin oxide layer are removed and a sacrificial oxide layer is then grown on the surfaces of the active regions. A first mask, a N-well mask, is formed for implanting N-type dopants. A buried layer implanted using P-type dopants with the first mask in place. Thereafter, the N-well regions are implanted. The first mask is removed and a second mask is formed to define regions for implanting P-well regions using P-type dopants. The P-well regions are implanted using P-type dopants.

Abstract: This invention proposes a process to form planarized twin-wells for CMOS devices. After depositing a pad oxide and a silicon nitride layers, a high-energy phosphorus ion implantation is performed to form the N-well by using a photoresist as s mask. A thick oxide layer deposited by liquid phase deposition process is then grown on the N-well region part of the silicon nitride layer, but not on the photoresist. After stripping the photoresist, a high-energy boron ion implantation is carried out to form the P-well by using the LPD-oxide layer as a mask. The thick LPD-oxide layer is removed by BOE or HF solution. A high temperature steam oxidation is performed to grow field oxides. The dopants are activated and driven in to form twin-wells at this step. After removing the pad oxide and the silicon nitride layer, the CMOS device is fabricated by standard processes.

Abstract: A process for dry etching a passivation layer (42) of a semiconductor device is performed such that a low radio frequency (RF) power step is used when an underlying bond pad (22) is initially exposed and a high RF power step is used after the initial exposure. The process virtually eliminates or reduces the likelihood of bond pad (22) staining, particularly when a polyimide die coat layer (72) is subsequently formed over the semiconductor device (50).

Abstract: A method of fabricating a semiconductor device. The procedure of fabricating process is performed inversely as the conventional method. Less numbers of photolithography process is performed with the application of selective liquid phase deposition.

Abstract: A semiconductor processing method of forming complementary metal oxide semiconductor memory circuitry includes, a) defining a memory array area and a peripheral area on a bulk semiconductor substrate, the peripheral area including a p-well area for formation of NMOS peripheral circuitry, the peripheral area including a first n-well area and a second n-well area for formation of respective PMOS peripheral circuitry, the first and second n-well areas being separate from one another and having respective peripheries; b) providing a patterned masking layer over the substrate relative to the peripheral first and second n-wells, the masking layer including a first masking block overlying the first n-well and a second masking block overlying the second n-well, the first masking block masking a lateral edge of the first n-well periphery; and c) with the first and second masking blocks in place, providing a buried n-type electron collector layer by ion implanting into the bulk substrate; the resultant n-type electron

Abstract: Integrated circuitry and methods of forming integrated circuitry are described. In one implementation, a common masking step is utilized to provide source/drain diffusion regions and halo ion implantation or dopant regions relative to the source/drain regions within one well region of a substrate; and well contact diffusion regions within another well region of the substrate. The common masking step preferably defines at least one mask opening over the substrate within which the well contact diffusion region is to be formed, and the mask opening is suitably dimensioned to reduce the amount of halo ion implantation dopant which ultimately reaches the substrate therebelow. According to one aspect, a plurality of mask openings are provided. According to another aspect, a suitably-dimensioned single mask opening is provided.

Abstract: A method of manufacturing a semiconductor integrated circuit device includes the steps of forming a first conductive film on a gate oxide film in a MISFET forming region for a memory cell on a main surface of a semiconductor substrate, and forming a second conductive film via the gate oxide film to a thickness which is larger than the difference in a step between the first conductive film and the gate oxide film in a MISFET forming region for the peripheral circuit on the main surface of the semiconductor substrate, simultaneously with the formation of the second conductive film on the first conductive film in the MISFET forming region for the memory cell.

Abstract: A method for forming a well structure in an integrated circuit such that, without any additional masking steps, the well implantation can be performed before the definition of the active device area. Hence, besides being able to avoid problems caused by a low breakdown voltage, also can provide a self-alignment mark for subsequent mask alignment, thereby reducing misalignment errors.

Abstract: The present invention discloses a structure for forming CMOS transistors with a self-aligned planarization twin-well by using fewer mask counts. An N-well is formed in the semiconductor substrate. Then, a P-well is formed against the N-well, and portion of the P-well is formed along the bottom of the N-well. An oxide region is formed on the surface of both the N- and P-wells, and covers portions of the N- and P-wells. A high energy and low dose boron blanket implantation is performed to increase the threshold voltage of the oxide region, which has been used for an ESD (Electro-Static Discharge) protection circuit. Punch-through stopping layers for the CMOS transistor are formed in the upper portion of the N-well. A BF.sub.2 ion implantation layer is formed at the top of both the N- and P-wells to increase the threshold voltages of the PMOSFET and NMOSFET transistors.

Abstract: An improved method for forming a triple well of a semiconductor device which is capable of more simply and easily forming a triple well without removing an anti-oxidation film.

Abstract: A semiconductor fabrication method for forming an insulation film and a first anti-oxidation film sequentially on a substrate which is sectioned into each of a peri region and a cell region. An active pattern is formed in the cell region and a first field ion-implanted region in a first conductive well of the cell region. Side wall spacers are formed on each side wall of the active pattern in the cell region. An active pattern is formed in the peri region by selectively etching the first anti-oxidation film and the insulation film so as to expose a certain surface portion of the peri region substrate therethrough. A first field ion-implanting region is formed in a first conductive well of the peri region by ion-implanting highly concentrated first conductive impurities through the exposed substrate and a second field ion-implanted region in a second conductive well of the peri region.

Abstract: Method for forming a CMOS transistor in a silicon layer positioned above an underlying buried oxide layer including isolating a first active area and a second active area; forming an n-well and a p-well having specified back gate threshold voltages; forming gates over the wells; forming a lightly doped drain region in the p-well that extends through the silicon layer; and implanting ions to form a source and a drain region in the p-well to provide a lightly doped drain drift region.

Abstract: A method for forming a shallow junction of a semiconductor device, characterized by a rapid thermal process executed to considerably decrease the density of the point defects which may be caused by ion implantation. With it, a junction which is much shallower, with lower sheet resistance and less junction leakage current can be obtained even under conventional ion implantation and tube treatment conditions. This contributes to an improvement in the production yield of a semiconductor device. By virtue of the elimination of the point defects, the limits in selecting the tube thermal treatment temperature and time for planarizing the subsequent interlayer insulating film can be relieved, so that process allowance can be secured, thereby improving the reliability of the semiconductor device and allowing the high integration of the semiconductor device.

Abstract: A method for fabricating alignment marks in a twin-well integrated circuit without using a zero-layer photomask is disclosed.

Abstract: SRAMs conventionally formed on N-type substrates are instead formed on P-type substrates which have had the surface layer of the substrate converted to a blanket N-type well region. Preferably, the blanket N-type well region is formed by ion implantation of phosphorus ions to a dosage of between 5.times.10.sup.12 to 2.times.10.sup.13 /cm.sup.2 at an energy of 200-1000 KeV. Use of a P-type substrate having a blanket N-well region formed by ion implantation are less expensive than the N-type substrates conventionally used, and make the SRAM processing techniques compatible with the P-type substrates conventionally used in microprocessors and other logic devices.

Abstract: A CMOS process with inverse-T gate LDD structure uses liquid phase deposition (LPD) processes to achieve a low thermal budget with only six photoresist-masks in a CMOS device. A first photoresist-mask is used to form field oxide regions. A second photoresist-mask is used to implant a P-well. Before the second photoresist-mask is removed, a first LPD oxide layer is used to cover the N-well. The second photoresist-mask is removed, and the first LPD oxide layer is used as a mask for implanting the N-well. The first LPD oxide layer is removed and a polysilicon layer is deposited on the substrate. A third photoresist-mask is used to etch the polysilicon layer to form gate-structures for the NMOS and PMOS devices. A conformal amorphous Si layer is formed on the gate-structures, followed by forming a fourth photoresist-mask over the N-well. A conformal LPD oxide layer is formed on the conformal polysilicon layer over the P-well. N-LDD regions are then implanted.

Abstract: A structure for improving latch-up immunity and interwell isolation in a semiconductor device is provided. In one embodiment, a substrate has an upper surface and a first dopant region formed therein. The first dopant region has a lower boundary located below an upper surface of the substrate and a side boundary extending from the upper surface of the substrate to the lower boundary of the first dopant region. A heavily doped region having a first portion and a second portion located along the lower boundary and the side boundary of the first dopant region, respectively, has a substantially uniform dopant concentration greater than a dopant concentration of the first dopant region. The heavily doped region improves latch-up immunity and interwell isolation without degrading threshold voltage tolerance.

Abstract: A method of forming a multiple transistor channel doping in a semiconductor substrate utilizes a unique photoresist sequence. A pattern of a first resist in first and second locations on first and second different areas of the semiconductor substrate is formed, respectively. A pattern of a second resist is then formed on the second area, wherein the second resist covers the first resist pattern in the second location. The first resist is selected for being immune from the second resist. Ions are then implanted in the first area to form a first conductivity type well having a first multiple transistor channel doping profile. The second resist pattern is then removed and a pattern of a third resist is formed on the first area, wherein the third resist covers the first resist pattern in the first location. In addition, the first resist is selected for being immune from the third resist.

Abstract: CMOS vertically modulated wells are constructed by using a blanket implant to form a blanket buried layer and then using clustered MeV ion implantation to form a structure having a buried implanted layer for lateral isolation in addition to said blanket buried layer.

Abstract: A vertical power MOSFET, which could be a trench-gated or planar double-diffused device, includes an N+ substrate and an overlying N-epitaxial layer. An N-type buried layer is formed in the epitaxial layer and overlaps the substrate, the buried layer having a dopant concentration which is greater than the dopant concentration of the epitaxial layer but less than the dopant concentration of the substrate. The ion implant which is used to create the buried layer is preferably performed after most of the high temperature operations in the fabrication process in order to minimize the diffusion of the buried layer. This controls the distance between the top edge of the buried layer and the drain-body junction of the MOSFET and allows the breakdown voltage and on-resistance of the MOSFET to be determined substantially without regard to the thickness of the epitaxial layer.

Abstract: CMOS vertically modulated wells have a structure with a buried implanted layer for lateral isolation (BILLI). This structure includes a field oxide area, a first retrograde well of a first conductivity type, a second retrograde well of a second conductivity type adjacent the first well, and a BILLI layer below the first well and connected to the second well by a vertical portion. This structure has a distribution in depth underneath the field oxide which kills lateral beta while preventing damage near the surface under the field oxide.

Abstract: A method and an apparatus for forming a transistor suitable for a high voltage circuit. In one embodiment, the transistor is formed without adding any steps to an existing state-of-the-art CMOS process. A well is implanted into a portion of a substrate such that the well has a higher doping concentration than the substrate. A first diffusion region is then implanted into the substrate such that at least a portion of the first diffusion is disposed within the well. In addition, a second diffusion is implanted into the substrate separated from the well such that the second diffusion region is disposed entirely outside the well. A channel region is disposed between the first and second regions and gate is disposed over the channel region to form the high voltage transistor. Since the second diffusion region is disposed entirely outside the well in the lower doped substrate, a higher junction breakdown voltage is realized.

Abstract: A method of manufacturing a semiconductor device comprises; forming a device isolation region in a semiconductor substrate; forming at least a first conductivity type impurity region in the semiconductor substrate; and forming on the semiconductor substrate a transistor including a gate insulating film, a gate electrode, source/drain regions and a channel located directly under the gate electrode, wherein the first conductivity type impurity region is formed by the steps of: an ion implantation 1 having a concentration peak at a location deeper than the bottom of the device isolation region; an ion implantation 2 having a concentration peak at a location around the bottom of the device isolation region; an ion implantation 3 having a concentration peak around the junction regions where the source/drain regions are to be formed; and an ion implantation 4 having a concentration peak on the surface or directly under the surface of the region where the channel is to be formed.

Abstract: A CMOS integrated circuit with field isolation including an NFET(s) having an isolated P-well, wherein the isolated P-well is adjusted so that it does not extend below the field isolation (e.g., STI) and the width and doping of the P-well and an underlying buried N-well is adjusted so that the depletion regions of the source/drain (S-D) diode and also the well-diode just meet (merge) without overlap in the P-well. The semiconductor device obtains bipolar effect and reduced junction capacitance in a bulk single-crystal technology. A method for fabricating the semiconductor device is also provided.

Abstract: A method of fabricating alignment marks on an integrated circuit device including steps of: forming first pad oxide layer and first nitride layer on a P-type semiconductor substrate; coating and patterning first photoresist layer by lithography; partially etching first nitride layer to form first nitride pattern by first photoresist etching mask; and ion implanting N-type ions to form an N-doped region; coating and patterning second photoresist layer by lithography; partially etching first nitride pattern to form second nitride pattern; and ion implanting P-type ions to formed a P-doped region. Next, performing thermally drive in N-type and P-type impurities to form N-well and P-well regions, and growing an oxide layer simultaneously. Finally, the height difference between the oxide layer and the second nitride pattern producing a ladder topography can be used as an alignment mark for the succeeding lithographic processes.

Abstract: Methods of forming semiconductor active regions having channel-stop regions therein include the steps of forming an oxide layer and first nitride layer on a face of a semiconductor substrate and then patterning the first nitride layer to expose first portions of the oxide layer. The patterned first nitride layer is then used as a mask during implantation of dopants of second conductivity type into the substrate. A second nitride layer is then deposited on the exposed first portions of the oxide layer and on the first nitride layer. A second photoresist layer is then patterned and used as a mask to etch the second nitride layer and patterned first nitride layer, to expose second portions of the oxide layer. A third photoresist layer is then patterned to cover the first portions of the oxide layer. The patterned third photoresist layer and remaining portions of the patterned first and second nitride layers are then used as implant masks during implantation of second conductivity type dopants.

Abstract: A method of forming first and second conductivity type wells in a semiconductor device includes the steps of forming an isolation layer on a semiconductor substrate, forming a multi-layer mask over a portion of the substrate to define the first and second conductivity type wells, implanting a first conductivity type impurity to form the first conductivity type well, removing a partial layer from the multi-layer mask, and implanting a second conductivity type impurity to form the second conductivity type well.