Abstract: An efficient method for fabricating dual well type structures uses the same number of masks used in single well type structure fabrication. In a preferred embodiment, the current invention allows low voltage and high voltage n-channel transistors and low voltage and high voltage p-channel transistors to be formed in a single substrate. One mask is used for forming a diffusion well, a second mask for both forming a retrograde well and doping the well to achieve an intermediate threshold voltage in that well, and a third mask for both differentiating the gate oxides for the low voltage devices and doping the threshold voltages to achieve the final threshold voltages.

Abstract: A process for forming a vertical double-diffused metal oxide semiconductor (VDMOS) structure comprising a semiconductor substrate, an epitaxial layer on the substrate, and a dielectric gate layer on the epitaxial layer includes implanting a first concentration dopant of a first conductivity type through an aperture defined by edges of a patterned gate conductor layer on the dielectric gate layer so that the first concentration dopant diffuses to form a body region of the VDMOS structure. A mask is formed on the patterned gate conductor layer and on a first portion of the body region for defining apertures exposing second portions of the body region.

Abstract: A pad oxide layer is formed on a substrate, wherein the thickness of the pad oxide layer is about greater than 250 Å. The alignment photo-resist layer is selectively patterned by a conventional lithography method to define the N-well region. The pad oxide layer is partially etched by using etch method with the alignment photo-resist pattern as a mask until the thickness of the pad oxide layer is about 100 Å to form an alignment mark. The N-type ion-implant is performed by the alignment photo-resist pattern as a mask to form an N-doped region in the substrate. Then, the alignment photo-resist pattern is removed. The P-well photo-resist is defined and formed on the pad oxide layer, then performing a P-type ion-implant through the pad oxide layer into the substrate by means of the P-well photo-resist as a mask to form a P-doped region. Then remove the P-well photo-resist and proceed with the drive-in process to form the N-well region and P-well region.

Abstract: A method of forming dual-metal gates in a semiconductor device, including the steps of providing a semiconductor substrate having a PMOS area and an NMOS area wherein dummy gates are formed in the PMOS and NMOS areas respectively, forming an insulating interlayer on the semiconductor substrate so as to cover the dummy gates, polishing the insulating interlayer until the dummy gates are exposed, forming a first groove defining a first metal gate area by selectively removing one of the dummy gates formed in the PMOS and NMOS areas, forming a first gate insulating layer and a first metal layer on an entire area of the semiconductor substrate including the first groove successively, forming a first metal gate in the first groove by etching the first metal layer and first gate insulating layer until the insulating interlayer is exposed, forming a second groove defining a second metal gate area by removing the remaining dummy gate, forming a second gate insulating layer and a second metal layer on the entire area o

Abstract: A photoresist pattern through which a first well forming region and a second well forming region are exposed is formed over a semiconductor substrate, used as the mask to dope the semiconductor substrate with an impurity thereby to form buried n-wells, and further used as the mask to dope the same with an impurity thereby to form shallow p-wells in a self-alignment manner over the buried n-wells. Subsequently, the photoresist pattern is removed. After this, a photoresist pattern through which the outer peripheral region of the first well forming region and a third well forming region are exposed is formed over the major surface of the semiconductor substrate, and used as the mask to dope the semiconductor substrate with an impurity thereby to form shallow p-wells.

Abstract: A semiconductor device having two or more types of separation oxide film are formed on the substrate of the semiconductor device by different methods so as to correspond with element types formed on the same semiconductor substrate. The method for producing the semiconductor device comprises a first separation oxide film formation process, and a second separation oxide film formation process. In the first separation oxide film formation process, a first mask layer is formed on the semiconductor substrate, the first mask layer of the element separation region of the logic element is selectively removed and the semiconductor substrate in the region area selectively oxidized. In second separation oxide film formation process, the remaining first mask layer is removed, a second mask layer is formed, the second mask layer of the element separation region of DRAM elements is then selectively removed, and the semiconductor substrate of the region is selectively oxidized.

Abstract: A high-voltage device. A substrate has a first conductive type. A first well region with the first conductive type is located in the substrate. A second well region with the second conductive type is located in the substrate but is isolated from the first well region. Several field oxide layers are located on a surface of the second well region. A shallow trench isolation is located between the field oxide layers in the second well region. A first doped region with the second conductive type is located beneath the field oxide layers. A second doped region with the first conductive type is located beneath the shallow trench isolation in the second well region. A third well region with the first conductive type is located in the first well region and expands from a surface of the first well region into the first well region. A gate structure is positioned on the substrate between the first and the second well regions and covers a portion of the first, the third well regions and the field oxide layers.

Abstract: A solid imaging device including: a semiconductor substrate of a first conductivity type; a layer of a second conductivity type formed on a surf ace of the semiconductor substrate, the layer at least including a photosensitive portion of the second conductivity type; and a MOS transistor of the second conductivity type coupled to the photosensitive portion, wherein the solid imaging device further includes a layer of the first conductivity type in at least a channel region of the MOS transistor of the second conductivity type, the layer of the first conductivity type having an impurity concentration which is higher than an impurity concentration of the semiconductor substrate, and wherein at least a portion of a boundary of the layer of the second conductivity type is in direct contact with the semiconductor substrate.

Abstract: In a semiconductor memory device, first and second impurity regions of a second conductivity are provided as wells in a semiconductor substrate of a first conductivity. Outside of the first and second impurity regions, third impurity regions of the first conductivity are provided as wells in the substrate. Fourth impurity regions of the first conductivity are provided as wells in the first impurity regions. The first impurity regions each have an impurity concentration which gradually decreases with increasing depth below the top surface of the semiconductor substrate, and the fourth impurity regions have at least two impurity concentration peaks below the top surface of the semiconductor substrate. A memory cell can be reliably erased by forming a retrograde pocket well for a memory cell array, and a diffusion well surrounding the pocket well, thus maintaining a high breakdown voltage between the pocket well and the substrate.

Abstract: A substantially vertical isolation junction between semiconductor devices is provided. The substantially vertical junction between a P-doped region and an N-doped region allows the P-doped region to be adjacent to the N-doped region with a lateral stagger with a width that is less than 0.1 of the depth. The substantially vertical junction is created by placing a first mask over part of a substrate. A first series of implants of a first dopant is implanted in the substrate. The first mask is removed and a second mask is placed over part of the substrate. A second series of implants of a second dopant of a second conductivity is then implanted in the substrate. A substantially vertical junction results.

Abstract: There is disclosed a method for manufacturing a semiconductor integrated circuit of triple well structure, comprising the steps of forming an N-well, a P-well and a device isolation region in an N-type silicon substrate, thereafter forming a silicon oxide film on the whole surface of the silicon substrate by a thermal oxidation, forming a resist mask covering a region in which the silicon oxide film is required, ion-implanting a P-type impurity using the resist mask as a mask and with an implantation energy enough to allow the ion-implanted impurity to reach a bottom of the N-well and the P-well, so as to form a buried impurity layer, thereafter removing the silicon oxide film not covered with the resist mask by an etching, then removing the resist mask, and conducting a thermal oxidation on the whole surface of the silicon substrate so that a relatively thick gate oxide film is formed on a region which was covered with the resist mask, and a relatively thin gate oxide film is formed on a region which was not

Abstract: Methods of forming field effect transistors and related field effect transistor constructions are described. A masking layer is formed over a semiconductive substrate and an opening having sidewalls is formed therethrough. The opening defines a substrate area over which a field effect transistor gate is to be formed. A dopant of a first conductivity type is provided through the opening and into the substrate. Sidewall spacers are formed over respective sidewalls of the opening. Enhancement dopant of a second conductivity type which is different from the first conductivity type is provided through the opening and into the substrate. A transistor gate is formed within the opening proximate the sidewall spacers, and source/drain regions of the second conductivity type are diffused into the substrate operably proximate the transistor gate. The first conductivity type dopant forms a halo region proximate the source/drain regions and lightly doped drain (LDD) regions for the transistor.

Abstract: A method for fabricating a high vltage device with double diffusion structure provides a pad oxide layer on a silicon substrate. A silicon nitride layer is formed and patterned to expose isolation regions. A first mask covers the partial isolation regions spaced from the silicon nitride layer. A well region is formed underlay the silicon nitride layer. A second mask covers the partial isolation region spaced from the silicon nitride layer and the partial silicon nitride layer. First doped regions are formed underlay the partial silicon nitride layer. Then the isolation regions are formed partially on the first doped regions. Next, a third mask covers the pad oxide layer and the partial isolation regions and second doped regions are formed spaced from the first doped regions and below the isolation regions. A gate is formed and located between the first doped regions and a spacer on a side-wall thereof. Third doped regions are formed in the first doped regions.

Abstract: An ultra-large scale CMOS integrated circuit semiconductor device with LDD structures is manufactured by forming a gate oxide layer over the semiconductor substrate; forming a polysilicon layer over the gate oxide layer; forming a first mask layer over the polysilicon layer; patterning and etching the first mask layer to form a first gate mask; anisotropically etching the polysilicon layer to form a first polysilicon gate, wherein the first polysilicon gate has sidewalls with sloped profiles and the sloped profiles are used as masks during the ion implantation of the LDD structures to space the resultant LDD structures away from the edges of second polysilicon gates to be formed subsequently with substantially vertical profiles.

Abstract: A process for forming self-aligned, twin well regions for a CMOS device, without the use of an oxidation retarding silicon nitride layer, has been developed. A first ion implantation procedure is used to place N type ions in a first portion of a semiconductor substrate, followed by a wet thermal oxidation procedure resulting in the growth of a thick silicon dioxide layer on the N type ions, in the first portion of the semiconductor substrate, while growing a thin silicon dioxide layer on a second portion of the lightly doped, P type semiconductor substrate. A second ion implantation procedure places P type ions through the thin silicon dioxide layer, into the second portion of the semiconductor substrate, while the thick silicon dioxide layer prevents the P type ions from reaching the first portion of the semiconductor substrate.

Abstract: A method of manufacturing a low power dissipation semiconductor power device is provided which is easy to perform and suitable for mass production. When a first and second conductivity-type regions are formed on a semiconductor substrate which is selectively irradiated by impurity ions, an excellent super junction is formed by controlling the ion acceleration energy and the width of each irradiated region so that the first and second conductivity-type regions may have a uniform impurity distribution and a uniform width along the direction of irradiation. Another method of manufacturing a low power dissipation semiconductor power device having an excellent super junction is provided which selectively irradiates a collimated neutron beam onto a P+ silicon ingot and forms an N+ region that has a uniform impurity distribution and a uniform width along the direction of irradiation in the P+ silicon ingot.

Abstract: Isolation regions are formed with greater accuracy and consistency by forming an oxide-silicon nitride stack and then depositing an amorphous silicon antireflective layer, on the silicon nitride layer before patterning. Embodiments also include depositing the silicon nitride layer and the amorphous silicon layer in the same tool.

Abstract: A method for fabricating a wiring which runs at least piecewise in a substrate. At least one conductive connection runs in the semiconductor substrate and at least one conductive connection runs on the semiconductor substrate being provided. The semiconductor component enables applications in which high security against external manipulations is important.

Abstract: An MOS device is provided using indium as a threshold adjust implant in the channel regions of an NMOS device and/or in the conductive gate overlying the channel region in a PMOS device. Indium ions are relatively immobile and achieve location stability in the areas in which they are implanted. They do not readily segregate and diffuse in the lateral directions as well as in directions perpendicular to the silicon substrate. Placement immobility is necessary in order to minimize problems of threshold skew and gate oxide thickness enhancement. Additionally, it is believed that indium atoms within the channel region minimize hot carrier effects and the problems associated therewith.

Abstract: A method for fabricating a CMOS image sensor is disclosed. The CMOS sensor includes the portions of sensor photo-diode array NMOS and PMOS. In the method, partial steps involving implantation for image sensor fabrication are implemented at different times with the fabrication of NMOS. The method is compatible with the present process only to add a mask for patterning sensor implantation and to modify some traditional patterns of masks. The doses of the field region within the region of sensor photo-diode array can be implemented separately and are not subject to higher dopants for NMOS in the present fabrication. Thus, the doses for the sensor photo-diode array can be adjusted to meet the requirements of isolation and low dark current for the image sensor.

Abstract: Wells of n- and p-type are formed in a p-type substrate. Wells of p-type are also formed in the n-type well. Both the p-type wells are formed by the same process at the same time to make MOS transistors have different threshold voltages. MOS transistors having a long gate length and a low threshold voltage are formed in the p-well in the n-well, and MOS transistors having a short gate length and a high threshold voltage are formed in the p-well at the outside of the n-well. Fuses are formed over the p-type wells in the n-type well at a high density.

Abstract: A method for selectively heating a substrate without damaging surrounding regions of the substrate. In particular, the invention provides for a method of selectively activating doped regions of a semiconductor device without damaging surrounding doped and activated regions. Specifically, the invention provides a laser anneal which activates locally doped regions, while surrounding doped and activated regions are protected using a reflective mask.

Abstract: A CMOS integrated circuit includes an NMOS transistor and a PMOS transistor in an integrated circuit substrate. The NMOS transistor and the PMOS transistor each include a gate, and a source/drain on opposing sides of the gate. An insulating layer is located on the integrated circuit substrate. The insulating layer includes a contact hole therein which exposes a portion of a corresponding one of the source/drains. A source/drain plug is formed in the corresponding one of the source/drains. The source/drain plug is of opposite conductivity from the corresponding one of the source/drains. The source/drain plug is centered about the portion of the corresponding one of the source/drains. The source/drain plug may be formed by ion implantation through the contact hole and is thereby self-aligned to the contact hole. The source/drain plug can compensate for misalignment and the diffusion for highly integrated CMOS devices.

Abstract: The semiconductor device comprises a semiconductor substrate 10 of a first conduction-type, first wells 20a, 20b of a second conduction-type formed in a first region on the primary surface of the semiconductor substrate 10, a second well 22a formed in a second region on the primary surface of the semiconductor substrate 10 other than the first region, a third well 22b of the first conduction-type formed in the first well, and high-concentration impurity-doped layers 26 of the first conduction-type formed in deep portions of the semiconductor substrate spaced from the primary surface of the semiconductor device in device regions. In the semiconductor device having triple wells according to the present invention, the high-concentration impurity-doped layers are formed in deep portions inside of the device regions. Accordingly, in the case where the wells have a low concentration so that the transistors have a low threshold voltage, the deep portions of the wells can independently have a high concentration.

Abstract: Provided with a semiconductor device including: a semiconductor substrate having a first conductivity type; a first well having a second conductivity type formed in a first region in a major surface of the semiconductor substrate; a second well having the first conductivity type formed in a second region in the major surface of the semiconductor substrate; a first MOS transistor having the first conductivity type and a first contact region having the second conductivity type formed in the first well; a second MOS transistor having the second conductivity type and a second contact region having the second conductivity type formed in the second well; a heavily doped region of buried layer having the second conductivity type formed at a portion corresponding to the first contact region in the first well; and a heavily doped region of buried layer having the first conductivity type formed at a portion corresponding to the second contact region in the second well.

Abstract: A method for manufacturing a CMOS sensor comprises the steps of providing a substrate having a first conductive type, wherein the substrate comprises an isolation region, an active region, a gate structure on the active region and a source/drain region having a second conductive type in the substrate. A patterned photoresist is formed over the substrate. A first doped region having the second conductive type is formed across a portion of the source/drain region and extends from the surface of the substrate into the substrate. A second doped region having the first conductive type is formed to wrap the first doped region in the substrate. A third doped region having the second conductive type is formed under the second doped region. A fourth doped region having the first conductive type is formed under the third doped region. The patterned photoresist is removed.

Abstract: An array of P-channel memory cells is separated into independently programmable memory segments by creating multiple, electrically isolated N-wells upon which the memory segments are fabricated. The methods for creating the multiple, electrically isolated N-wells include p-n junction isolation and dielectric isolation.

Abstract: A method of manufacturing wells comprises the step of providing a p-type substrate and then sequentially forming a p-well and n-well with low dosage in the p-type substrate. Thereafter, energy is used to dope n-type ions into the p-well. The triple well formed in the present invention has low dosage ions, hence the DRAM formed on the triple well in subsequent process can have a faster refresh time.

Abstract: The present invention discloses a method of forming CMOS transistors with self-aligned planarization twin-well by using fewer mask counts. After a silicon nitride layer is formed over a first pad oxide layer on a semiconductor substrate, an N-well region is defined by first implanting in the semiconductor substrate. After removing the first photoresist layer, a second ion implantation is performed to define a P-well region. Next, both the silicon nitride layer and the first pad oxide layer are removed. A high temperature long time anneal is done to form a deep twin-well. A plurality of trench isolation regions is formed to define an active area region. A second pad oxide layer is formed on the substrate. A high energy and low dose blanket phosphorous is implanted in a semiconductor substrate for forming a punch-through stopping layer of the PMOSFET device. A low energy and low dose blanket BF2 implant then adjust both the threshold voltages of the PMOSFET and NMOSFET.

Abstract: A photoresist pattern through which a first well forming region and a second well forming region are exposed is formed over a semiconductor substrate, used as the mask to dope the semiconductor substrate with an impurity thereby to form buried n-wells, and further used as the mask to dope the same with an impurity thereby to form shallow p-wells in a self-alignment manner over the buried n-wells. Subsequently, the photoresist pattern is removed. After this, a photoresist pattern through which the outer peripheral region of the first well forming region and a third well forming region are exposed is formed over the major surface of the semiconductor substrate, and used as the mask to dope the semiconductor substrate with an impurity thereby to form shallow p-wells.

Abstract: A circuit device that includes a gate overlying an area of a semiconductor substrate, a well formed in the substrate proximate a first edge of the gate and doped with a first concentration of a first dopant, a channel region doped with a first concentration of a second dopant underlying a portion of the gate adjacent the well, a non-conducting region formed in the first portion of the well, and a contact to the second portion of the well distal from the first edge of the gate.

Abstract: A mixed voltage CMOS process for fabricating transistors with different source-drain profiles is described. The present invention comprises a method for manufacturing a CMOS integrated circuit with a low voltage device 24 and a high voltage device 26 comprising the steps of obtaining active regions in a substrate 10 with gates 30 and 32 for the low voltage device 24 and the high voltage device 26, respectively, obtaining lightly implanted source and drain extensions 38 and 40 for the low voltage device 24, forming a side wall 42, 44, 46 and 48 next to each gate 30 and 32, and angularly implanting each of the source and drain regions 52, 54, 56 and 58 with an impurity 50 of a selected type for both the low voltage device 24 and the high voltage device 26, to eliminate the need for separately implanting the first voltage device and second voltage device with different source-drain extensions.

Abstract: A twin-well CMOS integrated circuit device includes an n-well region and a p-well region. Each of the n-well and p-well region includes spaced-apart regions which serve as drain and source regions, a channel region between the spaced-apart regions, a shallow trench isolation structure contiguous with one of the spaced-apart regions, and a doped diffused region extending from the surface of the well region, around and underneath the trench isolation structure, to a region beneath the contiguous spaced-apart region.

Abstract: A first dielectric layer (22) is formed over a semiconductor device substrate. A resist layer (32) is then patterned to expose portions of the first dielectric layer (22). Portions of the first dielectric layer (22) are removed to expose portions of the semiconductor device substrate (42). The resist layer (32) is then removed. The semiconductor device substrate is cleaned without using a fluorine-containing solution and a second dielectric layer (62) is formed overlying the semiconductor device substrate.

Abstract: Methods are described to prevent the inherent latchup problem of CMOS transistors in the sub-quarter micron range. Latchup is avoided by eliminating the low resistance between the Vdd and Vss power rails caused by the latchup of parasitic and complementary bipolar transistor structure that are present in CMOS devices. These goals have been achieved without the use of guard rings by using a deep n-well to disconnect the pnp collector to npn base connection of two parasitic bipolar transistors, and by using a buried p-well to disconnect the npn collector to pnp base connection of those same two parasitic transistors. Further, the deep n-well is shorted to a supply voltage Vdd, and the buried p-well is shorted to a reference voltage Vss via both the P substrate and a P+ ground tab. The proposed methods do not require additional mask or processes.

Abstract: The president invention discloses a method of manufacturing a semiconductor device, comprising the steps of: defining a cell region for an NMOS element and a peripheral circuit region for NMOS and PMOS elements on a semiconductor substrate; forming a sacrifice oxide film and an ion barrier oxide film on the entire structure after the defining process; performing ion injection process on the cell region and the peripheral circuit region, so that a low concentration impurity injection region therein is formed; removing the ion barrier oxide film formed on the cell region and the peripheral circuit region; performing ion injection process on selected regions of the cell region and the peripheral circuit region; injecting ions for adjusting a threshold voltage into selected regions of the cell region and the peripheral circuit region; performing ion injection process on the low concentration impurity regions of the cell region and the peripheral circuit region, so that R-well region and a P-well region are formed

Abstract: The semiconductor device according to the present invention comprises: a semiconductor substrate 10 of a first conductivity type; a well 28 of a second conductivity type different from the first conductivity type formed in a region 18 surrounding a region 20 of the semiconductor substrate 10; a diffused layer 42 of the second conductivity type formed, buried in the semiconductor substrate 10 in the region 20 and connected to the well 28 on a side thereof; and a well 44 of the first conductivity type formed in the semiconductor substrate 10 in the region 20 on the side of a surface thereof and electrically isolated from a rest region of the semiconductor substrate 10 by the well 28 and the diffused layer 42.

Abstract: A method of fabricating a semiconductor device wherein there is provided a semiconductor substrate of a first conductivity type. A dopant is implanted in one region of the substrate of opposite conductivity type and that region is masked, preferably with a silicon oxide mask. A relatively heavy dose of a dopant of the first conductivity type is implanted in a different region of the substrate while retaining the mask on the region of the substrate doped with dopant of the opposite conductivity type. The two implants are driven farther into the substrate to form a first tank of said first conductivity type and a second tank of opposite conductivity type by an annealing step while retaining the mask on the region of the substrate doped with dopant of the opposite conductivity type. A second implant of the first conductivity type is then implanted into the tank of first conductivity type while retaining the mask on the region of the substrate doped with dopant of the opposite conductivity type.

Abstract: A method of manufacturing a semiconductor device is provided in which a semiconductor device including a plurality of FETs having different threshold voltages and gate insulating films with different film thicknesses can be manufactured in a simplified process. Specifically, a first gate insulating film is formed on the main surface of a semiconductor substrate. On the first gate insulating film, a first protection film is formed. In regions A and B in each of which an FET having a second gate insulating film with a film thickness different from that of the first gate insulating film is to be formed, the first gate insulating film and the first protection film are removed to expose the surface of the semiconductor substrate. At the same time, the first protection film is left in regions other than the regions A and B. Using the first protection film as a mask, an impurity is implanted into the semiconductor substrate in the regions A and B.

Abstract: A method of fabricating a high-voltage device suitable for a low-voltage device. A well formed by ion implantation in the high-voltage device region serves as a drift region for fabricating the high-voltage device. Therefore, one mask is used to define a portion of the wells of the high-voltage device region and the wells of low-voltage device region. It is not necessary to use multiple masks to pattern the well of the low-voltage device region and the drift region of the high-voltage device region.

Abstract: An analog semiconductor device capable of preventing open of interconnection lines and notching due to step between transistor and capacitor regions is disclosed. An analog semiconductor device according to the present invention, includes a semiconductor substrate; a first, a second, and a third isolating layer of trench type formed on the substrate and defining a transistor region and a capacitor region, respectively; a lower electrode of a capacitor formed in the surface of the substrate of the capacitor region; an oxide layer formed under the lower electrode and insulating the lower electrode and the substrate; an gate insulating layer formed on the substrate of the transistor region; an dielectric layer formed on the lower electrode; a gate formed on the gate insulating layer; an upper electrode of the capacitor formed on the dielectric layer.

Abstract: A photoresist pattern through which a first well forming region and a second well forming region are exposed is formed over a semiconductor substrate, used as the mask to dope the semiconductor substrate with an impurity thereby to form buried n-wells, and further used as the mask to dope the same with an impurity thereby to form shallow p-wells in a self-alignment manner over the buried n-wells. Subsequently, the photoresist pattern is removed. After this, a photoresist pattern through which the outer peripheral region of the first well forming region and a third well forming region are exposed is formed over the major surface of the semiconductor substrate, and used as the mask to dope the semiconductor substrate with an impurity thereby to form shallow p-wells.

Abstract: A method for forming both n and p wells in a semiconductor substrate using a single photolithography masking step, a non-conformal oxide layer and a chemical-mechanical polish step. A screen oxide layer is formed on a semiconductor substrate. A barrier layer is formed on the screen oxide layer. The barrier layer is patterned to form a first opening in the barrier layer over regions of the substrate where first wells will be formed. We implant impurities of a first conductivity type into the substrate to form first wells. In a key step, a non-conformal oxide layer is formed over the first well regions and the barrier layer. It is critical that the non-conformal oxide layer formed using a HDPCVD process. The non-conformal oxide layer is chemical-mechanical polished stopping at the barrier layer. The barrier layer is removed using a selective etch, to form second openings in the remaining non-conformal oxide layer over areas where second well will be formed in the substrate.

Abstract: Systems and methods are described for fabricating semiconductor gate oxides of different thicknesses. Two methods for forming gate oxides of different thicknesses in conjunction with local oxidation of silicon (LOCOS) are disclosed. Similarly, two methods for forming gate oxides of different thicknesses in conjunction with shallow trench isolation (STI) are disclosed. Techniques that use two poly-silicon sub-layers of substantially equal thickness and techniques that use two poly-silicon sub-layers of substantially unequal thickness are described for both LOCOS and STI. The systems and methods provide advantages because gate uniformity and quality are improved, the processes and resulting devices are cleaner, and there is less degradation of carrier mobility.

Abstract: The present invention discloses a method of forming CMOS transistors with self-aligned planarization twin-well by using fewer mask counts. After a silicon nitride layer is formed over a pad oxide layer on a semiconductor substrate, an n-well region is defined by implanting a high energy dose phosphorous in the semiconductor substrate. When the photoresist layer used for defining the n-well is stripped, a high energy and low dose blanket boron is implanted under the n-well region in the semiconductor substrate. Next, both the silicon nitride layer and the pad oxide layer are removed. A high temperature steam oxidation process is then performed to remove the crystalline defects, and the in-situ high temperature long time anneal is done to form a deep twin-well. A thick pad oxide layer formed by the high temperature steam oxidation is then removed, and an active region is defined followed by a standard oxidation process to grow a thick field oxide region.

Abstract: The present invention provides apparatus and a process for efficiently removing particles generated during a laser marking of the semiconductor wafer substrate, thereby improving the yield. The process of the invention for marking a semiconductor wafer substrate by a beam of laser radiation comprises the steps of flowing a gas over a marking region at a predetermined flow rate and removing the gas from the marking region at the same predetermined flow rate, thereby generating a gas flow having a predetermined flow rate over and adjacent the marking region so that particles produced from the semiconductor wafer substrate while it is being marked will be removed. In a preferred embodiment, the semiconductor wafer substrate may be mounted with its upper surface to be marked directed downwardly while the laser marking beam is directed upwardly to the substrate.

Abstract: A method of fabricating a dual gate. A first conductive type region and a second conductive type region isolated by an isolation structure is provided. A polysilicon layer is formed on the first and the second conductive type regions. A diffusion layer containing second type conductive ions is formed on a second part of the polysilicon layer which covers the second conductive type region. First conductive ions are implanted into a part of the first conductive region which covers the first conductive type region. A first thermal process is performed. A metal layer is formed, and a second thermal process is performed, so that the metal layer is transformed into a metal silicide layer. A dielectric layer is formed on the metal layer. The dielectric layer, the metal silicide layer, diffusion layer, and the polysilicon layer are patterned to form a dual gate.

Abstract: A method for forming a dual inlaid contact structure (damascene) begins by etching dual inlaid contact structures (32, 34, and 36). Masking layers (28) are (228) and the deposition of low-K dielectric material 26 is used to selectively form low-K regions (30) only in critical areas where low-K dielectric material is absolutely needed. Other portions of the wafer remain covered with conventional oxide (24) so that adverse impacts of low-K dielectric material is minimized. Conductive material (38, 40, and 42) is then formed to complete dual inlaid contact structures whereby low-K dielectric plugs (30) reduce cross talk and capacitance within the final structure.

Abstract: Dynamic Random Access Memory (DRAM) cells are formed in a P well formed in a biased deep N well (DNW). PMOS transistors are formed in N wells. The NMOS channels stop implant mask is modified not to be a reverse of the N well mask in order to block the channels stop implant from an N+ contact region used for DNW biasing. In DRAMs and other integrated circuits, a minimal spacing requirement between a well of an integrated circuit on the one hand and adjacent circuitry on the other hand is eliminated by laying out the adjacent circuitry so that the well is located adjacent to a transistor having an electrode connected to the same voltage as the voltage that biases the well. For example, in DRAMs, the minimal spacing requirement between the DNW and the read/write circuitry is eliminated by locating the DNW next to a transistor precharging the bit lines before memory accesses. One electrode of the transistor is connected to a precharge voltage.

Abstract: A method of forming a twin well includes the steps of: forming a field oxide layer on a semiconductor substrate to define active regions of a device, and forming a first mask which exposes a predetermined active region of the semiconductor substrate; ion-implanting a first conductivity type impurity into the exposed region of the semiconductor substrate using the first mask as an ion implantation mask, to form a first well; ion-implanting a second conductivity type impurity to penetrate the first mask, to form a buried region which is self-aligned with the first well and comes into contact with the bottom of the field oxide layer; removing the first mask, and forming a second mask which is to expose the first well of the semiconductor substrate; and ion-implanting a second conductivity impurity into the exposed region of the semiconductor substrate to levels deeper and shallower than the buried region using the second mask as an ion implantation mask, to form a second well including the buried region.