Abstract: A buried channel PMOS transistor for analog applications is integrated into a digital CMOS process. A third well region (105) is formed by implanting a region in the semiconductor substrate with all the n-type and p-type implants used to form the n-well and p-well regions for the digital CMOS process. A gate dielectric layer (50) and gate layer (109) are formed above the third well (105) and comprise the gate stack of the buried channel PMOS transistor. The implants used to form the drain extension regions and the source and drain regions of the CMOS transistors are used to complete the buried channel PMOS transistor.

Abstract: A linear laser light which has an energy and is to be scanned is irradiated to a semiconductor device formed on a substrate, and then the substrate is rotated to irradiate to the semiconductor device a linear laser light which has a higher energy than that of the irradiated linear laser light and is to be scanned. Also, in a semiconductor device having an analog circuit region and a remaining circuit region wherein the analog circuit region is smaller than the remaining circuit region, a linear laser light having an irradiation area is irradiated to the analog circuit region without moving the irradiation area so as not to overlap the laser lights by scanning. On the other hand, the linear laser light to be scanned is irradiated to the remaining circuit region.

Abstract: A semiconductor contact structure for a merged dynamic random access memory and a logic circuit (MDL) and a method of manufacturing the contact structure to: (i) a cell contact pad; (ii) at least one active region; and (iii) at least one gate electrode simulaneously, whereby an electric short between the gate electrodes and the cell contact pad is avoided, even in the event a lithographic misalignment occurs and whereby it is possible to obtain an overlap margin in the cell region, even with an improved metal contact to the gate electrode in the peripheral circuit region of the semiconductor device.

Abstract: A semiconductor memory device has a silicon substrate 10. A first embedded layer 11 is formed in the silicon substrate 10 under a p-well 18 in an area below a region where a drain 36 of a driver transistor 30 is located. The first embedded layer 11 makes a junction with the p-well 18. Also, the first embedded layer 11 is formed below an n-well 16 and contacts the n-well 16. When the drain 36 of the driver transistor 30 is at a voltage of 3V, &agr;-ray may pass through the p-well 18, the first embedded layer 11 and the silicon substrate 10. As a result, electron-hole pairs are cut. Due to the presence of the p-n junction that is formed by the p-well 18 and the first embedded layer 11, only electrons in the p-well 18 are drawn to the drain 36. As a result, a fall in the drain voltage of 3V is reduced. As a consequence, the device structure makes it difficult to destroy retained data.

Abstract: A new cascaded NMOS transistor output circuit with enhanced ESD protection is achieved. A driver PMOS transistor has the source connected to a voltage supply, the gate connected to the input signal, and the drain connected to the output pad. A dummy PMOS transistor has the source and the gate connected to the voltage supply, and the drain connected to the output pad. A driver NMOS cascaded stack comprises first and second NMOS transistors. The first NMOS transistor has the source connected to ground and the gate connected to the input signal. The second NMOS transistor has the gate connected to the voltage supply, the source connected to the first NMOS transistor drain, and the drain connected to the output pad. A p− implanted region underlies the n+ region of the drain but does not underlie the n+ region of the source. A dummy NMOS cascaded stack comprises third and fourth NMOS transistors. The third NMOS transistor has the gate and the source connected to ground.

Abstract: A manufacturing method of a semiconductor device, in which a native oxide film on a silicon substrate is removed before ion implantation is performed, and a process that the surface of the silicon substrate is liable to be oxidized, such as a resist removing process, is not to be performed after the ion implantation, is provided. At a source/drain extension region forming process after a gate electrode is formed, a pMOS region is covered with a resist, and As or P is implanted to an nMOS region by low energy implantation. After removing the resist from the pMOS region, a cover insulation film with about 20 nm thickness is disposed on the whole surface of a silicon substrate. The cover insulation film only at the pMOS region is removed by etching back, and a thin film side wall is formed on the gate electrode of the pMOS region. By removing the resist at the nMOS region, a hard mask is formed at the nMOS region, this hard mask works as a mask at the nMOS region when pMOS extension is performed.

Abstract: A method of fabricating an HV-I/O ESD MOS device comprising the following steps. A structure having a first device region, a second device region and an HV-I/O ESD MOS device region is provided. A gate is formed over an oxide layer within the first device region. A gate is formed over an oxide layer within the second device region. A gate is formed over an oxide layer within the HV-I/O ESD MOS device region. The first device gate oxide layer is thinner than the second device gate oxide layer and the HV-I/O ESD MOS device gate oxide layer. The gate and oxide layers within each region have exposed side walls. An LV-LDD mask is formed over the gate and the structure within the second device region. An LV-LDD implant is performed into the structure adjacent the first device gate and the HV-I/O ESD MOS device gate to form first device LV-LDD implants and HV-I/O ESD MOS device LV-LDD implants. The LV-LDD mask is removed. An HV-LDD mask is formed over the gate and the structure within the first device region.

Abstract: A mixed voltage CMOS process for high reliability and high performance core transistors and input-output and analog transistors with reduced mask steps. A patterned silicon nitride film 160 is used to selectively mask various implant species during the formation of the LDD regions 180, 220, and the pocket regions 190, 230 of the core transistors 152, 154. The LDD regions 240, 200 of the I/O or analog transistors 156, 158 are simultaneously formed during the process.

Abstract: A semiconductor substrate having a first conductivity type is first prepared. Then, a well region is formed in the substrate so as to have a second conductivity type opposite to the first conductivity type. Next, a first ion having the first conductivity type is implanted into the well region to form a region to be a first drain region having a first impurity density and into the substrate to form a region to be a first channel stopper region. Next, a second ion having the second conductivity type is implanted into the well to form a region to be a second channel stopper region and into the substrate to form a region to be a the second drain region having a second impurity density. Then, the respective ion implanted regions are thermally diffused to form the first drain region and the second channel stopper region in the well region and to form the second drain region and the first channel stopper region in the substrate.

Abstract: An efficient method for fabricating dual well type structures uses the same number of masks used in single well type structure fabrication. In a preferred embodiment, the current invention allows low voltage and high voltage n-channel transistors and low voltage and high voltage p-channel transistors to be formed in a single substrate. One mask is used for forming a diffusion well, a second mask for both forming a retrograde well and doping the well to achieve an intermediate threshold voltage in that well, and a third mask for both differentiating the gate oxides for the low voltage devices and doping the threshold voltages to achieve the final threshold voltages.

Abstract: There is provided a method of fabricating a semiconductor device, including the steps of (a) forming first well regions in a semiconductor substrate in all regions in which high-voltage and low-voltage MOS transistors are to be formed, the semiconductor At e having a first conductivity and the first well regions having a second conductivity, (b) forming an isolation layer on the semiconductor substrate for isolating the first well regions from each other, (c) forming high-voltage well regions having a first conductivity and low-voltage well regions one of which has a first conductivity and another of which has a second conductivity, and (d) forming MOS transistors on the high-voltage and low-voltage well regions. The high-voltage and low-voltage well regions are formed with the isolation layer being used as a mark. The above-mentioned method makes it possible to form low-voltage and high-voltage MOS transistors on a common semiconductor substrate in the smallest number of fabrication steps.

Abstract: A method for fabricating a metal-oxide semiconductor (MOS) transistor. A substrate having a gate structure is provided. The method of the invention includes forming a liner spacer on each side of the gate structure and a low dopant density region deep inside the substrate. The low dopant density region has a lower dopant density than that of a lightly doped region of the MOS transistor. Then a interchangeable source/drain region with a lightly doped drain (LDD) structure and an anti-punch-through region is formed on each side of the gate structure in the low dopant density region. The depth of the interchangeable source/drain region is not necessary to be shallow.

Abstract: A fabrication method for a metal oxide semiconductor transistor is described. A source/drain implantation is conducted on a substrate beside the spacer that is on the sidewall of the gate to form a source/drain region in the substrate beside the spacer. A self-aligned silicide layer is further formed on the gate and the source/drain region. A portion of the spacer is removed to form a triangular spacer with a sharp corner, followed by performing a tilt angle implantation on the substrate to form a source/drain extension region in the substrate under the side of the gate and the spacer with the sharp corner. A thermal cycle is further conducted to adjust the junction depth and the dopant profile of the source/drain extension region.

Abstract: The present invention provides a method and apparatus for providing a polysilicon type-1 ESD transistor in a flash memory chip. The method and apparatus include providing a select gate transistor that includes a gate, a floating gate, a medium doped junction, and a source and drain. The method and apparatus further include forming the source and drain by performing a lightly doped drain (LDD) mask and etch, performing a LDD spacer deposition and LDD spacer etch, and performing a N+ implant mask and a N+ implant.

Abstract: A new cascaded NMOS transistor output circuit with enhanced ESD protection is achieved. A driver PMOS transistor has the source connected to a voltage supply, the gate connected to the input signal, and the drain connected to the output pad. A dummy PMOS transistor has the source and the gate connected to the voltage supply, and the drain connected to the output pad. A driver NMOS cascaded stack comprises first and second NMOS transistors. The first NMOS transistor has the source connected to ground and the gate connected to the input signal. The second NMOS transistor has the gate connected to the voltage supply, the source connected to the first NMOS transistor drain, and the drain connected to the output pad. A p− implanted region underlies the n+ region of the drain but does not underlie the n+ region of the source. A dummy NMOS cascaded stack comprises third and fourth NMOS transistors. The third NMOS transistor has the gate and the source connected to ground.

Abstract: A method of manufacturing a flash memory semiconductor device that eliminates the step of forming sidewall spacers on n-channel and p-channel transistor gate structures. Resist spacers having a dimension of Gn+2Sn are formed on n-channel transistor gate structures and an N+ implant is performed to form N+ implant is performed to form N+ regions in the n-channel substrate region. Resist spacers having a dimension of Gs +2Sp are formed on p-channel transistor gate structures and a P+ implant is performed to form P+ regions in the p-channel substrate region.

Abstract: (issue) It is an issue to suppress variation in threshold voltage due to deterioration in shot channel characteristics and improve the slow trap characteristics of the MOS transistor for suppressing variation in threshold voltage of the transistor for a long-term use. (means for solving the issue) fluorine ions are implanted into a surface of a silicon substrate 1 but a peripheral region of a gate electrode on a p-MOS formation region. A first heat treatment is carried out for removing inter-lattice silicon atoms generated upon ion-implantation. Thereafter, a second heat treatment is carried out for diffusing fluorine ions into a region directly under the gate electrode. The first heat treatment is a lamp anneal such as RTA, and the second heat treatment is a furnace anneal.

Abstract: Method for producing an NMOS, PMOS or CMOS semiconductor device with reduced substrate current and increased device lifetime. A source-gate-drain device is fabricated having a moderately doped source region, a lightly doped source region, a gate or channel region, a lightly doped drain region, and a moderately doped drain region, arranged consecutively in that order, with the channel region adjacent to the gate having opposite electrical conductivity type to the electrical conductivity type of the source and drain regions. The source region and drain region are formed by ion implantation with ion kinetic energies of 40 keV or more, to increase the width and depth of charge carrier flow in these regions and to thereby reduce the substrate current associated with the device to less than one &mgr;Amp/&mgr;m.

Abstract: A method of creating a nitride, programmable read only memory (NROM) cell includes the step of decoupling injection of channel hot electrons into a charge trapping layer of the NROM cell from injection of non-channel electrons into the charge trapping layer. The step of decoupling can include the step of minimizing the injection of the non-channel electrons into the charge trapping layer. Alternatively, it includes the step of minimizing the generation of the non-channel electrons. The present invention includes cells which have minimal injection of non-channel electrons therein.

Abstract: In the fabrication of a 0.10 micron CMOS integrated circuit, a high-energy plasma etch is used to pattern a polysilicon layer and an underlying gate oxide layer to define gate structures. A thermal oxide step anneals silicon exposed and damaged by this etch. Instead of using this thermal oxide as a blocking layer for a source/drain extension implant, it is removed so as to expose the silicon surfaces of the source/drain regions. A TEOS deposition results in a carbon-bearing silicon dioxide layer in contact with the surfaces of the crystalline source/drain regions. A boron PMOS source/drain extension implant is performed through this carbon-bearing blocking layer. Subsequent steps result in the formation of sidewall spacers, heavily doped source/drain sections, submetal dielectric, an intermetal dielectric interconnect structure, and passivation. The relatively high interstitial recombination rate of the carbon-bearing blocking layer attracts a flow of interstitial silicon.

Abstract: A DRAM semiconductor device has: a semiconductor substrate with one surface; a first well and a second well respectively formed in a first region and a second region in areas of the one surface of the semiconductor substrate, the first and second wells each having a local maximum of a first conductivity type impurity concentration at a depth position apart from the one surface of the semiconductor substrate, and one of a depth and the first conductivity type impurity concentration of the local maximum of the second well is larger than that of the first well, and the other is at least equal to that of the first well; a memory cell formed in the first well; and a peripheral circuit for the memory cell formed in the second well. A DRAM semiconductor device is provided whose refresh characteristics are improved without deteriorating other characteristics.

Abstract: For forming a field effect transistor on a buried insulating material in SOI (semiconductor on insulator) technology, a gate dielectric and a gate electrode are formed on the semiconductor material, and spacers are formed on sidewalls of the gate electrode and the gate dielectric. The spacers cover portions of the semiconductor material. A dopant is implanted into exposed regions of the semiconductor material to form a drain doped region and a source doped region. A portion of the drain doped region and a portion of the source doped region extend under the spacers. A drain contact silicide is formed with an exposed portion of the drain doped region, and a source contact silicide is formed with an exposed portion of the source doped region. The spacers are removed to expose the portions of the semiconductor material including a portion of the drain doped region and a portion of the source doped region.

Abstract: A fabrication method for fabricating a dual-gate CMOSFET on a semiconductor substrate according to the present invention includes: implanting ions of N-type impurity for forming a deep junction source and drain in a first region on the semiconductor substrate where an NMOSFET is to be formed; performing a first annealing process for activating the N-type impurity; implanting ions of P-type impurity for forming a deep junction source and drain in a second region on the semiconductor substrate where a PMOSFET is to be formed; and performing a second annealing process for activating the P-type impurity. By performing the above processes in that order, the N-type impurity ions in the N+ polysilicon gate electrode of the NMOSFET are sufficiently activated, thus preventing the problem of depletion. Also, fluctuation of a threshold voltage because of penetration of the P-type impurity ions in the gate electrode of the PMOSFET can be prevented in the PMOSFET.

Abstract: High performance digital transistors (140) and analog transistors (144) are formed at the same time. The digital transistors (140) include pocket regions (134) for optimum performance. These pocket regions (134) are partially or completely suppressed from at least the drain side of the analog transistors (144) to provide a flat channel doping profile on the drain side. The flat channel doping profile provides high early voltage and higher gain. The suppression is accomplished by using the HVLDD implants for the analog transistors (144).

Abstract: Methods of forming field effect transistors and related field effect transistor constructions are described. A masking layer is formed over a semiconductive substrate and an opening having sidewalls is formed therethrough. The opening defines a substrate area over which a field effect transistor gate is to be formed. A dopant of a first conductivity type is provided through the opening and into the substrate. Sidewall spacers are formed over respective sidewalls of the opening. Enhancement dopant of a second conductivity type which is different from the first conductivity type is provided through the opening and into the substrate. A transistor gate is formed within the opening proximate the sidewall spacers, and source/drain regions of the second conductivity type are diffused into the substrate operably proximate the transistor gate. The first conductivity type dopant forms a halo region proximate the source/drain regions and lightly doped drain (LDD) regions for the transistor.

Abstract: A semiconductor substrate having a first conductivity type is first prepared. Then, a well region is formed in the substrate so as to have a second conductivity type opposite to the first conductivity type. Next, a first ion having the first conductivity type is implanted into the well region to form a region to be a first drain region having a first impurity density and into the substrate to form a region to be a first channel stopper region. Next, a second ion having the second conductivity type is implanted into the well to form a region to be a second channel stopper region and into the substrate to form a region to be a the second drain region having a second impurity density. Then, the respective ion implanted regions are thermally diffused to form the first drain region and the second channel stopper region in the well region and to form the second drain region and the first channel stopper region in the substrate.

Abstract: For use with sub-micron CMOS technologies, a gate etch process improves control of the etch profile. Gate stacks utilize N-type or P-type doped amorphous or poly silicon to enhance device performance. However, the different etching characteristics of the N-type versus the P-type amorphous or poly silicon material can result in a localized breakthrough of the underlying thin gate oxide adjacent to the edge of the gate stack, especially in the N doped active regions. According to one example embodiment, this localized breakthrough (“microtrenching”) is avoided by building the gate stacks with undoped amorphous or poly silicon to the desired configuration, masking the gate stacks with a dielectric layer, planarizing the dielectric layer and then implanting the N-type or P-type species into the selected gate stack.

Abstract: A pad oxide layer is formed on a substrate, wherein the thickness of the pad oxide layer is about greater than 250 Å. The alignment photo-resist layer is selectively patterned by a conventional lithography method to define the N-well region. The pad oxide layer is partially etched by using etch method with the alignment photo-resist pattern as a mask until the thickness of the pad oxide layer is about 100 Å to form an alignment mark. The N-type ion-implant is performed by the alignment photo-resist pattern as a mask to form an N-doped region in the substrate. Then, the alignment photo-resist pattern is removed. The P-well photo-resist is defined and formed on the pad oxide layer, then performing a P-type ion-implant through the pad oxide layer into the substrate by means of the P-well photo-resist as a mask to form a P-doped region. Then remove the P-well photo-resist and proceed with the drive-in process to form the N-well region and P-well region.

Abstract: Integration of dual voltages on a single chip can be accomplished with a minimum of extra masks by optimizing only the MDD implant of the peripheral transistors, while other implants remain the same for both transistor types. This meets lifetime specifications without unnecessary expense.

Abstract: A new method for forming ultra-shallow junctions for PMOSFET while reducing short channel effects is described. A semiconductor substrate wafer is provided wherein there is at least one NMOS active area and at least one PMOS active area. Gate electrodes are formed in both the NMOS and PMOS areas. N-type source/drain extensions are implanted into the NMOS area. The wafer is annealed whereby the n-type source/drain extensions are driven in. Thereafter, p-type source/drain extensions are implanted in the PMOS area wherein the p-type source/drain extensions are not subjected to an annealing step. Spacers are formed on sidewalls of the NMOS and PMOS gate electrodes. Source/drain regions are implanted into the NMOS and PMOS areas wherein the source/drain regions are self-aligned to the spacers to complete formation of an integrated circuit device.

Abstract: In the manufacture of CMOS devices, the n+ gate is partially counterdoped with boron to produce a modified p-type FET that has improved short channel effects, reduced gate induced drain leakage and gate oxide fields for improved reliability. A doped polysilicon layer is formed over a silicon or silicon oxide substrate, and is counterdoped with boron to a level of about 1×1013/cm2 to 5×1016/cm2 to adjust the work function but without changing the essentially n-type character of the gate electrode. This single counterdoping step achieves improved results for sub-micron devices below 0.5 micron at low cost. For CMOS device manufacturing, the alternating n-type and p-type devices are made in similar manner but reversing the n-type and p-type dopants.

Abstract: A solid imaging device including: a semiconductor substrate of a first conductivity type; a layer of a second conductivity type formed on a surf ace of the semiconductor substrate, the layer at least including a photosensitive portion of the second conductivity type; and a MOS transistor of the second conductivity type coupled to the photosensitive portion, wherein the solid imaging device further includes a layer of the first conductivity type in at least a channel region of the MOS transistor of the second conductivity type, the layer of the first conductivity type having an impurity concentration which is higher than an impurity concentration of the semiconductor substrate, and wherein at least a portion of a boundary of the layer of the second conductivity type is in direct contact with the semiconductor substrate.

Abstract: A transistor having reduced series resistance and method for producing the same. The method reduces transistor series resistance by implanting nitrogen into an nLDD/Source/Drain extension region of the transistor. The nitrogen implantation in connection with the implantation of a conventional n-type dopant (e.g. arsenic or phosphorus), results in a transistor having low series resistance, reduced hot carrier effects and no significant increase in source/drain extension overlap.

Abstract: A contact opening to a silicon substrate within which a metal contact is to be formed is cleaned by soft sputter etch to clean the substrate surface and remove any residue which would interfere with formation of a continuous silicide layer across the contact region. Contact profile protrusion at the interface between two dielectrics forming the insulating material through which the contact opening is formed is also reduced by the soft sputter etch. A barrier is formed over the contact region utilizing two discrete deposition steps, preferably separated by an interval of time and employing different process parameters, to provide a shift in the grain boundaries between the two barrier layers, creating diffusion traps at grain discontinuities inhibiting the diffusion of metal through the barrier layer. Performance of the barrier layer in preventing junction spiking is thereby increased.

Abstract: A method of forming CMOS integrated circuitry includes, a) providing a series of gate lines over a semiconductor substrate, a first gate line being positioned relative to an area of the substrate for formation of an NMOS transistor, a second gate line being positioned relative to an area of the substrate for formation of a PMOS transistor; b) masking the second gate line and the PMOS substrate area while conducting a p-type halo ion implant into the NMOS substrate area adjacent the first gate line, the p-type halo ion implant being conducted at a first energy level to provide a p-type first impurity concentration at a first depth within the NMOS substrate area; and c) in a common step, blanket ion implanting phosphorus into both the NMOS substrate area and the PMOS substrate area adjacent the first and the second gate lines to form both NMOS LDD regions and PMOS n-type halo regions, respectively, the phosphorus implant being conducted at a second energy level to provide an n-type second impurity concentration

Abstract: A method for fabricating a semiconductor resistor in embedded FLASH memory applications is described. In the method a gate array (9) is formed on a semiconductor substrate. Isolations regions (70) are removed and the exposed silicon implanted forming diffused regions (180). The SAS so formed can be configured to function as a resistor element (240).

Abstract: A process for forming self-aligned, twin well regions for a CMOS device, without the use of an oxidation retarding silicon nitride layer, has been developed. A first ion implantation procedure is used to place N type ions in a first portion of a semiconductor substrate, followed by a wet thermal oxidation procedure resulting in the growth of a thick silicon dioxide layer on the N type ions, in the first portion of the semiconductor substrate, while growing a thin silicon dioxide layer on a second portion of the lightly doped, P type semiconductor substrate. A second ion implantation procedure places P type ions through the thin silicon dioxide layer, into the second portion of the semiconductor substrate, while the thick silicon dioxide layer prevents the P type ions from reaching the first portion of the semiconductor substrate.

Abstract: The present invention is related to a method for forming a CMOS image sensor device. A CMOS image device has a first MOS device acting as a source follower of an active pixel, a second MOS device acting as a row select of the active pixel. An amorphous silicon layer acts as a photo-diode area for collecting incident light over the first MOS device and the second MOS device. The amorphous silicon layer has both N-type and P-type dopants.

Abstract: A method for fabricating a semiconductor substrate includes forming a silicide layer at a predetermined portion of a semiconductor substrate, implanting two or more impurity ions before annealing, and forming an impurity region in the semiconductor substrate by annealing the silicide layer and by diffusing the impurity ions from the silicide layer into the semiconductor substrate. Accordingly, the present invention can improve reliability and performance of a semiconductor device by reducing dopant loss and leakage current of a PN junction in the substrate and by decreasing a sheet resistance of the silicide layer. The dose of the second implanter ions is about one hundred to one thousand times less than the dose of the first implanted ions.

Abstract: A MOS field effect transistor for reducing the resistance between a source and a drain includes a gate insulation layer and a gate electrode sequentially formed on a semiconductor substrate includes deep source/drain regions formed in upper portions of the semiconductor substrate at both sides of the gate electrode. Source/drain extension regions are formed in upper portions of the semiconductor substrate extending from the deep source/drain regions toward a channel region below the gate electrode to be thinner than the deep source/drain regions. A first silicide layer having a first thickness is formed on the surface of each of the deep source/drain regions. A second silicide layer having a second thickness thinner than the first thickness of the first silicide layer is formed to extend from the first silicide layer in a predetermined upper portion of each of the source/drain extension regions.

Abstract: An MOS device is provided using indium as a threshold adjust implant in the channel regions of an NMOS device and/or in the conductive gate overlying the channel region in a PMOS device. Indium ions are relatively immobile and achieve location stability in the areas in which they are implanted. They do not readily segregate and diffuse in the lateral directions as well as in directions perpendicular to the silicon substrate. Placement immobility is necessary in order to minimize problems of threshold skew and gate oxide thickness enhancement. Additionally, it is believed that indium atoms within the channel region minimize hot carrier effects and the problems associated therewith.

Abstract: A short channel insulated gate field effect transistor has within the semiconductor body that houses the transistor a buried layer of the same conductivity type as the body but of higher impurity concentration. The buried layer is below the channel region and essentially extends only the distance between the drain and source regions of the transistor. The process to form the device provides high concentration in the region under the gate to suppress lateral depletion region expansion, while keeping a gradual junction in the vertical direction.

Abstract: Wells of n- and p-type are formed in a p-type substrate. Wells of p-type are also formed in the n-type well. Both the p-type wells are formed by the same process at the same time to make MOS transistors have different threshold voltages. MOS transistors having a long gate length and a low threshold voltage are formed in the p-well in the n-well, and MOS transistors having a short gate length and a high threshold voltage are formed in the p-well at the outside of the n-well. Fuses are formed over the p-type wells in the n-type well at a high density.

Abstract: Methods of forming a MOS transistor having dual gates minimizes impurity channeling and diffusion that can occur during impurity injection and activating processes. A method of fabricating the transistor includes the steps of forming a first conduction type well and a second conduction type well in a semiconductor substrate having an isolation region and an active region formed therein. Then, a gate oxide film is formed on an entire surface of the substrate, and a polysilicon layer is deposited on the gate oxide film preferably at a temperature of about 660° C. to about 700° C. and a pressure of about 10 to about 300 Torr. Next, portions of the polysilicon layer and the gate oxide film are selectively removed to form a gate electrode on each of the wells. Impurity ions are injected, having a conduction type opposite a conduction type of the corresponding well, into an exposed surface of each of the wells, to form lightly doped impurity regions.

Abstract: A method for manufacturing a semiconductor device in which ROM programming ion implantation is performed by utilizing the same mask as used for implanting dopant in MOS transistors. The ROM programming ion implantation is conducted under the same conditions as the MOS transistor forming step. Only a single mask needs to be modified for the programming, thus reducing cost and complexity of manufacturing the device.

Abstract: A method for fabricating poly-spacers used in a semiconductor substrate, comprising: forming an undoped first polysilicon layer on the semiconductor substrate; performing a first ion implantation with a first angle to implant impurities into the first polysilicon layer; performing a second ion implantation with a second angle to implant the impurities into the first polysilicon layer; forming a second polysilicon layer on the first polysilicon layer; and etching the first polysilicon layer and the second polysilicon layer to form spacers.

Abstract: A nonvolatile semiconductor memory device includes an n-type region which is in contact with n+ drain diffusion region at a surface of p-type silicon substrate and covers the periphery thereof. The device also includes a p-type impurity region which is in contact with n-type region and covers the periphery thereof. The n+ drain diffusion region, n-type region and p+ impurity region extend to region located immediately under the floating gate electrode. Thereby, the nonvolatile semiconductor memory device has a structure which can promote injection of high energy electrons along a gate electrode direction.

Abstract: A circuit device that includes a gate overlying an area of a semiconductor substrate, a well formed in the substrate proximate a first edge of the gate and doped with a first concentration of a first dopant, a channel region doped with a first concentration of a second dopant underlying a portion of the gate adjacent the well, a non-conducting region formed in the first portion of the well, and a contact to the second portion of the well distal from the first edge of the gate.

Abstract: In a semiconductor device and method for manufacturing the same, a buried insulating layer is formed on a semiconductor substrate, multiple depletion regions of a first conductivity type are formed on the buried insulating layer and separated from one another, a field oxide layer is formed among the depletion regions of the buried insulating layer, a gate oxide layer is formed on the depletion regions, a gate is formed on the gate oxide layer, impurity regions that are heavily doped with impurities of a second conductivity type is formed in the depletion regions on both sides of the gate to define a source and drain, and a counter doping layer that is lightly doped with impurities of the second conductivity type is formed under the channel defined by a portion of the depletion regions positioned between the impurity regions.

Abstract: A method of forming DRAM circuitry includes, a) defining a memory array area on a substrate for formation of first conductivity type DRAM field effect transistors and defining an area peripheral to the array on the substrate for formation of second conductivity type transistors; b) providing a plurality of patterned gate lines within the array area and the peripheral area, the gate lines defining respective source areas and drain areas adjacent thereto; c) providing capacitor storage nodes over selected array source areas; d) providing a capacitor dielectric layer and an electrically conductive capacitor cell plate layer over the storage nodes and the peripheral area; and e) in two separate photomasking and two separate etching steps, etching the cell plate layer to substantially remove cell plate material from the peripheral area and provide bit line contact openings through the cell plate layer to selected drains in the array area.