Abstract: The method of the present invention is to fabricate a CMOS device without boron penetration. Firstly, a gate oxide layer is formed on a semiconductor substrate. A first silicon layer is formed upon the gate oxide layer. Thereafter, a second silicon layer is stacked on the first silicon substrate, and N type dopant is in situ doped into the second silicon layer, and then a third silicon layer is stacked upon the second silicon layer. A gate structure is formed by patterning the stacked silicon layers, and source/drain structures with LDD regions are subsequently formed in the substrate by ion implantation processes. Finally, a thermal treatment is performed to form shallow source and drain junction in the substrate, thereby achieving the structure of the CMOS device. Meanwhile, the N type dopant is driven to the boundaries of stacked silicon layers of gate structure so as to act as diffusion barriers for suppressing boron penetration.

Abstract: The method of manufacturing a semiconductor integrated circuit device, which has an n-channel MIS transistor and a p-channel MIS transistor formed in the same semiconductor substrate, comprises ion implantation processes using the same photoresist as masks. The ion implantation processes include a step of injecting an impurity ion into the semiconductor substrate 1 to form the source and drain of an n-channel MOSFET 3n, a p type semiconductor region 4p for suppressing the short channel effect, and an n-well power supply region 10n, and a step of injecting an impurity ion into the semiconductor substrate 1 to form the source and drain of a p-channel MOSFET 3p, an n type semiconductor region 4n for suppressing the short channel effect, and a p-well power supply region 10p.

Abstract: After a source-drain region is formed, fluorine 24 is ion-implanted into the entire surface of a substrate and thereafter a heat treatment is conducted, for example, at 600 to 800° C. Through this heat treatment, the dangling binds and the Si—H bonds in the channel regions 26 are substituted by the Si—F bonds, which prevents the generation of the negative bias temperature instability effect in a MOSFET.

Abstract: A method of forming CMOS integrated circuitry includes, a) providing a series of gate lines over a semiconductor substrate, a first gate line being positioned relative to an area of the substrate for formation of an NMOS transistor, a second gate line being positioned relative to an area of the substrate for formation of a PMOS transistor; b) masking the second gate line and the PMOS substrate area while conducting a p-type halo ion implant into the NMOS substrate area adjacent the first gate line, the p-type halo ion implant being conducted at a first energy level to provide a p-type first impurity concentration at a first depth within the NMOS substrate area; and c) in a common step, blanket ion implanting phosphorus into both the NMOS substrate area and the PMOS substrate area adjacent the first and the second gate lines to form both NMOS LDD regions and PMOS n-type halo regions, respectively, the phosphorus implant being conducted at a second energy level to provide an n-type second impurity concentration

Abstract: A transistor is provided with a graded source/drain junction. At least two dielectric spacers are formed in sequence upon the gate conductor. Adjacent dielectric spacers have dissimilar etch characteristics. An ion implant follows the formation of at least two of the dielectric spacers to introduce dopants into the source/drain region of the transistor. The ion implants are placed in different positions a spaced distance from the gate conductor according to a thickness of the dielectric spacers. As the implants are introduced further from the channel, the implant dosage and energy is increased. In a second embodiment, the ion implants are performed in reverse order. The dielectric spacers pre-exist on the sidewall surfaces of the gate conductor. The spacers are sequentially removed followed by an ion implant. An etchant is used which attacks the spacer to be removed but not the spacer beneath to the one being removed.

Abstract: A transistor and a transistor fabrication method for forming an LDD structure in which the n-type dopants associated with an n-channel transistor are formed prior to the formation of the p-type dopants is presented. The n-type source/drain and LDD implants generally require higher activation energy (thermal anneal) than the p-type source/drain and LDD implants. The n-type arsenic source/drain implant, which has the lowest diffusivity and requires the highest temperature anneal, is performed first in the LDD process formation. Performing such a high temperature anneal first ensures minimum additional migration of subsequent, more mobile implants. Mobile implants associated with lighter and less dense implant species are prevalent in LDD areas near the channel perimeter. The likelihood of those implants moving into the channel is lessened by tailoring subsequent anneal steps to temperatures less than the source/drain anneal step.

Abstract: A method of fabricating a CMOS transistor using Si—B layer to form a source/drain extension junction is disclosed. The fabrication includes the steps as follows; First, a p-type semiconductor substrate and an n-well region are provided. Afterwards, a shallow trench isolation (STI) is formed into the p-type semiconductor substrate and the n-well region, thereby forming a plurality of active regions therebetween. A channel is formed into the p-type semiconductor substrate and the n-well region. Then, a PMOSFET gate pattern and an NMOSFET gate pattern are formed over the p-type semiconductor substrate and the n-well region. A first defined photoresist layer is formed over the n-well region. Afterwards, the n−-type dopant is implanted into the p-type semiconductor substrate to form an n−-type lightly doped source/drain. Then the first defined photoresist layer is removed. A first dielectric layer is deposited over the p-type semiconductor substrate and the n-well region.

Abstract: In a method for fabricating a highly activated shallow abrupt doped junction in a semiconductor substrate, a first dopant is implanted into a predetermined surface of the semiconductor substrate to form a preamorphization junction having a first predetermined depth from the predetermined surface of the semiconductor substrate. Furthermore, a second dopant is implanted into the preamorphization junction with a dopant profile along a depth of the semiconductor substrate from the predetermined surface of the semiconductor substrate. A peak of the dopant profile is located at a fraction of the first predetermined depth of the preamorphization junction. A silicidation RTA (Rapid Thermal Anneal) is performed to form silicide on the semiconductor substrate. The silicidation RTA (Rapid Thermal Anneal) recrystallizes the preamorphization junction from the first predetermined depth of the preamorphization junction up to an unrecrystallized depth of the preamorphization junction.

Abstract: A twin-well CMOS integrated circuit device includes an n-well region and a p-well region. Each of the n-well and p-well region includes spaced-apart regions which serve as drain and source regions, a channel region between the spaced-apart regions, a shallow trench isolation structure contiguous with one of the spaced-apart regions, and a doped diffused region extending from the surface of the well region, around and underneath the trench isolation structure, to a region beneath the contiguous spaced-apart region.

Abstract: A method of fabricating conductive plugs of different conductive types in contact with different conductivity type semiconductor regions of a semiconductor substrate. The method of the present invention utilizes a simplified two-step masking process and results in a semiconductor device having low resistance conductive plugs of two different conductivity types. The conductive plugs may be formed from conductive materials such as doped polysilicon or refractory metal. If a refractory metal is used, a barrier layer of titanium nitride or titanium oxynitride is used to form the outer layer of the conductive plug.

Abstract: A DMOS device structure includes a lightly doped semiconductor layer of a first conductivity type, a plurality of lightly doped semiconductor regions of a second conductivity type extending from a top surface of the lightly doped semiconductor layer thereinto, source regions of the first conductivity type contained in the lightly doped semiconductor regions and defining channel regions. The lightly doped semiconductor regions are contained in respective enhancement regions of the lightly doped semiconductor layer of the same conductivity type as, but with a lower resistivity than, the lightly doped semiconductor layer.

Abstract: A method of fabricating a high-voltage device suitable for a low-voltage device. A well formed by ion implantation in the high-voltage device region serves as a drift region for fabricating the high-voltage device. Therefore, one mask is used to define a portion of the wells of the high-voltage device region and the wells of low-voltage device region. It is not necessary to use multiple masks to pattern the well of the low-voltage device region and the drift region of the high-voltage device region.

Abstract: A method for forming both n and p wells in a semiconductor substrate using a single photolithography masking step, a non-conformal oxide layer and a chemical-mechanical polish step. A screen oxide layer is formed on a semiconductor substrate. A barrier layer is formed on the screen oxide layer. The barrier layer is patterned to form a first opening in the barrier layer over regions of the substrate where first wells will be formed. We implant impurities of a first conductivity type into the substrate to form first wells. In a key step, a non-conformal oxide layer is formed over the first well regions and the barrier layer. It is critical that the non-conformal oxide layer formed using a HDPCVD process. The non-conformal oxide layer is chemical-mechanical polished stopping at the barrier layer. The barrier layer is removed using a selective etch, to form second openings in the remaining non-conformal oxide layer over areas where second well will be formed in the substrate.

Abstract: A method of forming a CMOS sensor. Shallow first doped regions are formed in a provided substrate beside a gate electrode which is on the substrate. One of the shallow first doped region is defined as a source/drain area. Another of the shallow first doped region is defined as a sensor area. A spacer is formed on the sidewall of the gate electrode. A second doped region is formed within the predetermined sensor area by implanting. In the predetermined sensor area, the second doped region is deeper than the first doped region. The sensor region is composed of the first doped region and the second doped region.

Abstract: A static random access memory cell is given increased stability and latch-up immunity by using N-type gate NMOS transistors and P-type gate PMOS transistors in the control and sensing circuits, but using the same gate conductivity type for both the NMOS and PMOS memory cell transistors. For example, both NMOS and PMOS memory cell transistors have N-type gates. Weakening the memory cell load transistors by lightly doping the source and/or drain regions further enhances stability.

Abstract: A low cost method of producing proper source/drain junctions and transistor characteristics is disclosed. Through consolidation of masking steps, source/drain processing has a significantly lower cost with no performance loss. A blanket boron implant is employed as both a PLDD implant for the PMOS and a halo region implant for the NMOS. After formation of sidewall spacers on the gates, a masked arsenic and phosphorous implant is employed as a N+ implant. Because the phosphorous drives in faster than the arsenic, the desired N+/NLDD/halo architecture is generated. A masked boron implant is then employed as the P+ implant. Thus, the source/drain junctions are formed using only two masked implants. In an alternative embodiment, a third masked implant of phosphorous is used to form the NLDD junction prior to the sidewall spacer deposition instead of phosphorous being implanted with the arsenic.

Abstract: A method for manufacturing a CMOS semiconductor device having a first conductivity type (1st-type) MOS transistor including a gate electrode made of a 1st-type polysilicon film of high impurity concentration and a second conductivity type (2nd-type) MOS transistor including a gate electrode made of a 2nd-type polysilicon film of high impurity concentration on a single semiconductor substrate, comprising the steps of: forming a polysilicon film on the substrate; forming a first resist mask on the polysilicon film so as to cover a 2nd-type MOS transistor formation region, followed by implanting a 1st-type impurity at a high concentration into the polysilicon film by using the first resist mask; removing the first resist mask; forming a second resist mask on the polysilicon film so as to cover a 1st-type MOS transistor formation region, followed by implanting a 2nd-type impurity at a high concentration into the polysilicon film by using the second resist mask; etching the 2nd-type polysilicon film by a specific

Abstract: A method for doping a poly depleted semiconductor transistor, the semiconductor transistor including a gate region, a source region adjacent the gate region and a drain region adjacent the gate region and opposite the source region, the method comprising steps of exposing the gate region to a first ion implantation and shielding the gate region from a second ion implantation step.

Abstract: A novel transistor with a low resistance ultra shallow tip region and its method of fabrication in a complementary metal oxide semiconductor (CMOS) process. According to the preferred method of the present invention, a first gate dielectric and a first gate electrode are formed on a first portion of a semiconductor substrate having a first conductivity type, and a second gate dielectric and a said gate electrode are formed on a second portion of semiconductor substrate having a second conductivity type. A silicon nitride layer is formed over the first portion of the semiconductor substrate including the first gate electrode and over the second portion of the semiconductor substrate including the second gate electrode. The silicon nitride layer is removed from the second portion of the silicon substrate and from the top of the second gate electrode to thereby form a first pair of silicon nitride spacers adjacent to opposite sides of the second gate electrode.

Abstract: To obtain a semiconductor device which prevents an increase in the resistance of a source/drain region; which operates fast and stably; and which provides a high manufacturing yield, and to obtain a method of manufacturing the semiconductor device. A recess 8 is formed on a first low impurity-concentration region 5 with the exception of the area immediately below side wall insulating material 6y, and a layer damaged as a result of formation of the side wall insulating material 6y is removed. Further, a second low impurity-concentration region 10 is formed below the recess 8.

Abstract: An implementation of sensor-driven run-to-run process control for semiconductor wafer fabrication integrates a robust, automated Fourier transform infrared reflectometer onto a wafer fabrication cluster tool. Cell controller software integrates an adaptive run-to-run controller, process tool recipe upload and download through a SECS port, sensor control, data archiving, and a graphical user interface.

Abstract: An integrated circuit fabrication process is provided for forming a transistor in which the channel length is mandated by the width of a gate conductor formed upon a gate dielectric having a dielectric constant greater than about 3.8. The thickness of the gate dielectric may be made sufficiently large to serve as a mask during subsequent implantation of impurities into a substrate. The gate conductor and the gate dielectric are first patterned using lithography and an etch step. In one embodiment, a masking layer is then formed across a select portion of the gate conductor and an ensuing source region of the substrate. The uncovered portion of the gate conductor is etched to expose a region of the gate dielectric. A first implant of impurities is forwarded into regions of the substrate not covered by the masking layer to form an LDD area underneath the exposed region of the gate dielectric and a heavily doped drain region laterally adjacent the LDD area.

Abstract: An integrated circuit is disclosed that includes a semiconductor substrate, an oxide layer on the substrate, and a polysilicon layer on the oxide layer. The polysilicon layer extends away from the substrate and is doped with elemental boron to increase electrical conductivity thereof. Boron difluoride atoms are implanted in the substrate to define corresponding source and drain regions. Initially, the boron difluoride ions also penetrate a portion of the polysilicon layer. At least a portion of the polysilicon layer is removed to substantially reduce the fluorine-induced migration of boron through the oxide layer to the substrate.

Abstract: A method of fabricating a dual gate. A first conductive type region and a second conductive type region isolated by an isolation structure is provided. A polysilicon layer is formed on the first and the second conductive type regions. A diffusion layer containing second type conductive ions is formed on a second part of the polysilicon layer which covers the second conductive type region. First conductive ions are implanted into a part of the first conductive region which covers the first conductive type region. A first thermal process is performed. A metal layer is formed, and a second thermal process is performed, so that the metal layer is transformed into a metal silicide layer. A dielectric layer is formed on the metal layer. The dielectric layer, the metal silicide layer, diffusion layer, and the polysilicon layer are patterned to form a dual gate.

Abstract: In one aspect of the invention, a semiconductor processing method includes: a) providing a semiconductor substrate; b) defining a first conductivity type region and a second conductivity type region of the semiconductor substrate; c) providing a first transistor gate over the first type region which defines a first source area and a first drain area operatively adjacent thereto; d) providing a second transistor gate over the second type region which defines a second source area and a second drain area operatively adjacent thereto; and e) blanket implanting a conductivity enhancing dopant of the second conductivity type through the first source and drain areas of the first conductivity region and the second source and drain areas of the second conductivity region to provide second conductivity type regular LDD implant regions within the substrate operatively adjacent the first transistor gate and to provide second conductivity type halo implant regions within the substrate operatively adjacent the second trans

Abstract: Disclosed is a method for fabricating semiconductor device, which has the steps of: forming a device separation region to section a first device forming region and a second device forming region on a substrate with a SOI structure; forming gate oxide film on the first and second device forming regions; introducing first conductivity type impurity and second conductivity type impurity into the first and second device forming regions to form a channel region of a first channel type transistor by the first conductivity type impurity and to form a source-drain region of the first channel type transistor by the second conductivity type impurity on at least the first device forming region; and introducing the first conductivity type impurity and the second conductivity type impurity selectively into the second device forming region to form a channel region and a source-drain region of a second channel type transistor on the second device forming region.

Abstract: A PMOS or CMOS device includes an active region with a shallow heavy atom p-type implant. The PMOS device has a substrate, at least one gate electrode disposed on the substrate, and first and second doped active regions disposed adjacent to the gate electrode. The first active region has a higher concentration of a p-type heavy atom dopant material than the second active region. In one method of forming the PMOS device, spacers are formed on sidewalls of the gate electrode. A first p-type dopant material is selectively implanted into active regions adjacent to the gate electrode using the spacers as a mask. Then a portion of one of the spacers is removed to form a thinner spacer and a second p-type dopant material is selectively implanted into a first one of the active regions using the thinner spacer as a mask. The second p-type dopant material is a heavy atom species.

Abstract: In a split gate process for dual voltage chips, the N-type high-voltage transistors which are part of the ESD protection circuit, and therefore have the thicker gate oxide of the high-voltage transistors, can receive channel doping and drain extender doping which is the same as the core transistors. This causes these transistors to develop a high substrate current during an ESD event, triggering the protection circuit.

Abstract: A high voltage transistor, formed in a bulk semiconductor material, has a gate region defined by a relatively thick field oxide and a source and drain on opposite sides of the field oxide.

Abstract: The present invention provides a method for forming a CMOS transistor on a semiconductor wafer. The semiconductor wafer comprises a substrate, a first gate positioned on the substrate being used to form a PMOS transistor of the CMOS transistor, and a second gate positioned on the substrate being used to form an NMOS transistor of the CMOS transistor. First spacers are formed on both lateral surfaces of the first gate and of the second gate. A first ion implantation process is performed to form a pair of first doped regions in the substrate, oppositely adjacent to the first gate, the pair of first doped regions to serve as heavy doped drain (HDD) of the PMOS transistor. Then the thickness of the first spacers is reduced. A second ion implantation process is performed to form a pair of second doped regions in the substrate, oppositely adjacent to the second gate, the pair of second doped regions to serve as the HDD of the NMOS transistor. Second spacers are then formed covering each first spacer.

Abstract: The invention is directed to a process for forming p+ and n+ gates on a single substrate. A polycrystalline silicon or amorphous silicon layer is formed on a substrate with n-type and p-type regions formed therein and with a layer of silicon dioxide formed thereover and the structure is subjected hobo a low temperature anneal. A layer of metal silicide is then formed over the structure and n-type and p-type dopants are implanted into the resulting structure. A nitrogen implant is selectively performed in the portion of the metal silicide layer overlying a field oxide region that separates the n-type region from the p-type region in the substrate surface. The nitrogen implant reduces the amount to which the p-type dopant diffuses through the silicide layer and into the n+ gates. A dielectric material is then formed over the structure and patterned, after which the structure is subjected to additional processing steps to form gate stacks over the n-regions and the p-regions of the substrate.

Abstract: A method of forming a MOS transistor. According to the method of the present invention, a pair of source/drain contact regions are formed on opposite sides of a gate electrode. After forming the pair of source/drain contact regions, semiconductor material is deposited onto opposite sides of the gate electrode. Dopants are then diffused from the semiconductor material into the substrate beneath the gate electrode to form a pair of source/drain extensions.

Abstract: A microelectronic device includes a first region having a first conductivity type. A second region having a second conductivity type contacts the first region at a junction therebetween. A metal silicide region contacts the second region at a contact surface apart from the junction. Impurities of the second conductivity type in the second region are concentrated between the contact surface and the junction, for example, in one or more subregions disposed between the contact surface and the junction. The subregions may include a first subregion adjacent the junction formed by an ion implantation at a first energy level, and a second subregion disposed between the first subregion and the contact surface formed by a second ion implantation at a different energy level. Related fabrication methods are also provided.

Abstract: Since a field effect MOS transistor can be formed with a reduced number of manufacturing processes, a semiconductor integrated circuit device can be materialized at a low cost. A semiconductor device has a structure in which a gate electrode is provided in the vicinity of the surface of a semiconductor substrate through a gate insulating film, a second conductive type heavily doped impurity region is provided in a region adjacent to a part of the gate electrode through a part of the gate insulating film and a part of a thick oxide film, another second conductive type heavily doped impurity region is provided in a region adjacent to an opposite part of the gate electrode opposing the part of the gate electrode through the part of the gate insulating film and a part of another thick oxide film, and a first conductive type heavily doped impurity region for device isolation is provided so as to surround the gate electrode and the second conductive type heavily doped impurity regions.

Abstract: Semiconductor devices of different conductivity types are formed on a semiconductor substrate using a minimal number of critical masks. Embodiments include forming conductive gates on the main surface of the semiconductor substrate, and disposable nitride spacers on the sidewalls of the gates. A photoresist mask is then formed on gates and portions of the main surface intended to be implanted with impurities of a first conductivity type. Moderate or heavy source/drain implants of a second impurity type are then formed in the substrate, the disposable spacers on the unmasked gates are then removed, and lightly or moderately doped source/drain extension implants of the second impurity type are formed in the substrate. The first mask is then removed and a second photoresist mask is formed on the previously uncovered gates and implanted portions of the main surface.

Abstract: A masking process for forming first and second ion-doped regions on a substrate of a semiconductor device. An oxide layer and a first nitride layer are formed on the substrate in order. The first nitride layer is etched using a photolithography process to form a first predetermined pattern which exposes portions of the oxide layer. The exposed portions of the oxide layer are then etched using the first predetermined pattern as an etching mask, until portions of the substrate corresponding to the first ion-doped regions are exposed. Next, first ions are doped into the exposed portions of the substrate using the first predetermined pattern as a doping mask. The first predetermined pattern is removed. A second nitride layer is then formed over the substrate and the patterned oxide layer. Portions of the second nitride layer are removed to reveal the top of the patterned oxide layer, forming a second predetermined pattern on the substrate.

Abstract: Disclosed is a manufacturing method of semiconductor device which can simplify the manufacturing procedures for transistors with different gate insulation film thickness in the same substrate. According to the present invention, a manufacturing method for semiconductor device having NMOS and PMOS transistors with gate insulation films of different thickness from each other, is formed by the following processes. First, a semiconductor substrate in which a low voltage NMOS transistor region, a high voltage NMOS transistor region, a low voltage PMOS transistor region, and a high voltage PMOS transistor region are defined by isolation films, is provided. Next, a N well is formed in the low and high voltage PMOS transistor regions and threshold voltage adjustment ions for high voltage PMOS transistor are then implanted into the N well.

Abstract: The present invention includes forming gate structures having a nitride cap on the substrate. An ion implantation is used to dope ions into the substrate to form the lightly doped drain (LDD) structures. An oxide layer is formed on the gate structures. Subsequently, the oxide layer is etched back to form oxide spacers on the side walls of the gate structures. Next, an ion implantation with a tilted angle relative to the normal line of the substrate is used. The tilted angle is about 30 to 90 degrees respect to the substrate. The ions pass through the spacers, gate oxide and into the substrate under a portion of the gate by controlling the energy of the ion implantation. The spacers also doped with ions during the implantation. The energy of the ion implantation is about 5 to 150 KeV, and the dosage of the ion implantation is about 5E12 to 2E15 atoms/cm.sup.2. The cap silicon nitride layer is then removed.

Abstract: A semiconductor device having memory cells, high-voltage CMOS transistors, and low-voltage, deep sub-micron CMOS transistors is formed in a process that allows the same low-voltage device parameters to be used regardless of whether the low-voltage transistors are formed with or without the memory cells and the high-voltage CMOS transistors.

Abstract: The present invention discloses a high voltage semiconductor device with high breakdown voltage without increment in area occupied an increase in the size of junction region. Each junction region includes: (i) a first impurity region of a first conductivity type of a low impurity concentration formed at a predetermined position in the semiconductor substrate, (ii) a second impurity region of a second conductivity type of a medium impurity concentration formed in the first impurity region, a part of the second impurity region being exposed to the surface of the substrate, and (iii) a third impurity region of a first conductivity type of a high impurity concentration, the third impurity region being in contact with the second impurity region, wherein a reverse bias is applied to the third impurity region.

Abstract: A method of fabricating a semiconductor device includes the steps of preparing a semiconductor substrate having a first region and a second region, forming a first gate electrode and a second gate electrode over the semiconductor substrate at the first and second regions, respectively, implanting a first impurity ion into the substrate of the first region using the first gate electrode as a mask, implanting a second impurity ion into the substrate of the second region using the second gate electrode as a mask, forming sidewall spacers at both sides of each of the first and second gate electrodes, and implanting the second impurity ion into the first and second regions using the first and second gate electrodes and the sidewall spacers as masks.

Abstract: A CMOS semiconductor device having NMOS source/drain regions formed using multiple spacers has at least one NMOS region and at least one PMOS region. A first n-type dopant is selectively implanted into an NMOS active region of the substrate adjacent a NMOS gate electrode to form a first n-doped region in the NMOS active region. A first NMOS spacer is formed on a sidewall of the NMOS gate electrode and a first PMOS spacer on a sidewall of a PMOS gate electrode. A second n-type dopant is selectively implanted into the NMOS active region using the first NMOS spacer as a mask. A p-type dopant is selectively implanted into a PMOS active region using the first PMOS spacer as a mask to form a first p-doped region in the PMOS active region. A second NMOS spacer and a second PMOS spacer are formed adjacent the first NMOS spacer and first PMOS spacer, respectively.

Abstract: A semiconductor device include: a substrate of a conductivity type; a first well provided in the substrate and of the same conductivity type as the conductivity type of the substrate; a second well provided in the substrate and of an opposite conductivity type to the conductivity type of the substrate; and a buried well provided at a deep position in the substrate and of the opposite conductivity type to the conductivity type of the substrate. A buried well of the same conductivity type as the conductivity type of the substrate is further provided so as to be in contact with at least a part of a bottom portion of the first well so that the first well is at least partially electrically connected to the substrate.

Abstract: The present invention relates to a method for fabricating semiconductor devices having triple wells, the present invention has an effect as follows. The present invention provides carrying out N-well and P-well and R-well ion implantation using a mask for implanting two wells after forming an element isolation oxide film, defining an accurate well region by forming wells having an accurate profile due to activating impurity ions in accordance with the thermal process, and improving the punch characteristic between a well and a well.

Abstract: A method of fabricating a transistor is provided. According to the method, a heavy ion is implanted into a silicon substrate so as to amorphize at least a portion of the silicon substrate. The amorphized silicon is substantially free of channels. A dopant is subsequently implanted into the amorphized silicon, and the amorphized silicon substantially contains the implanted dopant. Thereafter, a silicon implanting step is performed to create an excess of vacancies to interstitials within a predetermined range. Enhanced diffusion of the dopant within the predetermined range is mitigated because of the excess of vacancies to interstitials within this predetermined range.

Abstract: An N-type impurity is ion-implanted in the exposed surface of a semiconductor substrate, thereby forming N-type diffusion layers. A P-type impurity is ion-implanted in the semiconductor substrate covered with a cover film, thereby forming P-type diffusion layers. A compound film of a semiconductor and a metal is formed on each of the surfaces of the N-type and P-type diffusion layers.

Abstract: Methods are described to prevent the inherent latchup problem of CMOS transistors in the sub-quarter micron range. Latchup is avoided by eliminating the low resistance between the V.sub.dd and V.sub.ss power rails caused by the latchup of parasitic and complementary bipolar transistor structures that are present in CMOS devices. These goals have been achieved without the use of guard rings by using p-region implants in the n-well to disconnect the pnp collector to npn base connection of two parasitic bipolar transistors. Further, the p-region implants are shorted to a reference voltage V.sub.ss via a p.sup.+ ground tab thus backbiasing the diode-like p-region implants. The proposed methods are compatible with CMOS processes.

Abstract: An asymmetrical N-channel IGFET and a symmetrical P-channel IGFET are disclosed. The N-channel IGFET includes heavily doped and ultra-heavily doped source regions, and lightly doped and heavily doped drain regions. The P-channel IGFET includes lightly doped and heavily doped source and drain regions.

Abstract: A CMOS device and a method for forming the same is provided so as to overcome the problem of boron penetration through the thin gate oxide of P-channel devices. Silicon is implanted into the polysilicon gate electrode of the PMOS device functioning as a diffusion barrier for preventing boron penetration through the thin gate oxide and into the semiconductor substrate. As a result, the reliability of the CMOS device will be enhanced.

Abstract: This invention discloses a DMOS power device supported on a substrate of a first conductivity type functioning as a drain. The DMOS power device includes a polysilicon-over-double-gate-oxide gate disposed on the substrate includes a polysilicon layer disposed over a double-gate-oxide structure having a central thick-gate-oxide segment surrounded by a thin-gate-oxide layer with a thickness of about one-fourth to one-half of a thickness of the thick-gate-oxide segment. The DMOS power device further includes a body region of a second conductivity type disposed in the substrate underneath the thin-gate-oxide layer around edges of the central thick-gate-oxide segment the body region extending out laterally to a neighboring device circuit element. The DMOS power device further includes a source region of the first conductivity type disposed in the substrate encompassed in the body region having a portion extending laterally underneath the thin-gate-oxide layer.