Abstract: There is provided a semiconductor device having a COB type DRAM, which comprises a first insulating film formed on a semiconductor substrate, first wiring trenches formed in a first insulating film in the first region, second wiring trenches formed in the first insulating film in the second region to have a substantially same depth as the first wiring trenches, first wirings buried in lower portions of the first wiring trenches, a second insulating film buried in upper portions of the first wiring trenches and formed of material different from the first insulating film, and second wirings formed of same conductive material as the first wirings in the second wiring trenches and formed thicker than the first wirings. Accordingly, the pattern precision of the bit lines and the wirings that have a different film thickness can be increased, and through holes that are formed between the bit lines in the self-alignment manner are formed shallow, and also resistances of the bit lines and the wirings are reduced.

Abstract: A non-volatile memory cell and a high voltage MOS transistor on the same semiconductor chip without changing the characteristic of the non-volatile memory cell. A gate insulating film of a MOS transistor is formed using the steps of forming an oxide film 12 formed on a floating gate 14 of a split-gate type non-volatile memory cell and of forming a tunneling insulating film 16 formed on the floating gate 14 and the oxide film 12. The gate insulating film 13 of the MOS transistor is formed by a stacked layer of the oxide film 12 and tunneling insulating film 16. Thus, the quantity of heat treatment in the entire production process undergoes no change, and the optimized characteristic of the non-volatile memory undergoes no change.

Abstract: In a method of manufacturing a semiconductor device capable of reducing gate resistance by increasing the width of a conductive layer formed on a gate electrode without increasing the gate length, an extension is formed in an upper surface of a silicon substrate, and thereafter a silicon oxide film and a silicon nitride film are deposited on the overall surface. Then, the silicon nitride film and the silicon oxide film are anisotropically etched in this order. Then, another silicon oxide film is deposited on the overall surface and thereafter anisotropically etched. Then, ion implantation is performed through a gate electrode and a side wall serving as masks, to form an impurity region. Silicon is grown under conditions having selectivity for a silicon oxide film, to form a silicon growth layer. Then, cobalt is deposited on the overall surface and thereafter heat treatment is performed to form a cobalt silicide layer. Thereafter unreacted cobalt is removed.

Abstract: An impurity concentration profile that improves pn junction breakdown voltage and mitigates the electric field, and that does not adversely affect the characteristics of a field effect transistor is realized. An n type source/drain region is formed at a silicon substrate. A p type impurity concentration profile. includes respective peak concentrations at a dope region for forming a p type well, a p type channel cut region, and a p type channel dope region. An impurity concentration profile of the n type source/drain region crosses the p type impurity concentration profile at a low concentration, and includes phosphorus implantation regions indicating impurity concentrations respectively higher than those of the p type channel cut region and the p type channel dope region and respective peaks in impurity concentration at the neighborhood of respective depth thereof.

Abstract: An apparatus and method for fabrication a hexagonally symmetric cell, (e.g., a dynamic random access memory cell (100)). The cell can comprise a bitline contact (38), storage node contacts (32) hexagonally surrounding the bitline contact (38), storage nodes (36) also surrounding the bitline contact (38), a wordline (30) portions of which form field effect transistor gates. Large distances between bitline contacts (38) and storage node contact (32) cause large problems during photolithography because dark areas are difficult to achieve when using Levenson Phaseshift. Because Levenson Phaseshift depends on wave cancellations between nearby features, commonly known as destructive interferences, the resultant printability of the pattern is largely a function of the symmetry and separation distances. When non-symmetries in the pattern occur, the result is weaker cancellations of fields (i.e. between features) and a large loss of image contrast and depth of focus during the printing step.

Abstract: When a through hole 17 is transferred on a pair of contact holes 10 putting a data line DL therebetween, even if a pair of through holes 17 putting the data line DL therebetween are deviated, the pair of through holes are connected to the contact hole 10b and not connected to the data line DL. By this manner, a mask pattern formed by a photomask is use so as to be deviated and disposed in a direction separately from the data line DL at a design stage. This results in improvement of an alignment tolerance of the pattern.

Abstract: A semiconductor device comprises a first MOSFET and a second MOSFET. The first MOSFET includes a first gate insulating film formed on a semiconductor substrate and having a relatively large thickness and a first gate electrode composed of a polysilicon film formed on the first gate insulating film The second MOSFET includes a second gate insulating film formed on the semiconductor substrate and having a relatively small thickness and a second gate electrode composed of a metal film made of a refractory metal or a compound of a refractory metal and formed on the second gate insulating film.

Abstract: A process for making a capacitor for a silicon-on-insulator (SOI) structure. The SOI structure has a p-type silicon base layer, a buried oxide layer, a silicon layer, and an n+ layer formed within a portion of the p-type silicon base layer. The process comprises the steps of forming a buried oxide layer and a silicon layer in the p-type silicon base layer, forming an n+ layer in a portion of the p-type silicon base layer, and forming electrically conductive paths to the p-type silicon base layer and the n+ layer extending through the buried oxide and silicon layers.

Abstract: A method of forming a line of FLASH memory cells includes forming a first line of floating gates over a crystalline silicon semiconductor substrate. An alternating series of SiO2 isolation regions and active areas are provided in the semiconductor substrate in a second line adjacent and along at least a portion of the first line of floating gates. The series of active areas define discrete transistor source areas. A masking layer is formed over the floating gates, the regions and the areas. A third line mask opening is formed in the masking layer over at least a portion of the second line. Anisotropic etching is conducted of the SiO2 isolation regions exposed through the third line mask opening substantially selectively relative to crystalline silicon exposed through the third line mask opening using a gas chemistry comprising a combination of at least one non-hydrogen containing fluorocarbon having at least three carbon atoms and at least one hydrogen containing fluorocarbon.

Abstract: A method for fabricating an embedded dynamic random access memory (DRAM) is provided. The method contains implanting ions onto the substrate at a DRAM active area and a logic circuit with different dopant concentration. A thermal oxidation process is performed to form a DRAM gate oxide layer with a greater thickness than that of a logic gate oxide layer. A DRAM MOS transistor is formed at a DRAM region and a logic MOS transistor is formed at a logic region. The DRAM MOS transistor has a polycide gate structure. The logic transistor has a first self-aligned silicide (Salicide) layer on its gate structure, and a second Salicide on its interchangeable source/drain region. A dielectric layer is formed over the substrate. A contact opening is formed in the dielectric layer by patterning the dielectric layer to expose the interchangeable source/drain region of the DRAM transistor. A stack capacitor is formed on the dielectric layer.

Abstract: A manufacturing method of a semiconductor device obtaining performances respectively required in a MOS transistor in semiconductor memories and a MOS transistor in logic devices even in case of manufacturing a system LSI combining the semiconductor memories with the logic devices. Forming silicide films 7 in a logic device region 11 makes it possible to reduce the resistivity of diffusion regions 9 and a conductive film 4 of polysilicon or the like that will serve as an electrode of a resulting MOS transistor. Therefore, the semiconductor devices can be manufactured in which such the MOS transistor can be used as the MOS transistor in the logic devices that is required to operate at high speed and the MOS transistor is also formed in a DRAM or the like where miniaturization is required. Since no alternation is made of the structures of the respective MOS transistors, a semiconductor device whose performance is equivalent to that of the conventional counterpart can be manufactured.

Abstract: A fabrication method provides a single electron transistor with a reduced quantum dot size. The method includes the steps of forming a first gate insulating film on a semiconductor substrate, implanting impurity ions into source/drain regions of the semiconductor substrate to form source/drain impurity regions, forming a lower gate on the first gate insulating film over a channel region between the source/drain impurity regions, forming a second gate insulating film on the lower gate and the first gate insulating film, forming a third insulating film on the second gate insulating film, selectively removing a portion of the third insulating film over the channel region in a direction perpendicular to a direction between the source/drain impurity regions to define a groove in the third insulating film, and forming an upper gate in he groove of the third insulating film.

Abstract: The present invention provides a method for forming dual workfunction metal oxide semiconductor field effect transistors (MOSFETs) which utilizes processing steps that solve the problem of doping the dual work function MOSFETs, while providing contacts to the diffusion regions which are borderless to the gate conductors. Specifically, the present invention provides a method wherein a self-aligned insulating gate cap is formed on top of a previously defined and doped gate conductor region. The inventive method which forms an insulating cap that is self-aligned to an underlying gate conductor enables the formation of dual workfunction gate conductors and borderless diffusion contacts without the need of employing separate block masks as required by prior art processes.

Abstract: A memory device structure is provided in which the array oxide layer has a thickness that is greater than the thickness of the support oxide layer.

Abstract: A semiconductor memory device is provided, which makes it possible to increase the capacitance of capacitors in the capacitor section without degrading the withstand voltage of the capacitor dielectric. This device comprises a memory cell section including floating-gate type transistors and a capacitor section including capacitors. The memory cell section and the capacitor section are formed on a semiconductor substrate. Each of the transistors has a first gate dielectric, a floating gate, a second gate dielectric, and a control gate. Each of the capacitors has a lower electrode, a capacitor dielectric, and an upper electrode. A first part of the capacitors is/are designed to be applied with a first voltage and a second part thereof is/are applied with a second voltage on operation, where the first voltage is lower than the second voltage. Each of the first part of the capacitors has a recess formed on the lower electrode, thereby increasing its capacitance.

Abstract: In the method of manufacturing the DRAM mixed logic memory, first, a pattern of one gate electrode is formed, and then a pattern of another gate electrode is formed. A step of oxidizing a polycrystalline silicon residue is performed thereafter. Therefore, the polycrystalline silicon residue is prevented from being left and prevention of electric short circuit is allowed.

Abstract: A semiconductor device comprises a first MOSFET and a second MOSFET. The first MOSFET includes a first gate insulating film formed on a semiconductor substrate and having a relatively large thickness and a first gate electrode composed of a polysilicon film formed on the first gate insulating film. The second MOSFET includes a second gate insulating film formed on the semiconductor substrate and having a relatively small thickness and a second gate electrode composed of a metal film made of a refractory metal or a compound of a refractory metal and formed on the second gate insulating film.

Abstract: In one aspect, the invention includes a method of forming circuitry comprising: a) forming a capacitor electrode over one region of a substrate: b) forming a capacitor dielectric layer proximate the electrode; c) forming a conductive diffusion barrier layer, the conductive diffusion barrier layer being between the electrode and the capacitor dielectric layer; d) forming a conductive plug over another region of the substrate, the conductive plug comprising a same material as the conductive diffusion barrier layer; and e) at least a portion of the conductive plug being formed simultaneously with the conductive diffusion barrier layer. In another aspect, the invention includes an integrated circuit comprising a capacitor and a conductive plug, the conductive plug and capacitor comprising a first common and continuous layer.

Abstract: A semiconductor substrate is arranged to have a DRAM area in which to form at a high density gate electrodes of transistors serving as DRAM components, and a peripheral circuit area in which to form at a relatively low density gate electrodes of transistors as peripheral circuit components. A resist film is formed in corresponding relation to the gate electrodes of the DRAM. After an insulating film is etched, a resist film is formed in corresponding relation to the gate electrodes of the peripheral circuits. A conductive layer is then etched while the resist film and insulating film left in the DRAM area are being used as masks, whereby the gate electrodes are formed in the DRAM area and peripheral circuit area.

Abstract: Semiconductor processing methods of forming integrated circuitry are described. In one embodiment, memory circuitry and peripheral circuitry are formed over a substrate. The peripheral circuitry comprises first and second type MOS transistors. Second type halo implants are conducted into the first type MOS transistors in less than all of the peripheral MOS transistors of the first type. In another embodiment, a plurality of n-type transistor devices are formed over a substrate and comprise memory array circuitry and peripheral circuitry. At least some of the individual peripheral circuitry n-type transistor devices are partially masked, and a halo implant is conducted for unmasked portions of the partially masked peripheral circuitry n-type transistor devices. In yet another embodiment, at least a portion of only one of the source and drain regions is masked, and at least a portion of the other of the source and drains regions is exposed for at least some of the peripheral circuitry n-type transistor devices.

Abstract: In many mixed-signal or radio frequency Rf applications, inductors and capacitors are needed at the same time. For a high performance inductor devices, a thick metal layer is needed to increase performance, usually requiring an extra masking process. The present invention describes both a structure and method of fabricating both copper metal-insulator-metal (MIM) capacitors and thick metal inductors, simultaneously, with only one mask, for high frequency mixed-signal or Rf, CMOS applications, in a damascene and dual damascene trench/via process. High performance device structures formed by this invention include: parallel plate capacitor bottom metal (CBM) electrodes and capacitor top metal (CTM) electrodes, metal-insulator-metal (MIM) capacitors, thick inductor metal wiring, interconnects and contact vias.

Abstract: A non-volatile memory (NVM) cell is fabricated by slightly modifying a conventional logic process. The NVM cell is fabricated by forming the gate electrode of an access transistor from a first conductive layer, and then forming a capacitor structure that contacts the gate electrode. In one embodiment, the capacitor structure is fabricated by forming a crown electrode of a capacitor structure from a second conductive layer, forming a dielectric layer over the crown electrode, and then forming an plate electrode over the dielectric layer from a third conductive layer. The crown electrode contacts the gate electrode, thereby providing an electrical connection between these electrodes. A first set of thermal cycles are performed during the formation of the capacitor structure. After the capacitor structure has been formed, P+ and/or N+ ion implantations are performed, thereby forming shallow junctions on the chip (e.g., a drain region of the access transistor).

Abstract: A DRAM semiconductor device has: a semiconductor substrate with one surface; a first well and a second well respectively formed in a first region and a second region in areas of the one surface of the semiconductor substrate, the first and second wells each having a local maximum of a first conductivity type impurity concentration at a depth position apart from the one surface of the semiconductor substrate, and one of a depth and the first conductivity type impurity concentration of the local maximum of the second well is larger than that of the first well, and the other is at least equal to that of the first well; a memory cell formed in the first well; and a peripheral circuit for the memory cell formed in the second well. A DRAM semiconductor device is provided whose refresh characteristics are improved without deteriorating other characteristics.

Abstract: A memory device structure is provided in which the array oxide layer has a thickness that is greater than the thickness of the support oxide layer.

Abstract: A semiconductor memory device and a fabricating method thereof are provided. In the course of forming a buried contact hole after forming a bit line pattern, the buried contact hole is formed by a self aligned contact process using capping layers included in the bit line pattern, thereby securing an overlap margin. Formation of a deep inner cylinder type capacitor unit prevents a bridge defect between lower electrodes of the capacitor and suppresses the occurrence of particles while simplifying the fabrication process. Furthermore, a mechanism for forming a second metal contact hole can simplifies the problems related to etching and filling of the second metal contact hole.

Abstract: A method for forming a lower electrode structure of a capacitor of a semiconductor device, includes the steps of: forming an active region in a semiconductor substrate; forming an insulation layer atop the semiconductor substrate having the active region formed therein; forming a contact hole in the insulation layer, the contact hole exposing the active region; forming a conductive plug connected to the active region through the contact hole, the conductive plug having an upper contact surface; forming a silicide contact on the upper contact surface of the conductive plug; forming a lower electrode layer in electrical contact with the silicide contact, by depositing titanium aluminum nitride on the insulation layer; and patterning the lower electrode layer to form a lower electrode having an upper surface. A natural oxide film is prevented from generating between the interface of the plug and the lower electrode.

Abstract: A method of fabricating a vertical transistor of a memory cell is disclosed. Accordinng to this method, a semiconductor substrate is first provided. A pad layer is formed on the surface of the substrate. A deep trench is formed in the substrate. In the deep trench, a trench capacitor is formed, a collar oxide layer is then formed on the sidewalls above the trench capacitor. A first conductive layer is formed above the trench capacitor. A second conductive layer is deposited to form a buried strap and an opening. A first insulating layer and a second masking layer are formed and fill the opening. The pad layer, the substrate, the second masking layer, the first insulating layer, the collar oxide layer and the first conductive layer are patterned. A second insulating layer is deposited and forms a Shallow Trench Isolation. A portion of the second masking layer is removed. The pad layer is removed to expose the substrate. A well is formed in the exposed substrate after forming a third insulating layer.

Abstract: The present invention includes a DRAM technology compatible non-volatile, reprogrammable switch formed according to an DRAM optimized process flow. The non-volatile, reprogrammable switch includes a non-volatile memory cell. The non-volatile memory cell includes a first metal oxide semiconductor field effect transistor (MOSFET) formed in a semiconductor substrate. A capacitor is formed in a subsequent layer above the first MOSFET and is separated from the MOSFET by an insulator layer. A vertical electrical via couples a bottom plate of the capacitor through the insulator layer to a gate of first MOSFET. A second MOSFET is formed in the semiconductor substrate. The gate of the first MOSFET also serves as a gate of the second MOSFET. Additional MOSFETs can be combined in a similar fashion with the non-volatile cell to create a new, powerful logic cell that is smaller and more robust than conventional circuit solutions.

Abstract: A semiconductor memory device comprises a memory cell region having an array of plurality of memory cells, and a peripheral circuit region to which a bit line connected to a predetermined number of the memory cells in the memory cell region is extended and connected, the bit line in the memory cell region and the bit line in the peripheral circuit region having substantially the same upper surface height.

Abstract: Disclosed is a method of forming a capacitor for a semiconductor memory device according to the present invention. The method includes the steps of: forming a lower electrode on a semiconductor substrate; performing a surface-treatment process to prevent a natural oxide layer from generating on the surface of the lower electrode; forming a TaON layer on the upper part of the surface-treated lower electrode by a reaction of Ta chemical vapor, O2 gas and NH3 gas; crystallizing the TaON layer; and forming an upper electrode on the upper part of the TaON layer, wherein the TaON layer is formed in a low pressure chemical vapor deposition (LPCVD) chamber equipped with a shower head injecting Ta chemical vapor, O2 gas and NH3 gas on an upper part thereof and at a temperature of 300 to 600° C. with pressure of 0.

Abstract: There is provided a semiconductor memory device including a first area in which peripheral circuits are to be formed and a second area in which memory cells are to be formed, the semiconductor memory device including (a) at least one capacity electrode formed in the second area, (b) at least one dummy pattern formed in the first area, and (c) an insulating film formed over the first and second areas, the dummy pattern having such a height that a height of the insulating film in the first area is equal to a height of the insulating film in the second area. For instance, the dummy pattern has the same height as a height of the capacity electrode. The semiconductor memory device can have a completely planarized surface.

Abstract: A dynamic random access memory (DRAM) includes a plurality of memory cells aligned with one another along a pair of wordlines with each wordline being connected to access alternate ones of the memory cells. The DRAM has aligned memory cells having cell areas of 6F2 yet exhibiting substantially the same superior signal-to-noise performance found in DRAM's having staggered 8F2 memory cells. The DRAM memory cells are formed by transistor stacks which are aligned along and interconnected by wordlines extending between and included within the transistor stacks. By forming the wordlines as a part of the transistor stacks, the wordlines are narrow ribbons of conductive material. During formation of the transistor stacks, the wordlines are connected so that a first wordline controls access transistors of every other one of the memory cells and a second wordline controls the access transistors of the remaining memory cells.

Abstract: A semiconductor memory device has a plurality of memory cells arranged in a matrix array, wherein each memory cell has a transistor and a capacitor and the transistor includes a vertical channel.

Abstract: A method for producing a storage cell includes forming a polycrystalline silicon layer on a semiconductor body having at least one selection transistor disposed in a first plane. An interspace is formed between two adjacent structures of the layer and one of the adjacent structures of the layer is placed on a surface of a first silicon plug. A cell plate electrode is formed in the interspace and a trench is formed in the layer. The trench reaches as far as the first plug surface and is filled with an insulating layer. The layer is removed. A storage capacitor having a high-epsilon or ferroelectric dielectric and a storage node electrode is formed. The capacitor is disposed in a second plane in and above the body. The insulating layer is replaced with silicon to form a second silicon plug directly connected to the first plug. The second plug is electrically connected to the storage node electrode, and the first plane is electrically connected to the second plane through the first and second plugs.

Abstract: A method of manufacturing a semiconductor device having a high Vth MOS FET and a low Vth MOS FET which have respective gate insulating films different in thickness from each other without covering the gate insulating film with a resist film. A silicon oxide film on a low Vth region is etched away, and in the nitriding process a nitride film is formed on the low Vth region. The silicon oxide film on a high Vth region is etched away without forming a resist film on the nitride film. A semiconductor substrate is thermally oxidized to form relatively a thick gate insulating film on the high Vth region and also to form a thin gate insulating film on the low Vth region. Gate electrodes are formed and then impurity diffusion layers forming a source and drain region are formed.

Abstract: A method for manufacturing a capacitor is provided in the present invention. The bottom electrode of the capacitor is a polysilicon layer, and the top electrode of the capacitor is a silicide layer. Since depletion regions cannot be generated in the metal layer or the suicide layer, and the resistivity of the metal layer or the silicide layer is smaller than a conventional polysilicon layer, so that operating speed and frequency of the capacitor are both increased.

Abstract: A semiconductor memory in which a layout margin at the contact hole between wiring layers of a SRAM does not need and the wiring capacity at bit lines is reduced and the high speed processing is made to be possible is provided. The SRAM is constituted of a pair of driving transistors Qd1 and Qd2, a pair of transferring transistors Qt1 and Qt2, high resistance loads R1 and R2, a pair of bit lines BL1 and BL2, and a VCC line and a GND line. Gate electrodes of each transistor and word lines are formed at a first layer, the high resistance loads are formed at a second layer, the VCC line and the GND line are formed at a third layer, and the bit lines are formed at a fourth layer. A shared contact hole using for connecting the high resistance loads to the source/drain area of transistors does not penetrate the other conductive layers. Therefore, the layout margin between the shared contact hole and the other conductive layers becomes unnecessary and the reduction of the cell size becomes possible.

Abstract: A semiconductor device includes a gate electrode (4) on a semiconductor substrate (1) of one conductivity type with a gate insulating film (3); first and second diffusion regions (5, 10) of another conductivity type; and a contact hole (17) for electrically connecting one (first) (10) of the first and second diffusion regions (5, 10) to a lower electrode (8) of a cell capacitor for storing charge therein, and when a reverse voltage Vrev is applied as a junction application voltage between semiconductors of different conductivity types of the first diffusion region (10) and substrate (1), a leakage current Ileak flows between the first diffusion region (10) and substrate (1), and Vrev when the leakage current Ileak is Ileak=Cs×(Vbit/2)×(1/T)×(1/S) (where a charge storage capacitance in the cell capacitor is Cs, a voltage applied to a data line (12) connected to the other (second) (5) of the first and second diffusion regions (5, 10) is Vbit, a target charge retention time is T and an

Abstract: The method involves forming a N well over a cell part and a P well over a periphery part of the semiconductor substrate, etching the N well and the P well to form trenches for a storage electrode and an element isolating film, forming an insulating film over the resulting structure, thereby filling the trench on the periphery part, sequentially forming a dielectric layer pattern and a storage electrode on the trench of the cell part, forming a storage electrode, forming an intermediate layer over the resulting structure, exposing the storage electrode, forming an undoped polysilicon layer over the resulting structure, thereby connecting the undoped polysilicon layer with the storage electrode, forming a polysilicon layer pattern and an intermediate insulating pattern, and forming a MOS transistor and a bit line over the polysilicon layer pattern of the cell part and the periphery part.

Abstract: A process for fabricating a capacitor under bit line (CUM), DRAM device, featuring increased capacitance, without increasing the aspect ratio for a dry etched, narrow diameter bit line contact hole, has been developed. The process features increasing the vertical space in a capacitor opening, needed to accommodate a capacitor structure with increased vertical dimensions, via selective removal of the top portions of the polysilicon plug structures exposed in the capacitor openings. The depth of a subsequent bit line contact hole, opened to a non-truncated polysilicon plug structure, is therefore not increased as a result of the increase capacitor depth, thus not resulting in an increased aspect ratio for the dry etched, narrow diameter bit line contact hole.

Abstract: Dual gate dielectric constructions and methods therefor are disclosed for different regions on an integrated circuit. In the illustrated embodiment, gate dielectrics in memory array regions of the chip are formed of silicon oxide, while the gate dielectric in the peripheral region comprises a harder material, specifically silicon nitride, and has a lesser overall equivalent oxide thickness. The illustrated peripheral gate dielectric has an oxide-nitride-oxide construction. The disclosed process includes forming silicon nitride over the entire chip followed by selectively etching off the silicon nitride from the memory array region, without requiring a separate mask as compared to conventional processes. After the selective etch, oxide is grown over the entire chip, growing differentially thicker in the memory array region.

Abstract: A method for forming isolation trenches for a semiconductor device forms, in a substrate, a plurality of trenches having different widths including widths above a threshold size and widths below a threshold size. The plurality of trenches have a same first depth. A masking layer is deposited in the plurality of trenches, the masking layer has a thickness sufficient to both line the trenches with the widths above the threshold size and completely fill the trenches with the widths below the threshold size. A portion of the substrate is exposed at a bottom of the trenches with the widths above the threshold size by etching the masking layer. The plurality of trenches is etched to extend the trenches with the widths above the threshold size to different depths.

Abstract: In a stack type memory cell of 8F2, bit line plug electrodes for connecting bit lines to source/drain diffusion layers of active regions in an area between two word lines WL are formed extend from the source/drain diffusion layers in parallel to the word lines WL and formed longer than the minimum element isolation width F and shorter than three times the minimum element isolation width F. Thus, a DRAM which uses stack type memory cells and whose integration density can be easily enhanced can be attained.

Abstract: A pair of transistors sharing a common electrodes e.g. a bitline in a DRAM array, has a self-aligned contact to the bitline in which the transistor gate stack has only a poly layer with a nitride cover; the aperture for the bitline contact is time-etched to penetrate only between the gates and not reach the silicon substrate; exposed nitride shoulders of the gate are etched to expose the poly; the remainder of the interlayer dielectric is removed by a selective etch; the exposed poly is re-oxidized to protect the gates; and the aperture bottom is cleaned; so that the thick gate stack of a DRAM is dispensed with in order to improve uniformity of line width across the chip beyond what the DRAM technique can deliver.

Abstract: In a DRAM having a capacitor-over-bitline structure in which the capacitive insulating film of an information storing capacitive element C is formed of a high dielectric material such as Ta2O5 (tantalum oxide) film 46, the portions of bit lines BL and first-layer interconnect lines 23 to 26 of a peripheral circuit which are in contact with at least an underlying silicon oxide film 28 are formed of a W film, the bit lines BL and the interconnect lines 23 to 26 being arranged below the information storing capacitive element C, whereby the adhesion at the interface between the bit lines BL and the interconnect lines 23 to 26 and the silicon oxide film is improved in terms of high-temperature heat treatment to be performed when the capacitive insulating film is being formed.

Abstract: The present invention discloses a ferroelectric memory device and a method for fabricating the same.

Abstract: A method for fabricating a semiconductor memory with a split level folded bitline structure consisting of three contact levels, in accordance with the present invention includes forming gate structures for transistors in an array region and a support region of a substrate. First contacts are formed down to diffusion regions between the gate structures in the array region. The first contacts have a height which is substantially the same for all first contacts in the array region. Second contacts are formed between first level bitlines in the array region and a first portion of the first contacts, while forming second contacts to a first metal layer from the gate structures and diffusion regions in the support region. Third contacts are formed between second level bitlines in the array region and a second portion of the first contacts, while forming third contacts to a second metal layer from the first metal layer in the support region.

Abstract: A memory cell which comprises a substrate having a top surface; a capacitor extending vertically into the substrate for storing a voltage representing a datum, said capacitor occupying a geometrically shaped horizontal area; a transistor formed above the capacitor and occupying a horizontal area substantially equal to the geometrically shaped horizontal area, and having a vertical device depth, for establishing an electrical connection with the capacitor, in response to a control signal, for reading from, and writing to, the capacitor, wherein the transistor includes a gate formed near the periphery of said horizontal device area and having a vertical depth approximately equal to the vertical device depth; an oxide layer on an inside surface of the gate; a conductive body formed inside the oxide layer, said conductive body having a top surface and a bottom surface and a vertical depth approximately equal to the vertical device depth; and diffusion regions in the body near the top and bottom surfaces and a met

Abstract: A mask for etching a relatively thin gate insulating film formed in a gate insulating film forming region is formed by patterning a photoresist film, and the mask is used for introducing an impurity for adjusting the threshold voltages of n-channel field-effect transistors and p-channel field-effect transistors having the relatively thin gate insulating film into regions on the semiconductor substrate not covered with the mask.

Abstract: A process for fabrication of both compact memory and high performance logic on the same semiconductor chip. The process comprises forming a memory device in the memory region, forming a spacer nitride layer and a protective layer over both the memory region and the logic region, removing the protective layer over the logic region to expose the substrate, and forming the logic device in the logic region. Cobalt or titanium metal is applied over all horizontal surfaces in the logic region and annealed, forming a salicide where the metal rests over silicon or polysilicon regions, and any unreacted metal is removed. An uppermost nitride layer is then applied over both the memory and logic regions and is then covered with a filler in the logic region. Chip structures resulting from various embodiments of the process are also disclosed.