Abstract: A method for fabricating a memory cell, in particular, a DRAM memory cell, having a transistor and a trench capacitor that are connected to one another through a buried strap contact includes applying at least one diffusion barrier on an upper surface of a first filling material of the trench capacitor to prevent an undesirable outdiffusion of dopant from the first filling material. Thus, with the diffusion barrier intact, at most a dopant that is possibly present in a second filling material can outdiffuse into adjoining regions. However, the outdiffusion of dopant from the first filling material can be initiated in a targeted manner by breaking open the diffusion barrier by a thermal treatment. Through the possibility of restraining the diffusion of the dopant until a suitable point in the process, it is possible to avoid an excessive outdiffusion into a contact region with a transistor.

Abstract: A circuit and method for a memory cell with a vertical transistor and a trench capacitor. The cell includes an access transistor that is formed in a pillar of a single crystal semiconductor material. The transistor has vertically aligned first and second source/drain regions and a body region. The transistor also includes a gate that is formed along a side of the pillar. A trench capacitor is also included in the cell. A first plate of the trench capacitor is formed integral with the first source/drain region. A second plate is disposed adjacent to the first plate and separated from the first plate by a gate oxide.

Abstract: A process for producing an integrated semiconductor memory configuration, in particular one suited to the use of ferroelectric materials as storage dielectrics, in which a conductive connection between one electrode of a storage capacitor and a selection transistor is not produced until after the storage dielectric has been deposited; and a semiconductor memory configuration produced using the production process.

Abstract: A trench capacitor memory cell structure is provided with includes a vertical collar region that suppresses current leakage of an adjacent vertical parasitic transistor that exists between the vertical MOSFET and the underlying trench capacitor. The vertical collar isolation, which has a vertical length of about 0.50 &mgr;m or less, includes a first portion that is present partially outside the trench and a second portion that is present inside the trench. The first portion of the collar oxide is thicker than said second portion oxide thereby reducing parasitic current leakage.

Abstract: There is provided a semiconductor device which comprises a capacitor including a lower electrode, a dielectric film, and an upper electrode, a first protection film formed on the capacitor, a first wiring formed on the first protection film, a first insulating film formed on the first wiring, a second wiring formed on the first insulating film, a second insulating film formed on the second wiring, and at least one of a second protection film formed between the first insulating film and the first wiring to cover at least the capacitor and a third protection film formed on the second insulating film to cover the capacitor and set to an earth potential. Accordingly, the degradation of the ferroelectric capacitor formed under the multi-layered wiring structure can be suppressed.

Abstract: A method for forming an isolation trench in a silicon or silicon-on-insulator substrate is described in which a trench is formed in the semiconductor structure (containing a multiple layer structure of Si, SiO2, and SiN layers) and an undoped polysilicon layer is deposited on the bottom and sidewalls of the trench and on the surface of the region adjacent to the trench. A substantial portion of the trench is left unfilled by the undoped polysilicon layer deposited. The polysilicon layer is thermally oxidized to form a thermal oxide that fills the trench and thereby avoids forming a birds-beak formation of the thermal oxide above the sidewalls of the trench. The isolation structure may be planarized by either removing the polysilicon layer from the region adjacent to the trench before oxidation or later removing the oxide from the SiN layer and adjusting height of the oxide in the trench.

Abstract: In a gas-phase treating process of a semiconductor wafer using hydrogen, there is provided a technique for safely eliminating the hydrogen in an exhaust gas discharged from a gas-phase treating apparatus. The profile at the end portions of the side walls of gate electrodes of a poly-metal structure is improved by forming the gate electrodes over a semiconductor wafer IA having a gate oxide film and then by supplying the semiconductor wafer 1A with a hydrogen gas containing a low concentration of water, as generated from hydrogen and oxygen by catalytic action, to oxidize the principal face of the semiconductor wafer 1A selectively. After this, the hydrogen in the exhaust gas, as discharged from an oxidizing furnace, is completely converted into water by causing it to react with oxygen by a catalytic method.

Abstract: Within a method for forming a memory cell structure there is provided a field effect transistor (FET) device having electrically connected to one of its source/drain regions a storage capacitor and electrically connected to the other of its source/drain regions a bitline stud layer separated from and rising above the storage capacitor. Within the memory cell structure, and at a minimum storage capacitor to bitline stud layer separation, a capacitor plate layer is further separated from the bitline stud layer than a capacitor node layer.

Abstract: A gate insulating film 2 is formed on a DRAM circuit region 11 and a logic circuit region 12 of a semiconductor substrate, and gate electrodes 3 are formed on the gate insulating film 2. Sidewalls of the gate electrodes 3 are oxidized. A first insulating film 4 is formed all over the semiconductor substrate 1. A sidewall insulating film 41 made of a first insulating film 4 is leaved on the both sides of the gate electrodes 3. A diffusion layer 5 is formed in the semiconductor substrate 1 by implanting ions with the first insulating film 4 and the sidewall insulating film 41 as a mask. A protection film 6 is formed on the first insulating film 4 in the DRAM circuit region 11 and on the logic circuit region 12 except for specific regions 51 of the diffusion layer 5 around certain gate electrodes 3a. A silicide layer 7 is formed in an upper layer portion of the diffusion layer 5 by a salicide technique.

Abstract: The present invention provides a memory array fabricated by complementary metal-oxide-semiconductor salicide process. The memory array comprises a semiconductor substrate. Multitudes of first isolation devices are aligned in the semiconductor substrate and second isolation devices aligned on the semiconductor substrate. The alignment of the second isolation devices is parallel to one of the first isolation devices. Some polysilicon lines are on the second isolation devices therefor have null memory function. A conductive structure is below a surface of the semiconductor substrate. The conductive structure is located between the first isolation devices. A conductive contact is on the conductive structure. The correspondence of the first isolation devices and the polysilicon lines can prevent the conductive structures from short effect.

Abstract: A method of forming memory circuitry having a memory array having a plurality of memory capacitors and having peripheral memory circuitry operatively configured to write to and read from the memory array, includes forming a dielectric well forming layer over a semiconductor substrate. A portion of the well forming layer is removed effective to form at least one well within the well forming layer. An array of memory cell capacitors is formed within the well. The peripheral memory circuitry is formed laterally outward of the well forming layer memory array well. In one implementation, memory circuitry includes a semiconductor substrate. A plurality of word lines is received over the semiconductor substrate. An insulative layer is received over the word lines and the substrate. The insulative layer has at least one well formed therein. The well has a base received over the word lines. The well peripherally defines an outline of a memory array area.

Abstract: As wiring patterns in a region for connecting two line & space pattern sets having different line & space widths on a semiconductor substrate, even-numbered line patterns in a region having a smaller line & space width are connected to line patterns in a region having a larger line & space width and thicken their line widths stepwise in the middle of the lengthwise direction, and odd-numbered line patterns in the region having the smaller line & space width terminate at different positions in a connection region. Upon forming a fine wiring pattern on the connection region using photolithography, the resolution and depth of focus can be suppressed from impairing.

Abstract: Methods of forming dynamic random access memories (DRAM) are described. In one embodiment, an insulative layer is formed over a substrate having a plurality of conductive lines which extend within a memory array area and a peripheral area outward of the memory array. Capacitor container openings and contact openings are contemporaneously etched over the memory array and conductive line portions within the peripheral area respectively. In another embodiment, a patterned masking layer is formed over a substrate having a plurality of openings formed within an insulative layer, wherein some of the openings comprise capacitor container openings within a memory array and other of the openings comprise conductive line contact openings disposed over conductive lines within a peripheral area outward of the memory array.

Abstract: A method for tailoring properties of high k thin layer perovskite materials, and devices comprising such insulators are herein presented. The method comprise the steps of, first, substantially completing the manufacture of a device, which device contains the high k insulator in a polycrystalline form. The device, such as a capacitor, or an FET, went through the typically high temperature manufacturing process of a fabrication line. In the next step, the device is in situ ion implanted with such a dose and energy to convert a fraction of the polycrystalline material into an amorphous material state, hereby tailoring the properties of the insulator. The fraction of polycrystalline material converted to amorphous material might be 1. This process can be applied to many electronic devices and some optical devices. The process results in novel perovskite thin layer materials and novel devices fabricated with such materials.

Abstract: Gate structures, comprising a first insulation film, a first gate material and a gate oxide film, are formed. A second insulation film is formed on side surfaces of the gate structures in the peripheral region. Trenches are formed at a surface of the semiconductor substrate by etching the semiconductor substrate with the first and the second insulation films used as masks. The second insulation film formed on side surface of the gate structures is removed, exposing the surface of the semiconductor substrate in the vicinity of the gate structures on both sides of the trenches. Element-isolating insulation films are formed in the trenches and on the exposed substrate. The gate structures in the peripheral region are removed. Gate structures of peripheral transistors are formed between the element-isolating insulation films in the peripheral region.

Abstract: First of all, a semiconductor substrate is provided, and then a photoresist layer is formed and defined on the semiconductor substrate. The pulsed plasma doping is then performed by the photoresist layer as a mask to form a doping region and an undoping region on the semiconductor substrate. After removing the photoresist layer, performing a thermal oxidation process to form a thick gate oxide layer in the doping region and a thin gate oxide layer in the undoping region. Subsequently, two gates are respectively formed on the thick gate oxide layer and the thin gate oxide layer by means of the conventional process.

Abstract: The dynamic random access memory (DRAM) cells in a semiconductor chip are isolated from the peripheral circuitry by forming the DRAM cells directly in the substrate while the peripheral and other functional circuits are formed in wells that are isolated from the substrate. In addition to providing isolation, the placement of the DRAM cells also reduces the leakage current in the cells, thereby increasing the time that a DRAM cell can hold a charge without being refreshed.

Abstract: A semiconductor device includes a trench isolating elements, a memory cell transistor and a peripheral circuit Vcc transistor having a thermal oxide film of a first thickness, and a peripheral circuit Vpp transistor including a thermal oxide film and a thermal oxide film formed before trench formation, having a second thickness greater than the first thickness.

Abstract: A semiconductor memory has a buried bit line structure. One end of the bit line and one end of the diffused impurity layer are connected by being overlapped with each other, and the surface of the source/drain of the selection transistor and the surface of the diffused impurity layer including the connecting portion are silicidized by using metals having high melting points, Ti and Si in this case, thereby forming the titanium silicide layer thereon. This invention not only solves the various problems arising from the buried bit line structure but also realizes sure formation of the silicide, low resistance, greater fineness and high speed operation.

Abstract: A technology of preventing the threshold voltage of the transistor of a cell region from increasing and the refresh characteristic of the transistor of the cell region from deteriorating, while maintaining the characteristic of the transistor of core circuit/peripheral circuit regions of a semiconductor memory device, is provided. A semiconductor memory device comprises a first transistor comprised of a first gate, a first gate insulating film, a first source region, and a first drain region formed in core circuit/peripheral circuit regions of a semiconductor memory device having a cell region and core circuit/peripheral circuit regions, a planarized interlayer dielectric film which covers the first transistor, and a second transistor formed in the cell region, including a second source region, a second drain region, a second gate having a height corresponding to the height of the interlayer dielectric film, and a second gate insulating film.

Abstract: An isolation oxide film is formed on a silicon substrate, and a pad oxide film is formed in an active region. A lower electrode of a capacitor is formed on the isolation oxide film, and a multilayered film (ON film) comprising a silicon oxide film and a silicon nitride film is formed on the lower electrode. A mask oxide film is formed on the ON film so as to cover only the area in the vicinity of the lower electrode. The ON film is patterned by means of wet etching capable of selectively removing the silicon nitride film. The pad oxide film and the mask oxide film are removed before forming a gate oxide film. Fabrication of a capacitor and a transistor is completed by formation of gate electrodes and an upper electrode.

Abstract: A method of forming an array of FLASH field effect transistors and circuitry peripheral to the array includes etching periphery active area semiconductive material of a substrate substantially selectively relative to periphery field isolation while not etching array active area semiconductive material. After the periphery active area etching, at least some FLASH transistor control gate material is formed within the array and at least some non-FLASH transistor gate material is formed within the periphery. A method masking array active area semiconductive material while periphery active area semiconductive material is etched substantially selectively relative to the periphery field isolation. After the etching, the masking is removed. Thereafter, at least some FLASH transistor control gate material is formed within the array and at least some non-FLASH transistor gate material is formed within the periphery.

Abstract: A method of fabricating a semiconductor device, includes the steps of forming gates in a cell region and in a peripheral region of a substrate, forming a polysilicon layer over an entire surface of the resultant structure, partially removing portions of the polysilicon layer in the cell region to maintain the polysilicon layer of a predetermined thickness in the cell region, removing the predetermined thickness of the polysilicon layer both in the cell and peripheral regions, so that the resultant structure includes exposed gates in the cell region but no exposed gates in the peripheral region, and forming an insulating layer over the resultant structure.

Abstract: The semiconductor device including a memory cell region and a peripheral circuit region on a semiconductor substrate 10 comprises a transfer transistor formed in the memory cell region, a capacitor constituted by a storage electrode 46 connected to one of diffused layers 20 of the transfer transistor and formed of a first conducting layer, a dielectric film 52 covering a sidewall of the storage electrode 46, and an opposed electrode 56 formed on the dielectric film 52; a conducting plug formed of the first conducting layer and connected to the peripheral circuit region of the semiconductor substrate 10; and a first interconnection 62 electrically connected to the conducting plug 48.

Abstract: An improved method of implanting source and drain for CMOS devices is provided by a hard mask and dry etching to form polysilicon gates 20 percent longer than desired, implanting to form the source and drain of the PMOS transistor with dopant that moves faster during annealing such as Boron and then wet etching the polysilicon gates down to the shorter length such as the final length before implanting with the faster dopant such as arsenic.

Abstract: A DRAM memory cell includes a MOSFET selection transistor having a drain region and a source region in a semiconductor substrate column. A current channel, which is capable of being actuated by a control gate electrode extends in a vertical direction between the drain and source regions. A capacitor is stacked under the selection transistor and electrically connected to the source region in the semiconductor substrate column. Above the selection transistor is a metal bit line electrically connected to the drain region in the semiconductor substrate column. A metal word line in direct electrical communication with the control gate electrode of the selection transistor extends perpendicularly with respect to the metal bit line.

Abstract: A method of producing a ferroelectric semiconductor memory, includes forming a switching transistor on a semiconductor substrate, applying an insulating layer to the switching transistor and then forming a storage capacitor, with electrodes of platinum and a ferroelectric or paraelectric dielectric, on the insulating layer. In order to protect the dielectric from being penetrated by hydrogen during further process steps, a first barrier layer is embedded into the insulating layer and, after completion of the storage capacitor, a second barrier layer, which bonds with the first barrier layer, is deposited.

Abstract: The non-volatile semiconductor memory device has a booster including a capacitor, and a storage circuit including a storage element. The capacitor has a lower electrode, a capacitor capacitance insulating film and an upper electrode. The lower electrode of the capacitor is shaped to have an increased surface area.

Abstract: In one aspect, the invention provides a method of forming an integrated circuitry memory device. In one preferred implementation, a conductive layer is formed over both memory array areas and peripheral circuitry areas A refractory metal layer is formed over the conductive layer to provide conductive structure in both areas. According to a preferred aspect of this implementation, the conductive layer which is formed over the memory array provides an electrical contact for a capacitor container to be formed. According to another preferred aspect of this implementation, the conductive layer formed over the peripheral circuitry area constitutes a conductive line which includes at least some of the silicide. In another preferred implementation, the invention provides a method of forming a capacitor container over a substrate. According to a preferred aspect of this implementation, a conductive layer is elevationally interposed between an upper insulating layer and a lower conductive layer over the substrate.

Abstract: A method of forming a deep trench DRAM cell on a semiconductor substrate has steps of: forming a deep trench capacitor in the semiconductor substrate; using silicon-on-insulator (SOI) technology to form a silicon layer on the deep trench capacitor; and forming a vertical transistor on the silicon layer over the deep trench capacitor, wherein the vertical transistor is electrically connected to the deep trench capacitor.

Abstract: In a semiconductor device including a plurality of memory cells, a deposition preventing film is formed on an interlayer insulating film in which a plurality of holes are formed, or a seed film is selectively formed on the interlayer insulating film and on an inner surface and a bottom surface of the holes. A film of Ru, Ir or Pt is deposited by chemical vapor deposition on the deposition preventing film, or on the interlayer insulating film by utilizing the seed film, under the condition where underlayer dependency occurs. In consequence, lower electrodes are formed in accordance with a pattern of the deposition preventing film or the seed film. A dielectric film is formed on the lower electrodes and the deposition preventing film at a predetermined temperature. The material of the lower electrodes does not lose conduction even when exposed to the predetermined temperature employed for forming the dielectric film. Upper electrodes are further formed on the dielectric film.

Abstract: A ferroelectric capacitor with a multilayer ferroelectric film to prevent degradation of its ferromagnetic characteristics, wherein the ferroelectric film is made of a lower layer of PZT or PLZT formed on a lower electrode and an upper, titanium rich, layer of PZT, PLZT, or PbTiO3, an upper electrode formed on the upper layer of the ferroelectric film and a protective layer formed to cover the ferroelectric capacitor.

Abstract: A method of manufacturing a semiconductor device is provided. A polysilicon film and a rough-surfaced polysilicon film are formed on inter-layer insulating film including side and bottom surfaces of openings formed in inter-layer insulating film. A photoresist is formed on the rough-surfaced polysilicon film. The photoresist, the rough-surfaced polysilicon film and the polysilicon film that are located on the top surface of inter-layer insulating film are removed by the CMP method. The polysilicon film and rough-surfaced polysilicon film are etched in a predetermined atmosphere to make the position of the top end of storage nodes lower than the top surface of inter-layer insulating film.

Abstract: A method is disclosed for fabricating an MDL (Merged DRAM Logic) semiconductor device, in which suicide is formed on a logic region and a memory region selectively for enhancing device reliability. The method includes the steps of (a) providing a substrate having a first region and a second region adjoining the first region, (b) forming a first gate forming material layer in the first region, (c) forming a second gate forming material layer in the first region having the first gate forming material layer formed therein and the second region, (d) selectively patterning the second gate forming material layer to form second gates in the second region and a boundary dummy pattern layer at a boundary area of the first and second regions, and (e) selectively patterning the first gate forming material layer to form first gates in the first region.

Abstract: A novel method and structure are described for making capacitor-under-bit line (CUB) DRAM cells with improved overlay margins between bit lines and capacitor top electrodes. After insulating the FETs with a first insulating layer, a second insulating layer is deposited and first openings are etched for capacitor bottom electrodes. A first conducting layer is deposited. A photoresist layer sufficiently thick is deposited to fill the first openings and form a planar surface. A novel photomask design is used to form second openings between adjacent capacitors in the first openings and partially extending over the first openings. The second openings are recessed to the first conducting layer. The first conducting layer is removed and the underlying second insulating layer is recessed. A thin interelectrode layer is deposited.

Abstract: Methods of forming conductive lines and insulative spacers thereover are described. In accordance with one aspect of the invention, a substrate is provided having a first area and a second area relative to which conductive lines are to be formed. A layer of conductive material is formed over the first and second substrate areas and a layer of insulative material is formed over the conductive material. In a preferred implementation, insulative material is removed from the second area and conductive lines are subsequently patterned and etched in both the first and second areas. In another preferred implementation, conductive lines are first patterned and etched with insulative material in the second area being subsequently removed. The patterned and etched conducted lines have respective sidewalls.

Abstract: Two different gate conductor dielectric caps are used in the array and support device regions so that the bitline contact can be fabricated in the array region, but a thinner hard mask can be used for better linewidth control in the support device region. The thinner dielectric cap is made into dielectric spacers in the array device regions during support mask etching. These dielectric spacers allow for the array gate conductor resist line to be made smaller than the final gate conductor linewidth. This widens the array gate conductor processing window. The second dielectric cap layer improves linewidth control for the support devices and the array devices. Two separate gate conductor lithography steps and gate conductor dielectric etches are carried out in the present invention to optimize the gate conductor linewidth control in the array and support device regions. The gate conductors in the array and support devices regions are etched simultaneously to reduce production cost.

Abstract: In the formation of a semiconductor structure, where spacer formation is strongly dependent on the structure (e.g. taper), the improvement of a spacer formation on a poly stud planarized to pad nitride where an oxide is formed on top of the poly prior to the pad nitride strip, so that after pad nitride removal, the poly is etched back and nitride is deposited conformal followed by anisotropic nitride RIE etch, so that the oxide protects the nitride underneath from being etched.

Abstract: A process for manufacturing a semiconductor memory device includes double polysilicon level non-volatile memory cells and shielded single polysilicon level non-volatile memory cells in the same semiconductor material chip. A first memory cell includes a MOS transistor having a first gate electrode and a second gate electrode superimposed and respectively formed by definition in a first and a second layer of conductive material. A second memory cell is shielded by a layer of shielding material for preventing the information stored in the second memory cell from being accessible from the outside. The second memory cell includes a MOS transistor with a floating gate electrode formed simultaneously with the first gate electrode of the first cell by definition of the first layer of conductive material. The layer of shielding material is formed by definition of the second layer of conductive material.

Abstract: A memory device and method of forming the same, includes a plurality of wordlines for applying a cell driving signal, a plurality of bitlines for inputting or outputting data, and a plurality of cells, each cell having a first gate, source and drain electrodes and a second gate, wherein either the first or second gate is connected to one of the wordlines, the source electrode is connected to one of the bitlines, and the drain electrode is connected to either the first or second gate which is not connected to the one wordline.

Abstract: A semiconductor memory device includes a capacitive insulating film and an upper electrode formed at the inner surface of the cylindrical lower electrode to form a capacitive cell. Near the capacitive cell, a groove with the same depth as that of the capacitive cell is formed and electric conductive layers are formed at the inner surface thereof. The electric conductive layer and upper electrode are connected by the upper electrode extending part. At the bottom of the groove, the upper electrode contact is connected to the electric conductive layer.

Abstract: A semiconductor contact structure for a merged dynamic random access memory and a logic circuit (MDL) and a method of manufacturing the contact structure to: (i) a cell contact pad; (ii) at least one active region; and (iii) at least one gate electrode simultaneously, whereby an electric short between the gate electrodes and the cell contact pad is avoided, even in the event a lithographic misalignment occurs and whereby it is possible to obtain an overlap margin in the cell region, even with an improved metal contact to the gate electrode in the peripheral circuit region of the semiconductor device.

Abstract: A method of forming a memory device (e.g., a DRAM) including array and peripheral circuitry. A plurality of undoped polysilicon gates 58 are formed. These gates 58 are classed into three groups; namely, first conductivity type peripheral gates 58p, second conductivity type peripheral gates 58n, and array gates 58a. The array gates 58a and the first conductivity type peripheral gates 58n are masked such that the second conductivity type peripheral gates 58p remain unmasked. A plurality of second conductivity type peripheral transistors can then be formed by doping each of the second conductivity type peripheral gates 58p, while simultaneously doping a first and a second source/drain region 84 adjacent each of the second conductivity type peripheral gates 58p. The second conductivity type peripheral gates 58p are then masked such that the first conductivity type peripheral gates 58n remain unmasked.

Abstract: A memory cell. The memory cell includes an access transistor. The access transistor is formed in a pillar of single crystal semiconductor material. The transistor has first and second source/drain regions and a body region that are vertically aligned. The memory cell also includes a body contact that is coupled to the body region. A gate of the transistor is disposed on a side of the pillar that is opposite from the body contact. A trench capacitor is also included. The trench capacitor includes a first plate that is formed integral with the first source/drain region of the access transistor and a second plate that is disposed adjacent to the first plate and separated from the first plate by a gate oxide. An insulator layer that separates the access transistor and the trench capacitor from an underlying layer of semiconductor material.

Abstract: The present invention relates to a semiconductor device comprising a first MISFET group and a second MISFET group each formed on a semiconductor substrate. Upon fabrication of it, an MOSFET constituting a memory cell and an MOSFET constituting a peripheral circuit are not formed in the same step. When a side wall is formed on each side of a gate electrode of the MOSFET constituting the peripheral circuit, the memory cell region is covered and protected with a layer which is to be a gate electrode. The semiconductor device thus fabricated has no side walls in the MOSFET constituting a memory cell. According to the present invention, a semiconductor device of high reliability can be fabricated by forming one MOSFET free of side walls. Upon fabrication, it is possible to easily control the size or etching of the device, thereby widening the fabrication range.

Abstract: A method for fabricating stacked DRAM capacitors and FET structures for embedded circuits is achieved. The polysilicon capacitor bottom electrodes are formed first on the substrate in the memory regions. A single thin dielectric layer is formed over the bottom electrodes to serve as the interelectrode layer and concurrently on the device areas in the logic regions for the FET gate oxide. A second polysilicon layer is deposited and patterned to form the capacitor top electrodes and concurrently to form the FET gate electrodes. Next the lightly doped drains and source/drain contact areas are implanted to form FETs. Since the source/drain areas are formed after the DRAM capacitors are completed, the high-temperature thermal cycles for the DRAM capacitors are avoided. Therefore the FETs having shallow diffused junctions are formed without thermal degradation. The method also uses fewer processing steps to achieve these novel merged DRAM structures.

Abstract: The present invention relates to a method for forming a static random access memory (SRAM) cell. In order to avoid constantly reducing operating voltage of the SRAM cell affecting the unit stability and noise jamming of the SRAM cell during read/write processes, the invention employs different thicknesses of gate oxide layers of an access transistor and a pull down transistor. Thereby, not only the &bgr; ratio is increased, but also the unit area is decreased.

Abstract: According to the present invention, there is disclosed a 2-transistors type flash memory, wherein a memory-transistor is composed of layers of structure consisting of a floating gate and a control gate separated by a first insulating film; and, at least, a gate electrode of a select-transistor is composed of a single layer of a polysilicon film, which is formed from the same layer as the floating gate electrode of the memory-transistor and then doped to have an enhanced dopant concentration by ion implantation performed in the step of forming source-drain regions of the transistors.

Abstract: A method for manufacturing a semiconductor device including a metal contact and a capacitor. Gate structures are formed on a semiconductor substrate, and a first dielectric layer is formed on the semiconductor substrate to cover the gate structures. A bit line is formed on the first dielectric layer and a second dielectric layer is formed on the first dielectric layer to cover the bit line. A buried contact is formed to be electrically connected to the semiconductor substrate between the gate structures by etching the second dielectric and first dielectric layer. A third dielectric layer is formed on the second dielectric layer. A lower electrode of a capacitor, a dielectric layer, and an upper electrode are formed to be connected to the buried contact. A fourth dielectric layer is formed to cover the capacitor.

Abstract: A method for fabricating a semiconductor device is disclosed, which reduces defects of a device by improving the process to improve the production yield.