Including Device Responsive To Nonelectrical Signal Patents (Class 438/24)
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Patent number: 6563139Abstract: The present invention discloses a light source of full color LED (light emitted diode) by using die bond and packaging technology. A first mono-color LED chip with reflective metal on the bottom and transparent metal-oxide on the top of the chip is bonded on the PC board by thermal or ultrasonic die bond. A second mono-color LED chip with reflective metal on both sides is bonded in cascade on the first LED chip by thermal or ultrasonic die bond. The first LED chip emits light through the transparent metal-oxide to mix with the second LED light such that a different color light will obtain. The reflective metal reflects all the light to enforce the light intensity. In near field application, a red, a blue and a green LED are die bond in cascade to get a white light or full color light. In far field application, a yellow and a blue LED are die bond in cascade on the PC board, in its side is another cascaded die bond of a red and a green LED to get a white light or full color light.Type: GrantFiled: November 15, 2001Date of Patent: May 13, 2003Inventor: Chang Hsiu Hen
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Patent number: 6558970Abstract: A light irradiating device (68) having the good radiation characteristic comprises a plurality of conductive paths (51) that are electrically separated, a photo semiconductor chips (65) fixed onto desired conductive path (51), and a resin (67) for covering the photo semiconductor chips (65) to support the conductive paths (51) integrally.Type: GrantFiled: May 31, 2001Date of Patent: May 6, 2003Assignee: Sanyo Electric Co., Ltd.Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Eiju Maehara, Kouji Takahashi, Junji Sakamoto, Shigeaki Mashimo, Katsumi Okawa
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Patent number: 6555440Abstract: A method of fabricating a diode device, such as a PIN diode, includes forming top and bottom regions of opposite conductivity types and includes anisotropically etching into the top surface to form a pit having side walls that converge with approach to the bottom surface. However, the pit does not extend to the bottom surface. In the PIN diode embodiment, the pit terminates within an intrinsic region that separates a bottom surface diffusion region from a diffusion region along the walls of the anisotropically etched pit. The anisotropic etching approach provides a degree of self regulation with regard to the geometries of the pit. A process flow of steps is described, which allows thicker and larger diameter wafers to be used in the formation of an array of such diode device.Type: GrantFiled: June 5, 2000Date of Patent: April 29, 2003Assignee: Agilent Technologies, Inc.Inventor: Frank Sigming Geefay
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Patent number: 6555407Abstract: A method of carrying out the controlled oxidation of A material, such as Al(Ga)As is oxidized in a controlled manner placing it in a reactor, and causing a carrier gas containing an oxidizing vapour, such as water, at a controlled partial pressure to flow over the oxidizable Material. In this way, the reaction process can be made sensitive to only one variable.Type: GrantFiled: October 20, 2000Date of Patent: April 29, 2003Assignee: Zarlink Semiconductor ABInventors: Nicolae Pantazi Chitica, Fredrik Salomonsson, Anita Risberg
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Patent number: 6548835Abstract: An optoelectronic device having a highly conductive carrier tunneling current aperture. The device includes a centrally positioned current aperture formed from a quantum layer made of a III-IV-V semiconductor compound, which is doped with a first doping type. The current aperture is laterally confined by an oxide of the III-IV-V semiconductor compound. Adjacent layers are also formed of a semiconductor material that is doped with the first doping type.Type: GrantFiled: November 2, 2000Date of Patent: April 15, 2003Assignee: U-L-M photonics GmbHInventor: Karl Joachim Ebeling
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Patent number: 6545333Abstract: A device with an optically controlled VT is disclosed. The device includes a semiconductor die which includes an FET, the FET having a gate on an upper surface of a substrate, a body under the gate and a source contacting the body forming a body-to-source junction. A light source is provided for exposing the body to light from the lower surface of the substrate.Type: GrantFiled: April 25, 2001Date of Patent: April 8, 2003Assignee: International Business Machines CorporationInventors: Mark B. Ketchen, Edward J. Nowak, Jed H. Rankin, Keith C. Stevens
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Patent number: 6541291Abstract: In a process for producing a semiconductor light emitting device, first, a lamination including an active zone, cladding layers, and a current confinement layer is formed. Then, a near-edge portion of the lamination having a stripe width is removed so as to produce a first space, and a second near-edge portion located under the first space and a stripe portion of the lamination being located inside the first space and having the stripe width are concurrently removed so that a second space is produced, and cross sections of the active layer and the current confinement layer are exposed in the second space. Finally, the first and second spaces are filled with a regrowth layer so that a dopant to the regrowth layer is diffused into a near-edge region of the remaining portion of the active layer.Type: GrantFiled: August 23, 2001Date of Patent: April 1, 2003Assignee: Fuji Photo Film Co., Inc.Inventor: Toshiaki Kuniyasu
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Patent number: 6537839Abstract: A nitride semiconductor light emitting device having preferable light emitting characteristics even if dense threading dislocations extend through single crystal layers. The nitride semiconductor light emitting device includes an active layer obtained by depositing group-3 nitride semiconductors, and a barrier layer disposed adjacent to the active layer and having a greater bandgap than that of the active layer, the active layer having barrier portions which surround the threading dislocations and are defined by interfaces enclosing the threading dislocation and which are made of the same material as that of the barrier layer.Type: GrantFiled: November 16, 2001Date of Patent: March 25, 2003Assignee: Pioneer CorporationInventors: Hiroyuki Ota, Mitsuru Nishitsuka, Hirokazu Takahashi
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Patent number: 6525345Abstract: A semiconductor photonic device includes a Z-cut quartz substrate and a compound semiconductor layer presented by InxGayAlzN (where x+y+z=1, 0≦x ≦1, 0≦y≦1, and 0≦z≦1) formed on the Z-cut quartz substrate.Type: GrantFiled: August 5, 1999Date of Patent: February 25, 2003Assignee: Murata Manufacturing Co., Ltd.Inventor: Michio Kadota
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Patent number: 6521965Abstract: An integrated pressure sensor system and method for making such a device are provided. The pressure system includes a capacitor having an underlying electrode, a dielectric cavity, an upper electrode, and an etch cavity for removing sacrificial material from the dielectric cavity. The surface of the device is relatively flat due to epitaxal deposition of epi polysilicon and single crystal silicon. The capacitor circuit of the pressure sensor system is capable of undergoing CMOS processes without requiring additional steps of covering the capacitor device to protect it and then removing the covering following the CMOS processes.Type: GrantFiled: September 12, 2000Date of Patent: February 18, 2003Assignee: Robert Bosch GmbHInventor: Markus Lutz
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Patent number: 6521471Abstract: The invention concerns a semiconductor opto-electronic component comprising at least two optically active structures (20, 30), at least one of which consists of a detector (30), characterized in that the detector or detectors (30) comprise a first active portion (33) able to detect a signal at a given wavelength and a second inactive portion (34) only slightly sensitive to the signal to be detected and exposed to the non-guided stray light conveyed in the component.Type: GrantFiled: August 30, 2000Date of Patent: February 18, 2003Assignee: ALCATELInventors: Franck Mallecot, Christine Chaumont, Arnaud Leroy, Antonina Plais
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Patent number: 6511859Abstract: A combined IC/Mems process forms the IC parts first, and then forms the MEMS parts. One option forms a parylene overlayer, then forms a cavity under the parylene overlayer.Type: GrantFiled: March 10, 2000Date of Patent: January 28, 2003Assignee: California Institute of TechnologyInventors: Fukang Jiang, Zhigang Han, Xuan-Qi Wang, Yu-Chong Tai
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Patent number: 6504238Abstract: A semiconductor device comprising a lead frame that includes a large area mount pad having small elevated pads to which a semiconductor chip is attached. The small mount pads coupled with usage of a minimal amount of chip attach adhesive provide improved reliability against vapor phase package cracking, and further allow a given lead frame to be used by a family of chip sizes and shapes. The large pad provides good thermal dissipation, as well as stress relief during fabrication of the lead frame.Type: GrantFiled: January 18, 2001Date of Patent: January 7, 2003Assignee: Texas Instruments IncorporatedInventors: Johnny Cheng, Joyce Hsu, Joe Chiu
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Patent number: 6504183Abstract: The present invention provides a semiconductor device with reducing dislocation density. The semiconductor device includes multiple nucleuses between a substrate and an AlGaInN compound semiconductor. The dislocation density that is induced by crystal lattice differences between the substrate and the AlGaInN compound semiconductor is significantly reduced and the growth of the AlGaInN compound semiconductor is improved.Type: GrantFiled: September 8, 2000Date of Patent: January 7, 2003Assignee: United Epitaxy CompanyInventors: Chih-Sung Chang, Tzong-Liang Tsai
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Publication number: 20020195608Abstract: The invention provides a light emitting device and a semiconductor device each having improved characteristics by preventing occurrence of a damage caused by contact of a tool. On a substrate, an n-type semiconductor layer, an active layer, and a p-type semiconductor layer are stacked. On the p-type semiconductor layer, a p-side electrode is provided. The p-type semiconductor layer has a projected portion for limiting current in correspondence with a current injection area in the active layer. A projected portion is formed on the surface of the p-side electrode in correspondence with the projected portion for limiting current. On the surface of the p-side electrode, a protective portion is also provided in correspondence with the area other than the current injection area in the active layer. The top face of the protective portion is higher than that of the projected portion.Type: ApplicationFiled: August 21, 2002Publication date: December 26, 2002Inventor: Koichi Miyazaki
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Publication number: 20020190256Abstract: In the case where a material containing an alkaline metal or an alkaline-earth metal in a cathode, an anode, a buffer layer, or an organic compound layer is used, there is a fear of the diffusion of an impurity ion (representatively, alkaline metal ion or alkaline-earth metal ion) from the EL element to the TFT being generated and causing the variation of characteristics of the TFT.Type: ApplicationFiled: May 20, 2002Publication date: December 19, 2002Inventors: Satoshi Murakami, Mitsuhiro Ichijo, Taketomi Asami
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Patent number: 6495433Abstract: A method of activating a compound semiconductor layer into a p-type compound semiconductor layer is provided. In order to reduce the electrical conductivity of the compound semiconductor layer grown by a VPE method, electromagnetic waves having energy larger than the band gap of the compound semiconductor layer are irradiated and annealing is performed. If the amount of the p-type impurities contained in the layer during growth thereof increases, the resistivity of the layer increases and an annealing temperature is lowered. Also, the contact resistance between the compound semiconductor layer and an electrode is reduced.Type: GrantFiled: April 17, 2001Date of Patent: December 17, 2002Assignee: Samsung Electronics Co., Ltd.Inventor: Hyun-eoi Shin
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Patent number: 6495390Abstract: A method, apparatus and system for controlling the amount of heat transferred to a process region (30) of a workpiece (W) from exposure with laser radiation (10) using a thermally induced reflectivity switch layer (60). The apparatus of the invention is a film stack (6) having an absorber layer (50) deposited atop the workpiece, such as a silicon wafer. A portion of the absorber layer covers the process region. The absorber layer absorbs laser radiation and converts the absorbed radiation into heat. A reflective switch layer (60) is deposited atop the absorber layer. The reflective switch layer may comprise one or more thin film layers, and preferably includes a thermal insulator layer and a transition layer. The portion of the reflective switch layer covering the process region has a temperature that corresponds to the temperature of the process region.Type: GrantFiled: August 27, 2001Date of Patent: December 17, 2002Assignee: Ultratech Stepper, Inc.Inventors: Andrew M. Hawryluk, Somit Talwar, Yun Wang, Michael O. Thompson
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Patent number: 6495382Abstract: An application-specific rf optoelectronic integrated circuit having a generic chip member and a defining substrate in communication with at least one generic chip member. The generic chip member contains passive building block components that are independent from each other and being connected by paths external to the generic chip member. The external connection paths are defined by a defining substrate member having passive components for providing optical and electrical interconnection between selected building block components on the generic chip member to define the specific function of the integrated circuit. It is possible to use the same design of the generic chip for several applications merely by altering the interconnect paths on a defining substrate.Type: GrantFiled: May 25, 2001Date of Patent: December 17, 2002Assignee: Hughes Electronics CorporationInventor: Daniel Yap
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Publication number: 20020185650Abstract: The present invention provides a photocoupler capable of reducing the mount area required to mount the photocoupler on an object by eliminating a structurally unnecessary portion, and an apparatus and method for fabricating such a photocoupler. A light-receiving device and a light-emitting device placed on a pair of lead frames are embedded in a primary mold body made of a transparent resin, and the primary mold body is embedded in a secondary mold body made of a light-shading resin, to form the photocoupler. The lead frames are bent inside the secondary mold body, and the outer side of the terminal portion of each lead frame, ranging from the bent position to the top end, is exposed at the secondary mold body.Type: ApplicationFiled: May 15, 2002Publication date: December 12, 2002Inventor: Yasushi Hasegawa
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Patent number: 6492193Abstract: An optoelectronic device with a Group III Nitride active layer is disclosed that comprises a silicon carbide substrate; an optoelectronic diode with a Group III nitride active layer; a buffer structure selected from the group consisting of gallium nitride and indium gallium nitride between the silicon carbide substrate and the optoelectronic diode; and a stress-absorbing structure comprising a plurality of predetermined stress-relieving areas within the crystal structure of the buffer structure, so that stress-induced cracking that occurs in the buffer structure occurs at predetermined areas rather than elsewhere in the buffer structure.Type: GrantFiled: November 22, 2000Date of Patent: December 10, 2002Assignee: Cree, Inc.Inventors: John Adam Edmond, Hua-Shuang Kong, Kathleen Marie Doverspike, Michelle Turner Leonard
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Publication number: 20020177252Abstract: A method of manufacturing a semiconductor device is provided. The device is manufactured with use of an SOI (Silicon On Insulator) substrate having a first silicon layer, an oxide layer, and a second silicon layer laminated in this order. After forming a trench reaching the oxide layer from the second silicon layer, dry etching is performed, thus allowing the oxide layer located at the trench bottom to be charged at first. This charging forces etching ions to impinge upon part of the second silicon layer located laterally to the trench bottom. Such part is removed, forming a movable section. For example, ions to neutralize the electric charges are administered into the trench, so that the electric charges are removed from charged movable electrodes and their charged surrounding regions. Removing the electric charges prevents the movable section to stick to its surrounding portions.Type: ApplicationFiled: May 28, 2002Publication date: November 28, 2002Inventors: Hiroshi Muto, Tsuyoshi Fukada, Kenichi Ao, Minekazu Sakai, Yukihiro Takeuchi, Kazuhiko Kano, Junji Oohara
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Publication number: 20020171090Abstract: A display device is formed by burying at least part of a light emitting device in an insulating material, wherein a drive electrode for the light emitting device is formed so as to be extracted on a surface of the insulating material. A display unit is produced by two-dimensionally arraying such light emitting devices on a base body. Since the display device is modularized by burying a light emitting device finely formed in an insulating material, to re-shape the light emitting device into a size easy to handle, it is possible to suppress the production cost of the display unit using such display devices, and to ensure a desirable handling performance of the light emitting device; for example, facilitate the carrying of the light emitting device or the mounting thereof on a base body.Type: ApplicationFiled: May 15, 2002Publication date: November 21, 2002Inventors: Toyoharu Oohata, Hideharu Nakajima, Yoshiyuki Yanagisawa, Toshiaki Iwafuchi
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Patent number: 6476411Abstract: An intersubband light emitting element includes a semiconducting substrate, a first layer composed of a first semiconducting material, and a second layer composed of second semiconducting material. The first layer makes a heterojunction with the second layer. The top of a valence band of the first semiconducting material is higher in energy than the bottom of a conduction band of the second semiconducting material. The element further includes a third layer making a heterojunction with the first or second layer. The third layer has a superlattice structure. One of the first and second layer is provided on the semiconducting substrate directly or through at least one semiconducting layer.Type: GrantFiled: August 29, 2000Date of Patent: November 5, 2002Assignee: Tohoku UniversityInventors: Hideo Ohno, Keita Ohtani
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Patent number: 6472243Abstract: A capacitive pressure sensor (10) utilizes a diaphragm (38) that is formed along with forming gates (56,57) of active devices on the same semiconductor substrate (11).Type: GrantFiled: December 11, 2000Date of Patent: October 29, 2002Assignee: Motorola, Inc.Inventors: Bishnu P. Gogoi, David J. Monk, David W. Odle, Kevin D. Neumann, Donald L. Hughes, Jr., John E. Schmiesing, Andrew C. McNeil, Richard J. August
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Publication number: 20020151094Abstract: A method for the manufacturing of a Thin Film Inorganic Light Emitting Diode is disclosed. The device contains in one single layer or in a double layer a dispersion of zinc sulfide doped with a luminescent center, and a water-compatible p-type semiconductive polymer, preferably a polythiophene/polymeric polyanion complex.Type: ApplicationFiled: January 24, 2002Publication date: October 17, 2002Inventor: Hieronymus Andriessen
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Publication number: 20020145148Abstract: Semiconductor light emitting devices and methods of producing same are provided. The semiconductor light emitting devices include a substrate that has a surface including a difference-in-height portion composed of, for example, a wurtzite compound. A crystal growth layer is formed in the substrate surface wherein at least a portion of which is oriented along an inclined plane with respect to a principal plane of the substrate. The semiconductor device includes a first conductive layer, an active layer and a second conductive layer formed on the crystal layer in a stacked arrangement and oriented along the inclined place.Type: ApplicationFiled: December 17, 2001Publication date: October 10, 2002Inventors: Hiroyuki Okuyama, Masato Doi, Goshi Biwa, Toyoharu Oohata
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Patent number: 6458614Abstract: An optical electronic integrated circuit comprises: a silicon substrate; an electronic circuit formed in the silicon substrate and processing an electric signal; a ZnO film formed on at least portion of the silicon substrate; and an optical circuit electrically connected to the electronic circuit. The optical circuit includes at least one GaN-based semiconductor compound layer which is provided on the ZnO film, and the GaN-based compound semiconductor layer either receives or emits an optical signal.Type: GrantFiled: March 19, 1999Date of Patent: October 1, 2002Assignee: Murata Manufacturing Co.,Inventors: Yasushi Nanishi, Michio Kadota
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Patent number: 6455338Abstract: An integrated semiconductor laser-modulator device less affected by a fluctuating electric field due to modulating signals applied to the modulator has improved frequency characteristics. The integrated semiconductor laser-modulator includes an active layer, a beam waveguide layer having a bulk structure with a bandgap energy larger than that of the active layer but smaller than that of a laser beam absorption layer having a bulk structure, wherein waveguides of the laser and modulator are connected and aligned, and a cladding layer including a diffraction grating is disposed on top of or beneath the waveguides.Type: GrantFiled: September 21, 1999Date of Patent: September 24, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Kazuhisa Takagi, Hitoshi Tada, Tohru Takiguchi
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Patent number: 6444483Abstract: A full area of a semiconductor integrated circuit is divided into unit areas, a mask data file for use in a beam exposure system or an inspection apparatus is produced based on CAD data of the full area, full-area header information in which a starting address of a mask data of each unit area relates to positional information on said unit area, partial-area header information corresponding to each of partial areas obtained by division of the full area is produced based on the full-area header information and mask data of the partial areas are extracted from a mask data of the full area based on the partial area header information to produce the mask data files corresponding to the partial area header information.Type: GrantFiled: July 14, 2000Date of Patent: September 3, 2002Assignee: Fujitsu LimitedInventors: Masahiko Minemura, Tomoyuki Okada, Ryo Tsujimura, Kenji Kikuchi, Yoshimasa Iiduka
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Patent number: 6440778Abstract: An optical semiconductor element package including a housing, electric signal input and output wiring boards, and external leads. The housing has a metal frame and a metal bottom plate, for storing optical semiconductor elements. The electric signal input and output wiring boards are arranged in the housing at positions so that the optical semiconductor elements are not existent right above and right below the boards. The external leads are drawn to the outside through the side wall of the metal frame. The wiring boards are connected to the external leads and to the optical semiconductor elements by bonding wires. The input and output of an electric signal between the outside and the optical semiconductor elements are carried out through the bonding wires, the wiring boards and the external leads.Type: GrantFiled: July 11, 2000Date of Patent: August 27, 2002Assignee: The Furukawa Electric Co., Ltd.Inventors: Takahiro Okada, Hideaki Murata, Masato Sakata
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Publication number: 20020110947Abstract: When a plurality of semiconductor layers including a nitride compound layer containing indium are stacked on a substrate, materials of layers above the indium containing nitride compound layer are limited to specific compounds, or their growth temperatures are limited within a predetermined range, to suppress thermal deterioration of the nitride compound layer containing indium or deterioration of the interface and to thereby grow a high-quality semiconductor light emitting element using nitride compound semiconductors.Type: ApplicationFiled: April 18, 2002Publication date: August 15, 2002Applicant: KABUSHIKI KAISHA TOSHIBA.Inventors: Hideto Sugawara, Masayuki Ishikawa
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Publication number: 20020100912Abstract: A semiconductor laser package includes an island member formed of metal, including a base plane and a block member protruding in a direction substantially perpendicular to the base plane, a lead, a resin member molded integrally with the island member and the lead so as to fix the relative position relationship between the island member and the lead, a laser chip fixed at the block member, and a light receiving element functioning as a light receiving unit, directly fixed to the resin member.Type: ApplicationFiled: January 28, 2002Publication date: August 1, 2002Inventors: Takahide Ishiguro, Osamu Hamaoka
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Patent number: 6426236Abstract: Disclosed is an electroabsorption-type optical modulator, which has: a semiconductor substrate; and a semiconductor buffer layer, a semiconductor optical absorption layer and a semiconductor cladding layer which are layered in this order on the semiconductor substrate; wherein the absorption of a light wave supplied to an end of the semiconductor optical absorption layer is controlled by changing an intensity of electric field applied to the semiconductor optical absorption layer; and the semiconductor optical absorption layer has a region with absorption-edge wavelength shorter than that of the other region of the semiconductor optical absorption layer and a voltage corresponding an external electrical signal is simultaneously applied to both the regions of the semiconductor optical absorption layer, so that, to an incident light, a refractive index of the semiconductor optical absorption layer is decreased and an absorption coefficient of the semiconductor optical absorption layer is increased when an intenType: GrantFiled: August 21, 2000Date of Patent: July 30, 2002Assignee: NEC CorporationInventors: Masashige Ishizaka, Hiroyuki Yamazaki
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Publication number: 20020081760Abstract: The performance of individual detectors in pyroelectric detector arrays is improved by reducing the size of each detector as compared to the overall array size and providing each with a collection cavity which tapers from front aperture towards the detector itself.Type: ApplicationFiled: December 3, 2001Publication date: June 27, 2002Inventor: Roger W. Whatmore
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Patent number: 6410940Abstract: A micro-size LED-like optical element has an n-contact, a p-contact, and an optical active structure connected between the n-contact and the p-contact for generating light when forward biased and for detecting light when reverse biased. The optical active structure has a diameter of about 20 &mgr;m or smaller. When the the optical active structure is forward biased, it forms a micro-size LED (&mgr;LED). When the optical active structure is reverse biased, it forms a micro-size detector (&mgr;detector). An array of the micro-size optical active structures may be used as a minidisplay, a detector, or a sensor (when each structure is separately wired), or as a hyperbright LED (when the structures are wired to turn on and off simultaneously). Alternatively, a hyperbright LED may be obtained by forming a plurality of micro-size holes extending into an LED wafer.Type: GrantFiled: June 15, 2000Date of Patent: June 25, 2002Assignee: Kansas State University Research FoundationInventors: Hongxing Jiang, Jingyu Lin, Sixuan Jin, Jing Li
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Publication number: 20020066904Abstract: A solid-state relay is created by a power-switching device embedded in a semiconductor wafer which includes an optically transparent, electrically insulating surface, an organic light-emitting diode (OLED) formed on that surface, and a light-absorbing device integrated with the power-switching device, electrically isolated from the diode, and positioned in the path of the emitted light.Type: ApplicationFiled: December 4, 2000Publication date: June 6, 2002Inventors: Han-Tzong Yuan, Tae S. Kim, Francis G. Celii, Simon J. Jacobs
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Patent number: 6396297Abstract: An apparatus detects the width of a V-groove formed on a semiconductor wafer. A resistor overlaps a chip area and an area upon which the V-groove is to be etched on the wafer. A pad etched on the silicon wafer is coupled to the resistor. A tester supplies voltage to the pad after the V-groove has been etched into the silicon wafer; and a circuit coupled to the pad determines the width of the etched V-groove.Type: GrantFiled: December 14, 2000Date of Patent: May 28, 2002Assignee: Xerox CorporationInventors: Paul A. Hosier, Paul W. Browne, Scott L. TeWinkle
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Patent number: 6388275Abstract: A compound semiconductor device based on gallium nitride which can have a thick gallium nitride semiconductor layer serving to prevent cracks or defects attributable to a strain caused by a difference in lattice constant or coefficient of thermal expansion. Between a contact layer 4 consisting of a film of n-type GaN and a clad layer 5 consisting of a film of a n-type AlyGa1−yN is interposed a crack-preventive buffer layer 5 having both of the compositions of the two films.Type: GrantFiled: May 2, 2000Date of Patent: May 14, 2002Assignee: Sanyo Electric Co., Ltd.Inventor: Takashi Kano
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Patent number: 6372532Abstract: An LED device that emits light in a pattern is disclosed. The LED device is a layer of active material that is sandwiched between a transparent substrate with an anode formed thereon and a cathode. The active material has a layer of light emitting material that emits light when electron/hole recombination is induced in the material. The patterned emission is defined by a patterned layer in the active material of the LED device. The patterned layer has at least a first thickness and a second thickness. When the device is on, the portion of the device associated with the first thickness of the patterned layer is visually distinct from the portion of the device that is associated with the second thickness of the patterned layer.Type: GrantFiled: January 5, 2001Date of Patent: April 16, 2002Assignee: Lucent Technologies, Inc.Inventors: Zhenan Bao, John A. Rogers
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Patent number: 6372533Abstract: A process for use in fabrication of a semiconductor device is disclosed. The fabricated semiconductor device includes a top oxide aperture within a top oxidation layer and a bottom oxide aperture within a bottom oxidation layer precisely positioned relative to each other, and an electrical contact to a contact layer between the top and bottom oxidation layers. The process includes the following steps: etching past one of the oxidation layers and stopping in the contact layer, etching one or more holes traversing the top and bottom oxidation layers, and simultaneously oxidizing both oxidation layers. Etching past both oxidation layers in the same alignment step ensures that the centers of the two apertures, as formed through selective oxidation, will be aligned.Type: GrantFiled: March 13, 2001Date of Patent: April 16, 2002Assignee: Gore Enterprise Holdings, Inc.Inventors: Vijaysekhar Jayaraman, Jonathan Geske
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Patent number: 6368889Abstract: An object is to provide a variable-wavelength light-emitting element which employs a direct gap semiconductor having a magnetic moment for a semiconductor layer serving as an active layer, so that the semiconductor has reduced crystal distortion and stable characteristics as the active layer of the light-emitting element, as well as a method of fabricating the variable-wavelength light-emitting element. A semiconductor silicide or a semiconductor silicide doped with transition metal is used to form an active layer (&bgr;-FeSi2 transformed into spheres) (2″) of a semiconductor light-emitting element, and the active layer is sandwiched between p-type and n-type semiconductor layers forming a pn junction, the p-type and n-type semiconductor layers having a forbidden bandwidth greater than that of the semiconductor silicide.Type: GrantFiled: June 9, 2000Date of Patent: April 9, 2002Assignee: Japan Science and Technology CorporationInventor: Takashi Suemasu
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Patent number: 6365427Abstract: The present invention relates to a semiconductor laser device and a method for fabrication thereof, wherein the semiconductor laser device exhibits an improved mode selectivity.Type: GrantFiled: February 9, 2000Date of Patent: April 2, 2002Assignee: Avalon Photonics Ltd.Inventors: Hans Peter Gauggel, Karl Heinz Gulden
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Patent number: 6352872Abstract: A silicon-on-insulator (SOI) device having a double gate, comprising: a supporting substrate; a first insulating layer formed over the supporting substrate; a first silicon layer formed over the first insulating layer, the first silicon layer including a first impurity region of a first conductivity disposed in a central portion thereof and intrinsic regions disposed at the both sides of the first impurity region; a second insulating layer formed over the first silicon layer; a second silicon layer formed over the second insulating layer, the second silicon layer including a second impurity region of a second conductivity disposed in a central portion thereof and third impurity regions of first conductivities disposed at the both sides of the second impurity region; a third insulating layer formed over the second impurity region; and a polysilicon layer doped with impurity ions of first conductivities, formed over the third insulating layer.Type: GrantFiled: November 14, 2000Date of Patent: March 5, 2002Assignee: Hyundai Electronics Industries Co., Ltd.Inventors: Hyung Ki Kim, Jong Wook Lee
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Patent number: 6344670Abstract: The solid-state image sensor comprises a semiconductor substrate, a plurality of photoelectric conversion sections formed within respective isolated active regions on the semiconductor substrate, an image area wherein unit cells comprising the plurality of photoelectric conversion sections and a signal scanning circuit are arranged in a two-dimensional array form, and signal lines for reading signals from the respective unit cells within the image pick-up area, wherein the respective photoelectric conversion sections being formed by at least two ion implantations.Type: GrantFiled: January 8, 2001Date of Patent: February 5, 2002Assignee: Kabushiki Kaisha ToshibaInventors: Tetsuya Yamaguchi, Hisanori Ihara, Hirofumi Yamashita, Hidetoshi Nozaki, Ikuko Inoue
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Publication number: 20010055826Abstract: The present invention provides a method for manufacturing an optical element to be used for an optical system and an optical instrument using the optical system, and a method for manufacturing a device using the optical instrument, wherein the optical element is manufactured by the steps including the steps for processing a high purity silica glass by lithography, and the hydrogen molecule content is adjusted after manufacturing the optical element.Type: ApplicationFiled: June 7, 2001Publication date: December 27, 2001Inventor: Keiko Chiba
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Publication number: 20010049152Abstract: The purpose of the invention is to provide a photoelectric conversion element enable to ensure the connection of the contact electrode easily and accurately.Type: ApplicationFiled: August 9, 2001Publication date: December 6, 2001Inventors: Takehiro Taniguchi, Hironobu Narui, Noriko Ueno, Nobukata Okano
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Publication number: 20010042864Abstract: A gate oxide film 18 and a gate electrode 20 are formed on a surface of a P-type substrate 14. A concave portion 42 is provided in a region of the P-type substrate 14, the region being contiguous to the gate electrode 20. On the P-type substrate 14, an N-type drain region 30 is disposed on the opposite side of the gate electrode 20 from the concave portion 42. N-type impurities are implanted into the P-type substrate 14 at a predetermined angle relative to the latter, thereby forming an N-type region 44 which includes a region underneath the concave portion 42 and which is partially submerged beneath the gate oxide film 18. P-type impurities are then implanted into the P-type substrate 14 at right angles to the latter, thus forming a P-type region 46 which includes a region underneath the concave portion 42 while covering the N-type region 44 and which forms a PN junction diode in combination with the N-type region 44.Type: ApplicationFiled: July 9, 2001Publication date: November 22, 2001Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventor: Hisayuki Kato
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Patent number: 6316278Abstract: Methods and apparatus for fabricating a multiple display modular assembly. In one example of a method, a first flexible layer is coupled to a substrate, a second flexible layer is coupled to the first flexible layer, and a third flexible layer is coupled to the second flexible layer. Each of the flexible layers may be generated from a separate web-line process. In one example, one flexible layer may have a display plane with a driver backplane, a second flexible layer may have a fine interconnect, and a third flexible layer may have gross interconnect. The multiple flexible layer modular assembly may apply to either flexible or rigid displays.Type: GrantFiled: March 16, 1999Date of Patent: November 13, 2001Assignee: Alien Technology CorporationInventors: Jeffrey Jay Jacobsen, Glenn Wilhelm Gengel, Gordon S. W. Craig
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Publication number: 20010038100Abstract: An application-specific rf optoelectronic integrated circuit having a generic chip member and a defining substrate in communication with at least one generic chip member. The generic chip member contains passive building block components that are independent from each other and being connected by paths external to the generic chip member. The external connection paths are defined by a defining substrate member having passive components for providing optical and electrical interconnection between selected building block components on the generic chip member to define the specific function of the integrated circuit. It is possible to use the same design of the generic chip for several applications merely by altering the interconnect paths on a defining substrate.Type: ApplicationFiled: May 25, 2001Publication date: November 8, 2001Applicant: Hughes Electronics CorporationInventor: Daniel Yap