Including Device Responsive To Nonelectrical Signal Patents (Class 438/24)
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Patent number: 6734519Abstract: A waveguide photodiode includes an n-type cladding layer, an n-type light confining layer, an i-type light absorption layer, a p-type light confining layer, and a p-type cladding layer buried in an Fe—InP blocking layer on a semiconductor substrate. At least one of the p-type light confining layer and the p-type cladding layer contains a p-type impurity selected from Be, Mg, and C. An undoped layer is preferably located between the i-type light absorption layer and the p-type light confining layer.Type: GrantFiled: March 17, 2003Date of Patent: May 11, 2004Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Masaharu Nakaji, Eitaro Ishimura
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Patent number: 6730934Abstract: This invention relates an optoelectronic material comprising a uniform medium with a controllable electric characteristic; and semiconductor ultrafine particles dispersed in the medium and having a mean particle size of 100 nm or less, and an application device using the same.Type: GrantFiled: November 30, 2000Date of Patent: May 4, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yuka Yamada, Takehito Yoshida, Shigeru Takeyama, Yuji Matsuda, Katsuhiko Mutoh
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Patent number: 6727109Abstract: The present invention relates to a method of fabricating vertical-cavity surface emitting lasers being watched as a light source for long wavelength communication. The present invention includes forming a layer having a high resistance near the surface by implanting heavy ions such as silicon (Si), so that the minimum current injection diameter is made very smaller unlike implantation of a proton. Further, the present invention includes regrowing crystal so that current can flow the epi surface in parallel to significantly reduce the resistance up to the current injection part formed by silicon (Si) ions. Therefore, the present invention can not only effectively reduce the current injection diameter but also significantly reduce the resistance of a device to reduce generation of a heat. Further, the present invention can further improve dispersion of a heat using InP upon regrowth and thus improve the entire performance of the device.Type: GrantFiled: July 31, 2002Date of Patent: April 27, 2004Assignee: Electronics and Telecommunications Research InstituteInventors: Young Gu Ju, Won Seok Han, O Kyun Kwon, Jae Heon Shin, Byueng Su Yoo, Jung Rae Ro
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Patent number: 6723577Abstract: An integrated circuit with a number of optical fibers that are formed in high aspect ratio holes. The high aspect ratio holes extend through a semiconductor wafer. The optical fibers include a cladding layer and a core formed in the high aspect ratio hole. These optical fibers are used to transmit signals between functional circuits on the semiconductor wafer and functional circuits on the back of the wafer or beneath the wafer.Type: GrantFiled: August 30, 2000Date of Patent: April 20, 2004Assignee: Micron Technology, Inc.Inventors: Joseph E. Geusic, Kie Y. Ahn, Leonard Forbes
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Patent number: 6716654Abstract: The present invention discloses a light-emitting diode with enhanced brightness and a method for fabricating the same. The light-emitting diode comprises: an epitaxial LED structure having at least one lighting-emitting active layer with a plurality of spacers inside the lighting-emitting active layer; at least one conductive contact, formed on the bottom surface where no spacer is formed inside the lighting-emitting active layer; a transparent material layer formed in the spacers; an adhesion layer formed between the transparent material layer and a permanent substrate; a bottom electrode formed on the bottom surface of the permanent substrate; and an opposed electrode formed on the top surface of the epitaxial LED structure.Type: GrantFiled: March 12, 2002Date of Patent: April 6, 2004Assignee: Opto Tech CorporationInventors: Jung-Kuei Hsu, Hsueh-Chih Yu, Chia-Liang Hsu, Hung-Yuan Lu, Yen-Hu Chu, Chui-Chuan Chang, Kwang-Ru Wang, Chang-Da Tsai, San Bao Lin, Yung-Chiang Hwang, Ming-Der Lin
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Patent number: 6716655Abstract: An object of the invention is to produce, at high efficiency, semiconductor elements which are formed of a high-quality crystalline semiconductor having no cracks and a low dislocation density and which have excellent characteristics. Specifically, a mask formed from SiO2 film is provided on the Si(111) plane of an n-type silicon substrate, and a window portion (crystal growth region) in the shape of an equilateral triangle having a side of approximately 300 &mgr;m is formed through the mask. The three sides of the equilateral triangle are composed of three edges; each edge defined by the (111) plane and another crystal plane that is cleavable. Subsequently, a multi-layer structure of semiconductor crystals in an LED is formed through crystal growth of a Group III nitride compound semiconductor. Thus, limiting the area of one crystal growth region to a considerably small area weakens a stress applied to a semiconductor layer, thereby readily producing semiconductor elements having excellent crystallinity.Type: GrantFiled: June 4, 2002Date of Patent: April 6, 2004Assignee: Toyoda Gosei Co., Ltd.Inventors: Seiji Nagai, Masayoshi Koike, Kazuyoshi Tomita
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Patent number: 6716656Abstract: A method of fabricating an organic device is provided. A first layer is deposited over a substrate through a mask by a first process that results in the first layer having a first area of coverage. A second layer is then deposited over the substrate through the mask by a second process that results in the second layer having a second area of coverage that is different from the first area of coverage.Type: GrantFiled: September 4, 2002Date of Patent: April 6, 2004Assignee: The Trustees of Princeton UniversityInventors: Max Shtein, Stephen R. Forrest
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Patent number: 6713314Abstract: A film bulk acoustic resonator wafer and microelectromechanical switch wafer may be combined together in face-to-face abutment with sealing material between the wafers to define individual modules. Electrical interconnects can be made between the switch and the film bulk acoustic resonator within a hermetically sealed chamber defined between the switch and the film bulk acoustic resonator.Type: GrantFiled: August 14, 2002Date of Patent: March 30, 2004Assignee: Intel CorporationInventors: Daniel M. Wong, John Heck, Valluri Rao
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Publication number: 20040056264Abstract: A photodetector includes a light emitting portion for applying light, a light receiving portion for sensing the light, and a light guiding member 3 for guiding the light from the light emitting portion to a surface to be measured and guiding detection light from the surface to be measured to the light receiving portion. The light guiding member has a sheet-like optical transmission medium, which is disposed at a portion facing to the surface to be measured and transmits the light by internal reflection. The sheet-like optical transmission member has an optical aperture facing to the surface to be measured.Type: ApplicationFiled: March 4, 2003Publication date: March 25, 2004Applicant: Fuji Xerox Co., Ltd.Inventor: Tohru Hisano
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Publication number: 20040056268Abstract: A semiconductor device includes: a substrate having in its principal surface first and second recessed portions formed adjacent to each other; and first and second semiconductor laser chips each having a portion that is inserted in one of the recessed portions. The depth of the recessed portions is smaller than the height of the first and second semiconductor laser chips that are disposed in the recessed portions.Type: ApplicationFiled: June 17, 2003Publication date: March 25, 2004Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Kazutoshi Onozawa, Tetsuzo Ueda, Daisuke Ueda
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Patent number: 6709881Abstract: A method for manufacturing a semiconductor includes: a first step of forming an etching stop layer on a first semiconductor layer; and a second step of forming a second semiconductor layer made of a group III-V compound semiconductor on the etching stop layer. An etching rate for the etching stop layer by dry etching is less than an etching rate for the second semiconductor layer.Type: GrantFiled: November 27, 2001Date of Patent: March 23, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yoshiaki Hasegawa, Gaku Sugahara, Ryoko Miyanaga
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Patent number: 6706544Abstract: The light emitting device according to the present invention is characterized in that a gate electrode comprising plurality of conductive films is formed, and concentration of impurity regions in an active layer are adjusted with making use of selectivity of the conductive films in etching and using them as masks. The present invention reduces the number of photolithography steps in relation to manufacturing the TFT for improving yield of the light emitting device and shortening manufacturing term thereof, by which a light emitting device and an electronic appliance are inexpensively provided.Type: GrantFiled: April 19, 2001Date of Patent: March 16, 2004Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Takeshi Fukunaga, Jun Koyama, Kazutaka Inukai
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Patent number: 6706551Abstract: A method for the manufacturing of a Thin Film Inorganic Light Emitting Diode is disclosed. The device contains in one single layer or in a double layer a dispersion of zinc sulfide doped with a luminescent centre, and a water-compatible p-type semiconductive polymer, preferably a polythiophene/polymeric polyanion complex.Type: GrantFiled: January 24, 2002Date of Patent: March 16, 2004Assignee: Agfa-GevaertInventor: Hieronymus Andriessen
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Patent number: 6703657Abstract: A DRAM cell is provided, along with a method for fabricating such a DRAM cell. A protection layer pattern is formed to cover a common drain region of first and second access transistors. Storage node holes are then formed to expose each source region of the first and second access transistors, by using an etching insulator that has an etching selectivity with respect to the protection layer. Accordingly, even if there is a misalignment of the storage node holes to the source regions, the common drain region is not exposed by the misaligned storage node holes because of the presence of the protection layer pattern.Type: GrantFiled: July 8, 2002Date of Patent: March 9, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: Yoo-Sang Hwang, Byung-Jun Park
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Patent number: 6699728Abstract: An OLED device using improved pillars to facilitate patterning of a conductive layer is described. Conventional use of pillars to pattern electrodes encounters shorting problems due to piling of polymer material at the base of the pillars. This piling deteriorates the profile of the pillars which adversely impacts the ability of the pillars to pattern the conductive layer to form the electrodes. The present invention avoids the shorting problem by separating the pillars into at least first and second sub-pillars. By providing a relatively narrow gap between the sub-pillars, the amount of polymers filling the area between the gap is small. This prevents at least the sidewalls of the pillars facing the gap from being deteriorated by polymer pile-up, thus ensuring that the conductive layer is discontinuous between the sub-pillars.Type: GrantFiled: November 20, 2001Date of Patent: March 2, 2004Assignee: Osram Opto Semiconductors GmbHInventors: Ewald Guenther, Lim Hooi Bin, Soh Ed Vin, Tan Hou Siong, Hagen Klausmann
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Publication number: 20040036078Abstract: The invention provides a semiconductor device, a method of manufacturing the same, an electro-optic device and an electronic apparatus which are capable of addressing or solving a problem of mechanical mounting of a semiconductor element chip on a substrate. A semiconductor device includes a tile-shaped microelement bonded to a substrate, and an insulating functional film provided to cover at least a portion of the tile-shaped microelement.Type: ApplicationFiled: June 18, 2003Publication date: February 26, 2004Applicant: SEIKO EPSON CORPORATIONInventor: Takayuki Kondo
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Patent number: 6696312Abstract: A method of fabricating OLED devices is disclosed. A conductive layer is patterned by pillars to form electrodes in the device, wherein portions of the pillars have at least 2 sub-rows to prevent shorting of adjacent electrodes. In one embodiment, the ends of the pillars are split into at least 2 sub-rows.Type: GrantFiled: September 6, 2002Date of Patent: February 24, 2004Assignee: Osram Opto Semiconductors GmbHInventors: Ewald Guenther, Hooi Bin Lim, Ed Vin Soh, Hou Siong Tan, Hagen Klausmann
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Patent number: 6696308Abstract: A method of fabricating an electrically pumped, long-wavelength vertical cavity surface emitting laser includes epitaxially growing a stack of alternate layers of a first material and a second material on a compatible substrate. A long wave-length active region is epitaxially grown on the stack and a lasing aperture and current confinement volume are defined in the long wave-length active region. A first mirror stack is formed on the long wave-length active region and portions of one of the first material and the second material are removed to form a high reflectivity second mirror stack.Type: GrantFiled: October 27, 2000Date of Patent: February 24, 2004Inventors: Chan-Long Shieh, Jeff Tsao
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Patent number: 6689628Abstract: A method of fabricating a dense pixel array comprising the steps of: (a) printing a photoresist mask and applying said mask to a semiconductor material substrate to form a masked area and an unmasked area on said substrate; (b) applying a photoresist material layer to the unmasked area of the substrate, then applying a metal layer over the photoresist material layer and the substrate, and then applying a solvent to remove the photoresist material layer and said metal layer applied over said photoresist material layer to leave a plurality of metal layers superimposed over the unmasked area of the substrate; (c) removing the substrate to a depressed substrate surface between the metal layers formed in step (b) to form a plurality of pixels each having an upper metal layer; (d) superimposing an insulative layer over each of the metal layers formed in step (c); (e) forming a hole in at least one of the insulative layers formed in step (d) so as to expose the metal layer under the insulative layer; and (f) superimType: GrantFiled: August 15, 2002Date of Patent: February 10, 2004Assignee: Bae Systems Information and Electronic Systems Integration Inc.Inventor: Lawrence F. DePaulis
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Patent number: 6689627Abstract: A process for manufacturing components in a multi-layer wafer, including the steps of: providing a multi-layer wafer comprising a first semiconductor material layer, a second semiconductor material layer (, and a dielectric material layer arranged between the first and the second semiconductor material layer; and removing the first semiconductor material layer initially by mechanically thinning the first semiconductor material layer, so as to form a residual conductive layer, and subsequently by chemically removing the residual conductive layer. In one application, the multi-layer wafer is bonded to a first wafer of semiconductor material, with the second semiconductor material layer facing the first wafer, after micro-electromechanical structures have been formed in the second semiconductor material layer of the multi-layer wafer.Type: GrantFiled: December 19, 2001Date of Patent: February 10, 2004Assignee: STMicroelectronics S.r.l.Inventors: Marta Mottura, Alessandra Fischetti, Marco Ferrera, Bernardino Zerbini, Mauro Bombonati
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Patent number: 6689626Abstract: The invention relates to a substrate comprising a glass sheet (1) having a thickness which is smaller than or equal to 0.1 mm, the glass sheet (1) being provided with a layer of a synthetic resin material (2) having a thickness which is smaller than or equal to that of the glass sheet (1). This substrate proves to be flexible. In addition, the substrate cracks less easily, so that it can be processed more readily. The substrate may be used, for example, in light-emitting devices, such as a poly-LED or PALC.Type: GrantFiled: July 10, 2001Date of Patent: February 10, 2004Assignee: Koninklijke Philips Electronics N.V.Inventors: Marcellinus P. C. M. Krijn, Marinus J. J. Dona, Johannes M. M. Swinkels, Jeroen J. M. Vleggaar
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Patent number: 6686216Abstract: An electro-optical transceiver system with controlled lateral light leakage and a method of making such a system includes a plurality of emitter devices and detector devices including at least one of each, arranged in a planar array for transmitting and receiving, respectively, energy in a predetermined wavelength and a blocking medium disposed interstitially of the devices and being absorbing at the predetermined wavelength for blocking energy at the predetermined wavelength laterally leaking from an emitter device to one or more detector devices.Type: GrantFiled: May 13, 2003Date of Patent: February 3, 2004Assignee: Teraconnect, INCInventors: John A. Trezza, Gregory K. Dudoff
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Patent number: 6682949Abstract: A semiconductor laser basically includes a first cladding layer; an active layer; a second cladding layer; and a current constriction means for defining a current injection region in the active layer. The active layer has a gain region which acquires an optical gain by current injection thereto; a saturable absorption region in which current injection thereto little occurs and light effusion thereto occurs; and an outside region, being in contact with the saturable absorption region, in which current injection thereto little occurs and light effusion thereto little occurs. In this semiconductor laser, an effective band gap of the saturable absorption region is set to be larger than that of the outside region. With this configuration, carriers in the saturable absorption region are efficiently migrated to the outside region, so that the carrier lifetime in the saturable absorption region is actually shortened.Type: GrantFiled: July 9, 2002Date of Patent: January 27, 2004Assignee: Sony CorporationInventor: Masakazu Ukita
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Patent number: 6673642Abstract: An electro-optical transceiver system with controlled lateral light leakage and a method of making such a system includes a plurality of emitter devices and detector devices including at least one of each, arranged in a planar array for transmitting and receiving, respectively, energy in a predetermined wavelength and a blocking medium disposed interstitially of the devices and being absorbing at the predetermined wavelength for blocking energy at the predetermined wavelength laterally leaking from an emitter device to one or more detector devices.Type: GrantFiled: May 13, 2003Date of Patent: January 6, 2004Assignee: Teraconnect IncInventors: John A. Trezza, Gregory K. Dudoff
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Patent number: 6667183Abstract: An anti-reflective layer is formed on the sidewalls of metal interconnects in an integrated circuit containing photodetector devices. After fabricating the photodetector devices, the metal interconnects are formed. An anti-reflective layer is formed over the interconnects and is directionally etched so that a portion of the anti-reflective layer remains covering the interconnect sidewalls, thereby reducing optical cross-talk in the photodetector devices due to sidewall reflection.Type: GrantFiled: August 27, 2001Date of Patent: December 23, 2003Assignee: Tower Semicondcutor Ltd.Inventor: Jeffrey M. Levy
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Patent number: 6667184Abstract: Seeds are implanted in a regular pattern upon an undersubstrate. A GaN crystal is grown on the seed implanted undersubstrate by a facet growth method. The facet growth makes facet pits above the seeds. The facets assemble dislocations to the pit bottoms from neighboring regions and make closed defect accumulating regions (H) under the facet bottoms. The closed defect accumulating regions (H) arrest dislocations permanently. Release of dislocations, radial planar defect assemblies and linear defect assemblies are forbidden. The surrounding accompanying low dislocation single crystal regions (Z) and extra low dislocation single crystal regions (Y) are low dislocation density single crystals.Type: GrantFiled: September 19, 2002Date of Patent: December 23, 2003Assignee: Sumitomo Electric Industries, Ltd.Inventors: Kensaku Motoki, Takuji Okahisa, Seiji Nakahata, Ryu Hirota, Koji Uematsu
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Publication number: 20030227021Abstract: A light emission device manufactured by a method of forming a curved surface having a radius of curvature to the upper end of an insulator 19, exposing a portion of the first electrode 18c to form an inclined surface in accordance with the curved surface, and applying etching so as to expose the first electrode 18b in a region to form a light emission region, in which emitted light from the layer containing the organic compound 20 is reflected on the inclined surface of the first electrode 18c to increase the total take-out amount of light in the direction of an arrow shown in FIG.Type: ApplicationFiled: June 4, 2003Publication date: December 11, 2003Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Takeshi Noda, Yoshinari Higaki
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Patent number: 6656757Abstract: An electro-optical transceiver system with controlled lateral light leakage and a method of making such a system includes a plurality of emitter devices and detector devices including at least one of each, arranged in a planar array for transmitting and receiving, respectively, energy in a predetermined wavelength and a blocking medium disposed interstitially of the devices and being absorbing at the predetermined wavelength for blocking energy at the predetermined wavelength laterally leaking from an emitter device to one or more detector devices.Type: GrantFiled: September 12, 2002Date of Patent: December 2, 2003Assignee: Teraconnect, Inc.Inventors: John A. Trezza, Gregory K. Dudoff
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Patent number: 6653158Abstract: A vertical cavity surface emitting laser (VCSEL) includes a semiconductor device having a pair of mirror portions, an active region, a tunnel junction, a pair of cladding layers and a substrate. Heat generated by the VCSEL dissipates through the cladding layers, which utilize an indium phosphide material. The VCSEL also includes selective etches that are used to aperture the active region to allow electric current to be injected into the active region.Type: GrantFiled: August 21, 2001Date of Patent: November 25, 2003Assignee: The Regents of the University of CaliforniaInventors: Eric M. Hall, Shigeru M. Nakagawa, Larry A. Coldren
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Publication number: 20030213963Abstract: Conductors to interconnect electronic devices, the conductors being formed on a detachable substrate. The substrate is aligned with a package containing electronic devices. The conductors are bonded to pads on the devices. Then, the substrate is detached. Each conductor is self supporting between the devices, has a two dimensional shape and has a surface that is substantially parallel to a surface of the pads.Type: ApplicationFiled: May 17, 2002Publication date: November 20, 2003Inventors: Brian E. Lemoff, Lisa A. Buckman
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Patent number: 6649433Abstract: A heterogeneous blend of small electron-donor organic molecules and polymerizable monomers is flash evaporated to provide a molecular-level vapor-phase mixture, which is then condensed and cured in-line as a homogeneous liquid layer on a flexible web containing an anodic layer. The procedure is repeated with an electron-acceptor organic substance, which is deposited over the electron-donor layer. A metallic cathode is then deposited over the electron-acceptor layer and the composite OLED product is packaged. The electrical characteristics and the thickness of the metallic cathode and the composition of the polymer layers are selected such as to produce the gasification of elemental carbon generated by dielectric breakdowns and the oxidation of any exposed cathodic surface, thereby providing a built-in mechanism to prevent the propagation of the damage caused by electrical shorts.Type: GrantFiled: June 26, 2001Date of Patent: November 18, 2003Assignee: Sigma Technologies International, Inc.Inventors: Michael G. Mikhael, Angelo Yializis
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Patent number: 6642068Abstract: A method for forming a micro-optical switch component includes providing a semiconductor substrate having a surface. An opto-electronic device is integrated into the semiconductor substrate at a site. A pedestal of microlens material is formed on the semiconductor substrate surface at the site of the opto-electronic device. The pedestal extends from the semiconductor substrate surface and has a top surface spaced apart from the semiconductor substrate surface. A print head is provided and contains an optical fluid which is hardenable and capable of serving as a micro-optical element. The printhead includes an orifice from which micro-droplets of the optical fluid are ejected in response to control signals. Optical fluid is deposited onto the top surface of the pedestal to thereby form a micro-optical element on the pedestal.Type: GrantFiled: May 3, 2002Date of Patent: November 4, 2003Inventors: Donald J. Hayes, Ting Chen, W. Royall Cox
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Patent number: 6639249Abstract: A multi-color, solid-state lighting device includes a stack of two or more panels, each panel having an array of light emitting semiconductor components formed thereon. To form the light emitting components, high quality epitaxial layers of monocrystalline materials can be grown overlying a monocrystalline layer of silicon formed on a low cost substrate, such as glass. The growth of the monocrystalline materials is accomplished by forming a compliant substrate for growing the monocrystalline materials. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer.Type: GrantFiled: August 6, 2001Date of Patent: October 28, 2003Assignee: Motorola, Inc.Inventor: George Valliath
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Patent number: 6633421Abstract: A unit has an array of lasers having an emission surface through which beams can be emitted in a substantially vertical direction so as to define an emission side, drive electronics connected to a side opposite to the emission side of the array of lasers, and an array of modulators, located on the emission side of the array of lasers and connected to the drive electronics.Type: GrantFiled: June 26, 2002Date of Patent: October 14, 2003Assignee: Xanoptrix, Inc.Inventor: John Trezza
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Patent number: 6627468Abstract: The present invention provides a method for manufacturing an optical element to be used for an optical system and an optical instrument using the optical system, and a method for manufacturing a device using the optical instrument, wherein the optical element is manufactured by the steps including the steps for processing a high purity silica glass by lithography, and the hydrogen molecule content is adjusted after manufacturing the optical element.Type: GrantFiled: June 7, 2001Date of Patent: September 30, 2003Assignee: Canon Kabushiki KaishaInventor: Keiko Chiba
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Patent number: 6627482Abstract: Surface mount diodes are mass produced by first cutting a metal plate to form a plurality of vertical slits within metal plate. Parallel lines are cut midway between the slits to form wings for the slits. The wings are folded to form the bottoms for surface mounting. Glue is applied over the metal plate to form focusing cups.Type: GrantFiled: February 9, 2001Date of Patent: September 30, 2003Assignee: Harvatek CorporationInventors: Bily Wang, Bill Chang
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Patent number: 6627520Abstract: A nitride semiconductor substrate including (a) a supporting substrate, (b) a first nitride semiconductor layer having a periodical T-shaped cross-section, having grown from periodically arranged stripe-like, grid-like or island-like portions on the supporting substrate, and (c) a second nitride semiconductor substrate covering said supporting substrate, having grown from the top and side surfaces of said first nitride semiconductor layer, wherein a cavity is formed under the second nitride semiconductor layer. A protective layer having a periodically arranged stripe-like, grid-like or island-like apertures is formed on the supporting substrate. The first nitride semiconductor layer is laterally grown from the exposed portion of the substrate. The growth is stopped before the first nitride semiconductor layer covers the supporting substrate. Thus, the first nitride semiconductor layer has a periodical T-shaped cross-section.Type: GrantFiled: October 1, 2002Date of Patent: September 30, 2003Assignee: Nichia CorporationInventors: Tokuya Kozaki, Hiroyuki Kiyoku, Kazuyuki Chocho, Hitoshi Maegawa
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Publication number: 20030173564Abstract: An active matrix organic electroluminescent device includes a substrate, a gate line on the substrate, a data line on the substrate, the data line crossing the gate line to define a pixel region, a first switching thin film transistor connected to the gate line and the data line, a first driving thin film transistor connected to the first switching thin film transistor, a power line connected to the first driving thin film transistor and parallel to the gate line, a capacitor electrode connected to the first driving thin film transistor and overlapping the power line, and a pixel electrode connected to the first driving thin-film transistor and covering the pixel region.Type: ApplicationFiled: December 31, 2002Publication date: September 18, 2003Applicant: LG.Philips LCD Co., LtdInventors: Doo-Hyun Ko, Chang-Wook Han
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Patent number: 6620641Abstract: A GaN compound semiconductor laser includes an AlGaN buried layer which buries opposite sides of a ridge stripe portion formed on a p-type AlGaN cladding layer. The AlGaN buried layer is made by first patterning an upper part of the p-type AlGaN cladding layer and a p-type GaN contact layer into a ridge stripe configuration by using a SiO2 film as an etching mask, then growing the AlGaN buried layer non-selectively on the entire substrate surface to bury both sides of the ridge stripe portion under the existence of the SiO2 film on the ridge stripe portion, and thereafter selectively removing the AlGaN buried layer from above the ridge stripe portion by etching using the SiO2 film as an etching stop layer. Thus, the GaN compound semiconductor laser is stabilized in the transverse mode, intensified in output power, and improved in lifetime.Type: GrantFiled: June 17, 2002Date of Patent: September 16, 2003Assignee: Sony CorporationInventors: Takashi Yamaguchi, Toshimasa Kobayashi, Satoru Kijima, Takashi Kobayashi, Tsunenori Asatsuma, Takeharu Asano, Tomonori Hino
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Patent number: 6621104Abstract: A measuring system that includes a scale and a transparent substrate located opposite the scale. The transparent includes a graduation structure and a semiconductor layer arranged on a first side of the transparent substrate facing away from the scale, wherein a photodetector, a light source and an electronic circuit are integrated into the semiconductor layer.Type: GrantFiled: February 15, 2002Date of Patent: September 16, 2003Assignee: Dr. Johannes Heidenhain GmbHInventors: Peter Speckbacher, Dieter Michel
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Patent number: 6617185Abstract: In one embodiment, the present invention is directed to a method of fabricating a micro-mechanical latching device, comprising: depositing a structural layer in a fabrication plane, wherein the first structural layer possesses a topography; depositing a sacrificial layer adjacent to the first layer such that the sacrificial layer conforms to the topography of the first layer; depositing a second structural layer that conforms to the topography of the first layer; removing the sacrificial layer; and using at least the first structural layer and second structural layer to fabricate the micro-mechanical latching device.Type: GrantFiled: February 7, 2002Date of Patent: September 9, 2003Assignee: Zyvex CorporationInventor: Aaron Geisberger
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Patent number: 6613596Abstract: In the monolithically integrated photonic circuit, light travels through multiple quantum well channel waveguides and is coupled into and out of the devices that reside in common on a single semiconductor substrate. Each device, which is co-planar with any other device on the substrate, is comprised of a quantum well channel waveguide of a pre-determined length and an electrical contact pad mounted on the waveguide that facilitates the application of electric field to the device. The function of any particular device as an optical source, an optical modulator or a photo-detector is determined by the bias mode of electric field applied to that particular device. The circuit is comprised of multiple rows of such devices. Each of these rows contains at least three devices which function as an optical source, an optical modulator and a photo-detector, respectively, and are separated from each other by electrical isolation gaps.Type: GrantFiled: May 20, 2002Date of Patent: September 2, 2003Assignee: The United States of America as represented by the Secretary of the ArmyInventors: Mark J. Bloemer, Krishna Myneni
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Patent number: 6599133Abstract: A method for fabricating p-type, i-type, and n-type III-V compound materials using HVPE techniques is provided. If desired, these materials can be grown directly onto the surface of a substrate without the inclusion of a low temperature buffer layer. By growing multiple layers of differing conductivity, a variety of different device structures can be fabricated including simple p-n homojunction and heterojunction structures as well as more complex structures in which the p-n junction, either homojunction or heterojunction, is interposed between a pair of wide band gap material layers. The provided method can also be used to fabricate a device in which a non-continuous quantum dot layer is grown within the p-n junction. The quantum dot layer is comprised of a plurality of quantum dot regions, each of which is typically between approximately 20 and 30 Angstroms per axis.Type: GrantFiled: May 18, 2001Date of Patent: July 29, 2003Assignee: Technologies and Devices International, Inc.Inventors: Audrey E. Nikolaev, Yuri V. Melnik, Konstantin V. Vassilevski, Vladimir A. Dmitriev
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Patent number: 6597017Abstract: Provided is a semiconductor device that has pseudo lattice matched layers with good crystallinity, formed with lattice mismatched materials. Tensile-strained n-type Al0.5Ga0.5N layers (lower side) and compressive-strained n-type Ga0.9In0.1N layers (upper side) are grown on a GaN crystal layer substrate in 16.5 periods to form an n-type DBR mirror; an undoped GaN spacer layer and an active region are grown on the n-type DBR mirror; and an undoped a GaN spacer layer is grown on the active region. Further, tensile-strained p-type Al0.5Ga0.5N layers (lower side) and compressive-strained p-type Ga0.9In0.1N layers (upper side) are grown on the spacer layer in 12 periods to form a p-type DBR mirror and eventually complete a surface emitting semiconductor laser.Type: GrantFiled: March 7, 2000Date of Patent: July 22, 2003Assignee: Fuji Xerox Co., Ltd.Inventors: Yasuji Seko, Akira Sakamoto
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Patent number: 6586269Abstract: A photoconductive relay that comprises a light-emitting device, a photoconductive switching element and columns of a conductive, fusible material. The light-emitting device and the photoconductive switching element respectively include including a light-emitting region and a light-receiving region. The columns extend between the light-emitting device and the photoconductive switching element to locate the light-emitting region of the light-emitting device opposite the light-receiving region of the photoconductive switching element and separated from one another by a distance of no more than 100 &mgr;m.Type: GrantFiled: April 11, 2002Date of Patent: July 1, 2003Assignee: Agilent Technologies, Inc.Inventors: You Kondoh, Yasuhisa Kaneko, Tsutomu Takenaka
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Patent number: 6583443Abstract: A light emitting epi-layer structure which contains a temporality light absorption substrate on one side, the other side thereof can be adhered to a light absorption free transparent substrate in terms of a transparent adhesive layer which is light absorption free too. After that, the light absorption substrate portion is removed by means of an etching process. The resulted light emitting diode has significant improvement in light emitting efficiency. Moreover, the transparent conductive layer is a low resistance and high transparency layer. The current flow can thus be distributed evenly than conventional one.Type: GrantFiled: July 17, 2002Date of Patent: June 24, 2003Assignee: United Epitaxy Co., Ltd.Inventors: Chih-Sung Chang, Kuang-Neng Yang, Tzer-Perng Chen
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Method of making electronics package with specific areas having low coefficient of thermal expansion
Patent number: 6579747Abstract: Method of making semiconductor package including at least one semiconductor chip disposed within a housing, the housing including a lid which overlies the at least one semiconductor chip and a heat-dissipating device coupled to the housing, the heat-dissipating device including at least one area formed of a material with a low coefficient of thermal expansion.Type: GrantFiled: August 15, 2002Date of Patent: June 17, 2003Inventor: Jon Zuo -
Patent number: 6577006Abstract: An undoped GaN buffer layer, an n-type GaN layer and a p-type GaN layer are successively formed on a sapphire substrate, and a partial region from the p-type GaN layer to the n-type GaN layer is removed, to expose the n-type GaN layer. Ti films having a thickness of 3 to 100 Å and Pt films are successively formed on the p-type GaN layer and on the exposed upper surfaces of the n-type GaN layer. Consequently, a p electrode in ohmic contact with the p-type GaN layer and an n electrode in ohmic contact with the n-type GaN layer are formed without being alloyed by heat treatment.Type: GrantFiled: December 28, 1999Date of Patent: June 10, 2003Assignee: Sanyo Electric Co., Ltd.Inventors: Kiyoshi Oota, Nobuhiko Hayashi
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Patent number: 6570186Abstract: A wafer comprising a semiconductor layer formed on a substrate is diced on the back surface of the substrate to a depth of about ¾ thickness of the substrate. Thus a separation groove 21 is formed in a direction of a dicing line. A groove 22 is formed at the portion of the semiconductor layer corresponding to the groove 21. The groove 22 reaches the substrate. The back surface 11b of the substrate 11 is polished until the substrate become a lamella having only a trace of the groove 22. A metal layer 10 is formed by depositing aluminum (Al) so as to cover the entire back 11b of the substrate 11, and a groove 23 formed at the portion of the metal layer corresponding to the groove 21. An adhesive sheet 24 is adhered on an electrode pad 20. A scribe line is formed by scribing the metal layer 10 along the groove 23. The wafer is loaded by a roller in a breaking process. Accordingly, a wafer having the metal layer on the back surface 11b of the substrate can be obtained.Type: GrantFiled: May 10, 2000Date of Patent: May 27, 2003Assignee: Toyoda Gosei Co., Ltd.Inventors: Toshiya Uemura, Takahide Oshio
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Patent number: 6566743Abstract: A semiconductor package including at least one semiconductor chip disposed within a housing, the housing including a lid which overlies the at least one semiconductor chip and a heat-dissipating device coupled to the housing, the heat-dissipating device including at least one area formed of a material with a low coefficient of thermal expansion.Type: GrantFiled: February 21, 2002Date of Patent: May 20, 2003Assignee: Thermal Corp.Inventor: Jon Zuo