Including Selectively Removing Material To Undercut And Expose Storage Node Layer Patents (Class 438/254)
  • Patent number: 10461148
    Abstract: Metal-on-metal insulator structures and methods for making the same. The method includes: providing an insulator layer overlying a semiconductor substrate, forming a plurality of alternating first conductive layers and second conductive layers on the insulator layer, forming at least one dielectric layer between each of the alternating first conductive layers and second conductive layers, forming a first trench at a first location through a first portion of the plurality of the alternating first conductive layers and second conductive layers and the at least one dielectric layer, and first etching the first trench selective to the plurality of alternating first conductive layers and second conductive layers, wherein the first conductive layers are etched faster than the second conductive layers to form a first modified trench, wherein the first conductive layers are recessed relative to the center of the first modified trench greater than the second conductive layers.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: October 29, 2019
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Joshua M Rubin, Oscar Van Der Straten, Praneet Adusumilli
  • Patent number: 10224207
    Abstract: A method of making a semiconductor device includes forming a recessed fin in a substrate, the recessed fin being substantially flush with a surface of the substrate; performing an epitaxial growth process over the recessed fin to form a source/drain over the recessed fin; and disposing a conductive metal around the source/drain.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: March 5, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Ruilong Xie, Tenko Yamashita
  • Patent number: 10170319
    Abstract: A method of making a semiconductor device includes forming a recessed fin in a substrate, the recessed fin being substantially flush with a surface of the substrate; performing an epitaxial growth process over the recessed fin to form a source/drain over the recessed fin; and disposing a conductive metal around the source/drain.
    Type: Grant
    Filed: August 3, 2016
    Date of Patent: January 1, 2019
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Kangguo Cheng, Ruilong Xie, Tenko Yamashita
  • Patent number: 9837317
    Abstract: A method for producing a semiconductor device includes forming a first fin-shaped semiconductor layer and a second fin-shaped semiconductor layer on a substrate using a sidewall formed around a dummy pattern on the substrate. A first insulating film is formed around the first fin-shaped semiconductor layer and the second fin-shaped semiconductor layer. A first pillar-shaped semiconductor layer is formed in an upper portion of the first fin-shaped semiconductor layer, and a second pillar-shaped semiconductor layer is formed in an upper portion of the second fin-shaped semiconductor layer.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: December 5, 2017
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 9837277
    Abstract: A method of making a semiconductor device includes forming a recessed fin in a substrate, the recessed fin being substantially flush with a surface of the substrate; performing an epitaxial growth process over the recessed fin to form a source/drain over the recessed fin; and disposing a conductive metal around the source/drain.
    Type: Grant
    Filed: August 12, 2015
    Date of Patent: December 5, 2017
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Kangguo Cheng, Ruilong Xie, Tenko Yamashita
  • Patent number: 9431551
    Abstract: A circuit arrangement may be provided. The circuit arrangement may include a semiconductor substrate including a first surface, a second surface opposite the first surface, and a first doped region of a first conductivity type extending from the first surface into the semiconductor substrate. The circuit arrangement may include at least one capacitor including a first electrode including a doped region of the first conductivity type extending from the second surface into the semiconductor substrate, a dielectric layer formed over the first electrode extending from the second surface away from the semiconductor substrate, and a second electrode formed over the dielectric layer opposite the first electrode. The circuit arrangement may further include at least one semiconductor device monolithically integrated in the semiconductor substrate.
    Type: Grant
    Filed: September 15, 2014
    Date of Patent: August 30, 2016
    Assignee: INFINEON TECHNOLOGIES AG
    Inventor: Detlef Wilhelm
  • Patent number: 9349841
    Abstract: A finFET and methods for forming a finFET are disclosed. A structure comprises a substrate, a fin, a gate dielectric, and a gate electrode. The substrate comprises the fin. The fin has a major surface portion of a sidewall, and the major surface portion comprises at least one lattice shift. The at least one lattice shift comprises an inward or outward shift relative to a center of the fin. The gate dielectric is on the major surface portion of the sidewall. The gate electrode is on the gate dielectric.
    Type: Grant
    Filed: February 19, 2015
    Date of Patent: May 24, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lien Huang, Chun-Hsiang Fan, Tsu-Hsiu Perng, Chi-Kang Liu, Yung-Ta Li, Ming-Huan Tsai, Clement Hsingjen Wann, Chi-Wen Liu
  • Patent number: 9318337
    Abstract: An integrated circuit capacitor. The capacitor includes a substrate, a first conductor, and a first insulating region between the first conductor and the substrate. The capacitor also includes a second conductor, a second insulating region between the first conductor and the second conductor, a third conductor, and a third insulating region between the first conductor and the third conductor. The capacitor also includes a fourth conductor and a fourth insulating region between the first conductor and the fourth conductor.
    Type: Grant
    Filed: September 17, 2014
    Date of Patent: April 19, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Xiangzheng Bo, Douglas T. Grider
  • Patent number: 9196673
    Abstract: A method of forming capacitors includes providing first capacitor electrodes within support material. The first capacitor electrodes contain TiN and the support material contains polysilicon. The polysilicon-containing support material is dry isotropically etched selectively relative to the TiN-containing first capacitor electrodes using a sulfur and fluorine-containing etching chemistry. A capacitor dielectric is formed over sidewalls of the first capacitor electrodes and a second capacitor electrode is formed over the capacitor dielectric. Additional methods are disclosed.
    Type: Grant
    Filed: January 6, 2014
    Date of Patent: November 24, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Gurpreet Lugani, Kevin J. Torek
  • Patent number: 9048212
    Abstract: Semiconductor devices, methods of manufacture thereof, and methods of manufacturing capacitors are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a capacitor over a workpiece. The capacitor includes a bottom electrode, a capacitor dielectric disposed over the bottom electrode, and a top electrode disposed over the capacitor dielectric. A portion of the bottom electrode and a portion of the top electrode are removed proximate edges of the capacitor dielectric.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: June 2, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Kuo-Chi Tu
  • Patent number: 9029930
    Abstract: A FinFET device includes a substrate, a fin, and isolation regions on either side of the fin. The device also includes sidewall spacers above the isolation regions and formed along the fin structure. A recessing trench is formed by the sidewall spacers and the fin, and an epitaxially-grown semiconductor material is formed in and above the recessing trench, forming an epitaxial structure.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: May 12, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Andrew Joseph Kelly, Po-Ruwe Tzng, Pei-Shan Chien, Wei-Hsiung Tseng
  • Patent number: 9012309
    Abstract: Collections of laterally crystallized semiconductor islands for use in thin film transistors and systems and methods for making same are described. A display device includes a plurality of thin film transistors (TFTs) on a substrate, such that the TFTs are spaced apart from each other and each include a channel region that has a crystalline microstructure and a direction along which a channel current flows. The channel region of each of the TFTs contains a crystallographic grain that spans the length of that channel region along its channel direction. Each crystallographic grain in the channel region of each of the TFTs is physically disconnected from and crystallographically uncorrelated with each crystallographic grain in the channel region of each adjacent TFT.
    Type: Grant
    Filed: October 16, 2013
    Date of Patent: April 21, 2015
    Assignee: The Trustees of Columbia University in the City of New York
    Inventors: James S. Im, Ui-Jin Chung
  • Patent number: 8957469
    Abstract: A semiconductor storage device according to an embodiment comprises a memory cell string in which a plurality of memory cells each having a gate are serially connected to each other. A selective transistor is connected to an end memory cell at an end of the memory cell string. A sidewall film covers a side surface of a gate of the end memory cell and a side surface of a gate of the selective transistor between the end memory cell and the selective transistor. An air gap is provided between the sidewall film of the end memory cell and the sidewall film of the selective transistor.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: February 17, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ryosuke Isomura, Wataru Sakamoto, Hiroyuki Nitta
  • Patent number: 8912629
    Abstract: A semiconductor device includes a substrate and a plurality of storage nodes on the substrate and extending in a vertical direction relative to the substrate. A lower support pattern is in contact with the storage nodes between a bottom and a top of the storage nodes, the lower support pattern spaced apart from the substrate in the vertical direction, and the lower support pattern having a first maximum thickness in the vertical direction. An upper support pattern is in contact with the storage nodes above the lower support pattern relative to the substrate, the upper support pattern spaced apart from the lower support pattern in the vertical direction, and the lower support pattern having a second maximum thickness in the vertical direction that is greater than the first maximum thickness of the lower support pattern.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: December 16, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: JungWoo Seo
  • Patent number: 8907392
    Abstract: A semiconductor memory device which includes a memory cell including two or more sub memory cells is provided. The sub memory cells each including a word line, a bit line, a first capacitor, a second capacitor, and a transistor. In the semiconductor device, the sub memory cells are stacked in the memory cell; a first gate and a second gate are formed with a semiconductor film provided therebetween in the transistor; the first gate and the second gate are connected to the word line; one of a source and a drain of the transistor is connected to the bit line; the other of the source and the drain of the transistor is connected to the first capacitor and the second capacitor; and the first gate and the second gate of the transistor in each sub memory cell overlap with each other and are connected to each other.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: December 9, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama
  • Patent number: 8877583
    Abstract: In a method of forming an ohmic layer of a DRAM device, the metal silicide layer between the storage node contact plug and the lower electrode of a capacitor is formed as the ohmic layer by a first heat treatment under a first temperature and an instantaneous second heat treatment under a second temperature higher than the first temperature. Thus, the metal silicide layer has a thermo-stable crystal structure and little or no agglomeration occurs on the metal silicide layer in the high temperature process. Accordingly, the sheet resistance of the ohmic layer may not increase in spite of the subsequent high temperature process.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: November 4, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Bum Kim, Young-Pil Kim, Kwan-Heum Lee, Sun-Ghil Lee
  • Patent number: 8871588
    Abstract: A method of fabricating a memory cell comprises forming a plurality of doped semiconductor layers on a carrier substrate. The method further comprises forming a plurality of digit lines separated by an insulating material. The digit lines are arrayed over the doped semiconductor layers. The method further comprises etching a plurality of trenches into the doped semiconductor layers. The method further comprises depositing an insulating material into the plurality of trenches to form a plurality of electrically isolated transistor pillars. The method further comprises bonding at least a portion of the structure formed on the carrier substrate to a host substrate. The method further comprises separating the carrier substrate from the host substrate.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: October 28, 2014
    Assignee: Micron Technology, Inc.
    Inventors: David H. Wells, H. Montgomery Manning
  • Patent number: 8865545
    Abstract: A semiconductor device comprises: a semiconductor substrate including an active region defined as a device isolation film; a bit line hole disposed over the top portion of the semiconductor substrate; an oxide film disposed at sidewalls of the bit line hole; and a bit line conductive layer buried in the bit line hole including the oxide film. A bit line spacer is formed with an oxide film, thereby reducing a parasitic capacitance. A storage node contact is formed to have a line type, thereby securing a patterning margin. A storage node contact plug is formed with polysilicon having a different concentration, thereby reducing leakage current.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: October 21, 2014
    Assignee: SK Hynix Inc.
    Inventor: Se In Kwon
  • Patent number: 8853816
    Abstract: An isolated semiconductor circuit comprising: a first sub-circuit and a second sub-circuit; a backend that includes an electrically isolating connector between the first and second sub-circuits; a lateral isolating trench between the semiconductor portions of the first and second sub-circuits, wherein the lateral isolating trench extends along the width of the semiconductor portions of the first and second sub-circuits, wherein one end of the isolating trench is adjacent the backend, and wherein the isolating trench is filled with an electrically isolating material.
    Type: Grant
    Filed: December 5, 2012
    Date of Patent: October 7, 2014
    Assignee: NXP B.V.
    Inventors: Peter Gerard Steeneken, Roel Daamen, Gerard Koops, Jan Sonsky, Evelyne Gridelet, Coenraad Cornelis Tak
  • Patent number: 8809929
    Abstract: Memory devices comprise a lower layer that extends across a cell array region and across a peripheral region and that includes a flat outer surface from the cell array region to the peripheral region. A signal transfer conductor layer extends in the cell array region beneath the flat outer surface of the lower layer and extends in the peripheral region above the flat outer surface of the lower layer. An insulating layer is provided on the lower layer, including a flat outer surface from the cell array region to the peripheral region. A flat stopper layer is provided on the flat outer surface of the insulating layer and extending across the cell array region and the peripheral region. Related methods are also provided.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: August 19, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Wonmo Park, Hyunchul Kim, Hyodong Ban, Hyunju Lee
  • Patent number: 8790975
    Abstract: When forming capacitive structures in a metallization system, such as in a dynamic RAM area, placeholder metal regions may be formed together with “regular” metal features, thereby achieving a very efficient overall process flow. At a certain manufacturing stage, the metal of the placeholder metal region may be removed on the basis of a wet chemical etch recipe followed by the deposition of the electrode materials and the dielectric materials for the capacitive structure without unduly affecting other portions of the metallization system. In this manner, very high capacitance values may be realized on the basis of a very efficient overall manufacturing flow.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: July 29, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Peter Baars, Till Schloesser, Vivien Schroeder
  • Patent number: 8785282
    Abstract: A method of making a transistor includes etching a first side of a gate, the gate including an oxide layer formed over a substrate and a conductive material formed over the oxide layer, the etching removing a first portion of the conductive material, implanting an impurity region into the substrate such that the impurity region is self-aligned, and etching a second side of the gate to remove a second portion of the conductive material.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: July 22, 2014
    Assignee: Volterra Semiconductor Corporation
    Inventor: Marco A. Zuniga
  • Patent number: 8703556
    Abstract: A FinFET device is fabricated by first receiving a FinFET precursor. The FinFET precursor includes a substrate and fin structures on the substrate. A sidewall spacer is formed along sidewall of fin structures in the precursor. A portion of fin structure is recessed to form a recessing trench with the sidewall spacer as its upper portion. A semiconductor is epitaxially grown in the recessing trench and continually grown above the recessing trench to form an epitaxial structure.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: April 22, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Andrew Joseph Kelly, Po-Ruwe Tzng, Pei-Shan Chien, Wei-Hsiung Tseng
  • Patent number: 8614471
    Abstract: Collections of laterally crystallized semiconductor islands for use in thin film transistors and systems and methods for making same are described. A display device includes a plurality of thin film transistors (TFTs) on a substrate, such that the TFTs are spaced apart from each other and each include a channel region that has a crystalline microstructure and a direction along which a channel current flows. The channel region of each of the TFTs contains a crystallographic grain that spans the length of that channel region along its channel direction. Each crystallographic grain in the channel region of each of the TFTs is physically disconnected from and crystallographically uncorrelated with each crystallographic grain in the channel region of each adjacent TFT.
    Type: Grant
    Filed: September 22, 2008
    Date of Patent: December 24, 2013
    Assignee: The Trustees of Columbia University in the City of New York
    Inventors: James S. Im, Ui-Jin Chung
  • Patent number: 8569817
    Abstract: A semiconductor device comprises: a semiconductor substrate including an active region defined as a device isolation film; a bit line hole disposed over the top portion of the semiconductor substrate; an oxide film disposed at sidewalls of the bit line hole; and a bit line conductive layer buried in the bit line hole including the oxide film. A bit line spacer is formed with an oxide film, thereby reducing a parasitic capacitance. A storage node contact is formed to have a line type, thereby securing a patterning margin. A storage node contact plug is formed with polysilicon having a different concentration, thereby reducing leakage current.
    Type: Grant
    Filed: July 19, 2010
    Date of Patent: October 29, 2013
    Assignee: Hynix Semiconductor Inc
    Inventor: Se In Kwon
  • Patent number: 8530324
    Abstract: Memory devices comprise a microelectronic substrate including a cell array region and a peripheral region adjacent the cell array region, the cell array region including therein an array of memory cells and the peripheral region including therein peripheral circuits for the array of memory cells, the microelectronic substrate including a lower layer that extends across the cell array region and across the peripheral region and that includes a flat outer surface from the cell array region to the peripheral region. A signal transfer conductor layer extends in the cell array region beneath the flat outer surface of the lower layer and extends in the peripheral region above the flat outer surface of the lower layer. An insulating layer is provided on the lower layer, the insulating layer extending across the cell array region and the peripheral region and also including a flat outer surface from the cell array region to the peripheral region.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: September 10, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Wonmo Park, Hyunchul Kim, Hyodong Ban, Hyunju Lee
  • Patent number: 8518773
    Abstract: A method of fabricating a semiconductor capacitor includes forming a cavity in a first dielectric layer. Then, a nitride stack comprising a slow-etch nitride layer disposed between two fast-etch nitride layers is deposited in the cavity. Next, a portion of the nitride stack is etched within the cavity. Continuing, a metal plug is deposited in the cavity. The fast-etch nitride layers of the nitride stack are removed while preserving the slow-etch nitride layer of the nitride stack. A first metal layer is deposited over the slow-etch nitride layer, a second dielectric layer is deposited over the first metal layer, and a second metal layer is deposited over the second dielectric layer.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: August 27, 2013
    Assignee: International Business Machines Corporation
    Inventors: David Vaclav Horak, Shom Ponoth, Hosadurga Shobha, Chih-Chao Yang
  • Patent number: 8460996
    Abstract: An integrated circuit with devices having dielectric layers with different thicknesses. The dielectric layers include a high-k dielectric and some of the dielectric layers include an oxide layer that is formed from an oxidation process. Each device includes a layer including germanium or carbon located underneath the electrode stack of the device. A silicon cap layers is located over the layer including germanium or carbon.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: June 11, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Gauri V. Karve, Mark D. Hall, Srikanth B. Samavedam
  • Patent number: 8440525
    Abstract: Methods for etching metal nitrides and metal oxides include using ultradilute HF solutions and buffered, low-pH HF solutions containing a minimal amount of the hydrofluoric acid species H2F2. The etchant can be used to selectively remove metal nitride layers relative to doped or undoped oxides, tungsten, polysilicon, and titanium nitride. A method is provided for producing an isolated capacitor, which can be used in a dynamic random access memory cell array, on a substrate using sacrificial layers selectively removed to expose outer surfaces of the bottom electrode.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: May 14, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Kevin R. Shea
  • Patent number: 8343803
    Abstract: A through-silicon via stack package contains package units. Each package unit includes a semiconductor chip; a through-silicon via formed in the semiconductor chip; a first metal line formed on an upper surface and contacting a portion of a top surface of the through-silicon via; and a second metal line formed on a lower surface of the semiconductor chip and contacting a second portion of a lower surface of the through-silicon via. When package units are stacked, the second metal line formed on the lower surface of the top package unit and the first metal line formed on the upper surface of the bottom package unit are brought into contact with the upper surface of the through-silicon via of the bottom package unit and the lower surface of the through-silicon via of the top package unit, respectively. The stack package is lightweight and compact, and can form excellent electrical connections.
    Type: Grant
    Filed: October 27, 2010
    Date of Patent: January 1, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Qwan Ho Chung
  • Patent number: 8324069
    Abstract: A method of fabricating a high-performance capacitor that may be incorporated into a standard CMOS fabrication process suitable for submicron devices is described. The parameters used in the standard CMOS process may be maintained, particularly for the definition and etch of the lower electrode layer. To reduce variation in critical dimension width, an Anti-Reflective Layer (ARL) is used, such as a Plasma Enhanced chemical vapor deposition Anti-Reflective Layer (PEARL) or other Anti-Reflective Coatings (ARCS), such as a conductive film like TiN. This ARL formation occurs after the capacitor specific process steps, but prior to the masking used for defining the lower electrodes. A Rapid Thermal Oxidation (RTO) is performed subsequent to removing the unwanted capacitor dielectric layer from the transistor poly outside of the capacitor regions, but prior to the PEARL deposition.
    Type: Grant
    Filed: May 31, 2011
    Date of Patent: December 4, 2012
    Assignee: IXYS CH GmbH
    Inventors: Timothy K. Carns, John L. Horvath, Lee J. DeBruler, Michael J. Westphal
  • Patent number: 8324049
    Abstract: A semiconductor device and a method for fabricating a semiconductor device are provided. The method for fabricating a semiconductor device includes forming an isolation layer over a semiconductor substrate defining first and second regions, etching the isolation layer at an edge of the first region to form a guard ring pattern, forming a buried guard ring filling the guard ring pattern, selectively etching the isolation layer of the first region to form a plurality of patterns, forming a plurality of conductive patterns in the respective patterns, and completely removing the isolation layer of the first region through a dip-out process.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: December 4, 2012
    Assignee: Hynix Semiconductor, Inc.
    Inventors: Jin-A Kim, Seok-Ho Jie
  • Patent number: 8191217
    Abstract: A high density capacitor and low density capacitor simultaneously formed on a single wafer and a method of manufacture is provided. The method includes depositing a bottom plate on a dielectric material; depositing a low-k dielectric on the bottom plate; depositing a high-k dielectric on the low-k dielectric and the bottom plate; depositing a top plate on the high-k dielectric; and etching a portion of the bottom plate and the high-k dielectric to form a first metal-insulator-metal (MIM) capacitor having a dielectric stack with a first thickness and a second MIM capacitor having a dielectric stack with a second thickness different than the first thickness.
    Type: Grant
    Filed: August 5, 2009
    Date of Patent: June 5, 2012
    Assignee: International Business Machines Corporation
    Inventors: James S. Dunn, Zhong-Xiang He, Anthony K. Stamper
  • Patent number: 8187934
    Abstract: A method of fabricating a memory cell comprises forming a plurality of doped semiconductor layers on a carrier substrate. The method further comprises forming a plurality of digit lines separated by an insulating material. The digit lines are arrayed over the doped semiconductor layers. The method further comprises etching a plurality of trenches into the doped semiconductor layers. The method further comprises depositing an insulating material into the plurality of trenches to form a plurality of electrically isolated transistor pillars. The method further comprises bonding at least a portion of the structure formed on the carrier substrate to a host substrate. The method further comprises separating the carrier substrate from the host substrate.
    Type: Grant
    Filed: July 27, 2010
    Date of Patent: May 29, 2012
    Assignee: Micron Technology, Inc.
    Inventors: David H. Wells, H. Montgomery Manning
  • Patent number: 8183101
    Abstract: The drain and source regions of a multiple gate transistor may be formed without an epitaxial growth process by using a placeholder structure for forming the drain and source dopant profiles and subsequently masking the drain and source areas and removing the placeholder structures so as to expose the channel area of the transistor. Thereafter, corresponding fins may be patterned and a gate electrode structure may be formed. Consequently, reduced cycle times may be accomplished due to the avoidance of the epitaxial growth process.
    Type: Grant
    Filed: November 17, 2009
    Date of Patent: May 22, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Robert Mulfinger, Andy Wei, Jan Hoentschel, Andrew Waite
  • Patent number: 8178405
    Abstract: A memory cell device has a bottom electrode and a top electrode, a plug of memory material in contact with the bottom electrode, and a cup-shaped conductive member having a rim that contacts the top electrode and an opening in the bottom that contacts the memory material. Accordingly, the conductive path in the memory cells passes from the top electrode through the conductive cup-shaped member, and through the plug of phase change material to the bottom electrode.
    Type: Grant
    Filed: April 7, 2010
    Date of Patent: May 15, 2012
    Assignee: Macronix International Co., Ltd.
    Inventors: Erh-Kun Lai, ChiaHua Ho, Kuang Yeu Hsieh
  • Patent number: 8163613
    Abstract: A method of forming a plurality of capacitors includes forming a plurality of individual capacitor electrodes using two masking steps. An earlier of the two masking steps is used to form an array of first openings over a plurality of storage node contacts. A later of the two masking steps is used to form an array of second openings received partially over and partially offset from the array of first openings. Overlapping portions of the first and second openings are received over the storage node contacts. After both of the two masking steps, conductive material of the individual capacitor electrodes is deposited into the overlapping portions of each of the first and second openings. The individual capacitor electrodes are incorporated into a plurality of capacitors. Other aspects and implementations are contemplated.
    Type: Grant
    Filed: June 25, 2010
    Date of Patent: April 24, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Fred D. Fishburn
  • Patent number: 8163646
    Abstract: A method for manufacturing an interconnection wiring structure of a semiconductor device includes forming an isolation region, which arranges active regions in a diagonal direction, in a semiconductor substrate; forming first damascene trenches, which open upper portions of a bit line contacts, by selectively etching a second interlayer insulation layer; forming bit lines which fill the first damascene trenches; forming second damascene trenches, which expose portions of the active region, by selectively etching the portion of a second interlayer insulation layer between the bit lines and the portion of the first interlayer insulation layer thereunder; attaching trench spacer on side walls of the second damascene trench; forming storage node contact lines which fill the second damascene trenches.
    Type: Grant
    Filed: November 9, 2009
    Date of Patent: April 24, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Chun Soo Kang
  • Patent number: 8153486
    Abstract: A method for fabricating a capacitor includes forming an etch stop layer, a first isolating insulation layer, and a floating layer over a substrate including storage node contact plugs to form a resulting substrate structure; etching the floating layer, the first isolating insulation layer, and the etch stop layer to form a plurality of open regions; forming a conductive layer over the substrate structure; forming a second isolating insulation layer over the conductive layer, the second isolating insulation layer filling upper portions of the open regions; etching portions of the remaining floating layer to form a floating pattern; performing a storage node isolation process in a manner that the floating pattern is exposed to form a plurality of storage nodes having sidewalls supported by the floating pattern; and removing the etched first isolating insulation layer.
    Type: Grant
    Filed: November 5, 2009
    Date of Patent: April 10, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Seok-Ho Jie
  • Patent number: 8148223
    Abstract: Embedded memories. The devices include a substrate, a first dielectric layer, a second dielectric layer, a third dielectric layer, and a plurality of capacitors. The substrate comprises transistors. The first dielectric layer, embedding first and second conductive plugs electrically connecting the transistors therein, overlies the substrate. The second dielectric layer, comprising a plurality of capacitor openings exposing the first conductive plugs, overlies the first dielectric layer. The capacitors comprise a plurality of bottom plates, respectively disposed in the capacitor openings, electrically connecting the first conductive plugs, a plurality of capacitor dielectric layers respectively overlying the bottom plates, and a top plate, comprising a top plate opening, overlying the capacitor dielectric layers. The top plate opening exposes the second dielectric layer, and the top plate is shared by the capacitors.
    Type: Grant
    Filed: May 22, 2006
    Date of Patent: April 3, 2012
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Ching Lin, Chun-Yao Chen, Chen-Jong Wang, Shou-Gwo Wuu, Chung S. Wang, Chien-Hua Huang, Kun-Lung Chen, Ping Yang
  • Patent number: 8138042
    Abstract: A capacitor includes a substrate (110, 210), a first electrically insulating layer (120, 220) over the substrate, and a fin (130, 231) including a semiconducting material (135) over the first electrically insulating layer. A first electrically conducting layer (140, 810) is located over the first electrically insulating layer and adjacent to the fin. A second electrically insulating layer (150, 910) is located adjacent to the first electrically conducting layer, and a second electrically conducting layer (160, 1010) is located adjacent to the second electrically insulating layer. The first and second electrically conducting layers together with the second electrically insulating layer form a metal-insulator-metal stack that greatly increases the capacitance area of the capacitor. In one embodiment the capacitor is formed using what may be referred to as a removable metal gate (RMG) approach.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: March 20, 2012
    Assignee: Intel Corporation
    Inventors: Brian S. Doyle, Robert S. Chau, Suman Datta, Vivek De, Ali Keshavarzi, Dinesh Somasekhar
  • Patent number: 8129251
    Abstract: A METAL-INSULATOR-METAL structured capacitor is formed with polysilicon instead of an oxide film as a sacrificial layer material that defines a storage electrode region. A MPS (Meta-stable Poly Silicon) process is performed to increase the surface area of the sacrificial layer that defines the storage electrode region and also increase the area of the storage electrode formed over sacrificial layer. This process results in increasing the capacity of the capacitor in a stable manner.
    Type: Grant
    Filed: November 13, 2006
    Date of Patent: March 6, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Won Sun Seo
  • Patent number: 8114732
    Abstract: A method and system for forming a non-volatile memory structure. The method includes providing a semiconductor substrate and forming a gate dielectric layer overlying a surface region of the semiconductor substrate. A polysilicon gate structure is formed overlying the gate dielectric layer. The method subjects the polysilicon gate structure to an oxidizing environment to cause formation of a first silicon oxide layer overlying the polysilicon gate structure and formation of an undercut region underneath the polysilicon gate structure. An aluminum oxide material is formed overlying the polysilicon gate structure filling the undercut region. In a specific embodiment, the aluminum oxide material has a nanocrystalline silicon material sandwiched between a first aluminum oxide layer and a second aluminum oxide layer. The aluminum oxide material is subjected to a selective etching process while maintaining the aluminum oxide material in an insert region in a portion of the undercut region.
    Type: Grant
    Filed: February 11, 2010
    Date of Patent: February 14, 2012
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Mieno Fumitake
  • Patent number: 8084323
    Abstract: The invention provides a method for forming a stack capacitor of a memory device, including providing a substrate, forming a patterned sacrificial layer with a plurality of first openings over the substrate, conformally forming a first conductive layer on the patterned sacrificial layer and in the first openings, forming a second conductive layer on the first conductive layer to seal the first openings with a void formed therein, removing a portion of the first and second conductive layers to expose the patterned sacrificial layer, and removing at least a portion of the patterned sacrificial layer to form bottom cell plates.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: December 27, 2011
    Assignee: Nanya Technology Corporation
    Inventor: Shin-Yu Nieh
  • Patent number: 8053308
    Abstract: In a method of forming a pattern, a mold layer having an opening is formed on a substrate. A conductive layer is formed on the mold layer having the opening, the conductive layer having a substantially uniform thickness. A buffer layer pattern is formed in the opening having the conductive layer, the buffer layer pattern having a cross-linked structure of water-soluble copolymers including a repeating unit of N-vinyl-2-pyrrolidone and a repeating unit of acrylate. An upper portion of the conductive layer exposed over the buffer layer pattern is etched. Accordingly, a conductive pattern for a semiconductor device is formed on the substrate. The method of forming a pattern may simplify manufacturing processes for a capacitor and a semiconductor device, and may improve their efficiencies.
    Type: Grant
    Filed: November 27, 2007
    Date of Patent: November 8, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyoung-Min Kim, Jae-Ho Kim, Young-Ho Kim, Myung-Sun Kim
  • Patent number: 8048757
    Abstract: A method for fabricating a capacitor includes forming an isolation layer over a cell region and a peripheral region of a substrate. The isolation layer forms a plurality of open regions in the cell region. Storage nodes are formed on surfaces of the open regions. An upper portion of the isolation layer is etched to expose upper outer walls of the storage nodes. A sacrificial pattern is formed over the isolation layer to enclose the upper outer walls of the storage nodes. The isolation layer in the peripheral region is etched to expose side portions of the resulting structure obtained after forming the sacrificial pattern in the cell region. With the sacrificial pattern supporting the storage nodes, the isolation layer in the cell region is removed. The sacrificial pattern is then removed.
    Type: Grant
    Filed: March 22, 2011
    Date of Patent: November 1, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Jae-Sung Roh, Kee-Jeung Lee, Han-Sang Song, Seung-Jin Yeom, Deok-Sin Kil, Young-Dae Kim, Jin-Hyock Kim
  • Patent number: 8048758
    Abstract: A method for fabricating a capacitor includes forming an isolation layer over a cell region and a peripheral region of a substrate. The isolation layer forms a plurality of open regions in the cell region. Storage nodes are formed on surfaces of the open regions. A sacrificial pattern is formed over the isolation layer and covers the cell region. The isolation layer is etched in the peripheral region to expose side portions of the resulting structure obtained after forming the sacrificial pattern in the cell region. With the sacrificial pattern supporting the storage nodes, the isolation layer in the cell region is removed. The sacrificial pattern is then removed.
    Type: Grant
    Filed: March 22, 2011
    Date of Patent: November 1, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Jae-Sung Roh, Kee-Jeung Lee, Han-Sang Song, Seung-Jin Yeom, Deok-Sin Kil, Young-Dae Kim, Jin-Hyock Kim
  • Patent number: 8021948
    Abstract: A method for manufacturing a non-volatile memory device is described. The method comprises growing a layer in a siliconoxide consuming material, e.g. DyScO, on top of the upper layer of the layer where charge is stored. A non-volatile memory device is also described. In the non-volatile memory device, the interpoly/blocking dielectric comprises a layer in a siliconoxide consuming material, e.g. DyScO, on top of the upper layer of the layer where charge is stored, the siliconoxide consuming material having consumed at least part of the upper layer.
    Type: Grant
    Filed: December 18, 2008
    Date of Patent: September 20, 2011
    Assignee: IMEC
    Inventors: Bogdan Govoreanu, Stefan De Gendt, Sven Van Elshocht, Tom Schram
  • Patent number: 8017475
    Abstract: A method of fabricating a high-performance capacitor that may be incorporated into a standard CMOS fabrication process suitable for submicron devices is described. The parameters used in the standard CMOS process may be maintained, particularly for the definition and etch of the lower electrode layer. To reduce variation in critical dimension width, an Anti-Reflective Layer (ARL) is used, such as a Plasma Enhanced chemical vapor deposition Anti-Reflective Layer (PEARL) or other Anti-Reflective Coatings (ARCS), such as a conductive film like TiN. This ARL formation occurs after the capacitor specific process steps, but prior to the masking used for defining the lower electrodes. A Rapid Thermal Oxidation (RTO) is performed subsequent to removing the unwanted capacitor dielectric layer from the transistor poly outside of the capacitor regions, but prior to the PEARL deposition.
    Type: Grant
    Filed: July 20, 2010
    Date of Patent: September 13, 2011
    Assignee: IXYS CH GmbH
    Inventors: Timothy K. Carns, John L. Horvath, Lee J. DeBruler, Michael J. Westphal
  • Patent number: 7985645
    Abstract: A semiconductor device having a high aspect cylindrical capacitor and a method for fabricating the same is presented. The high aspect cylindrical type capacitor is a stable structure which is not prone to causing bunker defects and losses in a guard ring. The semiconductor device includes the cylindrical type capacitor structure, a storage node oxide, a guard ring hole, a conductive layer, and a capping oxide. The cylindrical type capacitor structure in a cell region includes a cylindrical type lower electrode, a dielectric and an upper electrode. The storage node oxide is in a peripheral region over the semiconductor substrate. The conductive layer coating the guard ring hole. The guard ring hole at a boundary of the peripheral region that adjoins the cell region over the semiconductor substrate. The capping oxide partially fills in a part of the conductive layer. The gapfill film filling in the rest of the conductive layer.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: July 26, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Cheol Hwan Park, Ho Jin Cho, Dong Kyun Lee