Abstract: A transistor-type ferroelectric nonvolatile memory element having an MFMIS (metal-ferroelectric-metal-insulator-semiconductor) structure that can be highly densely integrated. The MFMIS transistor has a constitution in which the MFM (metal-ferroelectric-metal) structure and the MIS (metal-insulator-semiconductor) structure are stacked up and down on nearly the same area, and the lower MIS structure has means for increasing the effective area of the MIS capacitance. Means for increasing the effective area of the capacitor is a trench in the semiconductor substrate, ruggedness in the MIS structure or a MIN (metal-insulator-metal) structure.

Abstract: A method for forming of a capacitor wherein an etching barrier layer comprising a stacked structure of a nitride film and a tantalum oxide film is disclosed. The method comprises the steps of: forming an etching barrier layer on an interlayer insulating film having a storage electrode contact plug therein, the etching barrier layer comprising a stacked structure of a nitride film and a tantalum oxide film; forming an oxide film on the etching barrier layer; selectively etching the oxide film and the etching barrier layer to form an opening exposing the storage electrode contact plug; depositing a storage electrode layer on the bottom and the inner walls of the opening; and removing the oxide film, whereby forming a storage electrode.

Abstract: In a semiconductor device producing method, a plug is formed within a contact hole formed in a barrier film and an interlayer insulating film on a semiconductor substrate. Then, an insulation film is formed on the plug and barrier film, and a hole is made in the insulation film such that an upper surface of the plug is exposed. A first conductive film is formed on the insulation film so as to fill the hole, and then etched by a CMP method to form a lower electrode within the hole. The insulation film is removed and the lower electrode is left in a protuberant manner. A dielectric film made of a ferroelectric or high-dielectric-constant substance and a second conductive film are sequentially formed over the lower electrode and the barrier film, and then patterned simultaneously to thereby form a capacitor dielectric film and an upper electrode.

Abstract: An intermediate metal plug is used to raise the platform to which contact is to be made. In the illustrated process, a partial bit line plug is formed adjacent a stacked capacitor, and an interlevel dielectric formed over the capacitor. The bit line contact is completed by extending a via from the bit line, formed above the interlevel dielectric, down to the level of the intermediate plug, and the via is filled with metal. The height of the via to be filled is thus reduced by the height of the intermediate plug. In one embodiment, the intermediate plug is slightly shorter than an adjacent container-shaped capacitor. In another embodiment, the intermediate plug is about as high as an adjacent stud capacitor.

Abstract: A unique electrochemical process fills oxygen vacancies in dielectrics while reducing oxidation of nearby electrodes and conductors. Preferably, an electromagnetic field or bias is applied to a dielectric. The bias causes oxygen vacancies in the dielectric to migrate to the surface of the dielectric. As the oxygen vacancies migrate toward the surface, oxygen ions fill the oxygen vacancies. In one embodiment, a unique plasma treatment provides the oxygen ions that react with the oxygen vacancies. In another embodiment, a unique electrolysis treatment provides the oxygen ions that react with the oxygen vacancies.

Abstract: A method for fabricating a high-density array of crown capacitors with increased capacitance while reducing process damage to the bottom electrodes is achieved. The process is particularly useful for crown capacitors for future DRAM circuits with minimum feature sizes of 0.18 micrometer or less. A conformal conducting layer is deposited over trenches in an interlevel dielectric (ILD) layer, and is polished back to form capacitor bottom electrodes. A novel photoresist mask and etching are then used to pattern the ILD layer to provide a protective interlevel dielectric structure between capacitors. The protective structures prevent damage to the bottom electrodes during subsequent processing. The etching also exposes portions of the outer surface of bottom electrodes for increased capacitance (>50%). In a first embodiment the ILD structure is formed between pairs of adjacent bottom electrodes, and in a second embodiment the ILD structure is formed between four adjacent bottom electrodes.

Abstract: A ferroelectric capacitor is fabricated using a noble metal hardmask. A hardmask is deposited on a top electrode of a capacitor stack comprising a ferroelectric layer sandwiched between the top electrode and a bottom electrode. The top electrode is patterned according to the pattern of the hardmask by etching at a first temperature. The top electrode serves as the noble metal hardmask and the ferroelectric layer is patterned according to the pattern of the top electrode at a second temperature lower than the first temperature, resulting in the top electrode having sidewalls beveled relative to a top surface of the top electrode etching. The bottom electrode is etched at a third temperature to form the capacitor.

Abstract: The disclosure describes a stacked capacitor and a method of forming the same. The method prevents a storage node of the stacked capacitor from crumbling due to lack of support, thereby improving the reliability of semiconductor devices that incorporate stacked capacitors. The disclosure also describes a stacked capacitor with a greater capacitance than a stacked capacitor in accordance with the conventional art.

Abstract: The invention encompasses DRAM constructions, capacitor constructions, integrated circuitry, and methods of forming DRAM constructions, integrated circuitry and capacitor constructions. The invention encompasses a method of forming a capacitor wherein: a) a first layer is formed; b) a semiconductive material masking layer is formed over the first layer; c) an opening is etched through the masking layer and first layer to a node; d) a storage node layer is formed within the opening and in electrical connection with the masking layer; e) a capacitor storage node is formed from the masking layer and the storage node layer; and f) a capacitor dielectric layer and outer capacitor plate are formed operatively proximate the capacitor storage node.

Abstract: Provided herein are vertical nanotube semiconductor devices and methods for making the same. An embodiment of the semiconductor devices comprises a vertical transistor/capacitor cell including a nanotube. The device includes a vertical transistor and a capacitor cell both using a single nanotube to form the individual devices.

Abstract: A method for forming a storage node contact plug of a dynamic random access memory includes forming insulating layers on an overall surface of a semiconductor substrate having a plurality of buried contact plugs, etching the insulating layers down to a top surface of the buried contact plugs to form first contact holes on the buried contact plugs, forming a photoresist pattern on the insulating layers and the first contact holes, etching the insulating layers to form second contact holes on the second insulating layer, and filling the first and second contact holes with conductive material.

Abstract: A method for manufacturing a capacitor bottom electrode by using low k dielectric material as a sacrificial layer is employed to simplify manufacturing steps and prevent electrical shortage phenomenon of bottom electrodes.

Abstract: A storage node contact forming method and structure reduces the number of processes required by the conventional art and increases a critical dimension of a storage node to prevent a leaning phenomenon and reduce a manufacturing cost of semiconductor memory devices. The method includes preparing a semiconductor substrate that involves at least one contact pad contacted with an active region of a memory cell transistor through an insulation layer. The method also includes forming a storage node contact of T-shape, the storage node contact being composed of a lower region contacted with an upper part of the contact pad, and an upper region that is extended to a gate length direction of the memory cell transistor and that is formed as a size larger than a size of the lower region, in order to electrically connect the contact pad with a storage node to be formed in a later process.

Abstract: Methods of forming metal-insulator-metal type capacitors in integrated circuit memory devices can include crystallizing an HfO2 dielectric layer on a lower electrode of a capacitor structure in a low temperature plasma treatment at a temperature in range between about 250 degrees Centigrade and about 450 degrees Centigrade. An upper electrode can be formed on the HfO2 dielectric layer.

Abstract: A manufacturing method of carbon nanotube transistors is disclosed. The steps include: forming an insulating layer on a substrate; forming a first oxide layer on the insulating layer using a solution with cobalt ion catalyst by spin-on-glass (SOG); forming a second oxide layer on the first oxide layer using a solution without the catalyst; forming a blind hole on the second oxide layer using photolithographic and etching processes, the blind hole exposing the first oxide layer, the sidewall of the second oxide layer, and the insulating layer; forming a single wall carbon nanotube (SWNT) connecting the first oxide layer separated by the blind hole and parallel to the substrate; and forming a source and a drain connecting to both ends of the SWNT, respectively.

Abstract: The present invention relates to a method for fabricating a capacitor of a semiconductor memory device using an electrochemical deposition. The method in accordance with the present invention includes the steps of forming a contact hole in an insulating layer formed on a substrate; forming a plug in the contact hole, wherein the plug contains a nitride layer; forming a seed layer on the insulating layer and in the contact hole; forming a sacrificial layer including a trench overlapped with the contact hole; forming a Ru bottom electrode in the trench with electrochemical deposition; removing the sacrificial layer and exposing the Ru bottom electrode, wherein the seed layer not covered with the Ru bottom electrode is exposed; removing the exposed seed layer; forming a dielectric layer on the Ru bottom electrode; and forming a top electrode on the dielectric layer.

Abstract: The method of forming a ferroelectric memory device includes forming capacitor patterns over a substrate, each capacitor pattern having an adhesive assistant pattern, a lower electrode, a ferroelectric pattern, and an upper electrode. An oxygen barrier layer is formed over the substrate and is etched to expose a sidewall of the ferroelectric pattern but not a sidewall of the adhesive assistant pattern. Then, a thermal process for curing ferroelectricity of the ferroelectric pattern is performed.

Abstract: A stress buffer and dopant barrier in the form of a TetraEthylOrthoSilicate (TEOS) film is deposited after the capacitor cell plate has been etched and cleaned to thereby eliminate electrical shorts from the bit line to the cell plate.

Abstract: A method of fabricating a metal-insulator-metal (MIM) capacitor of a semiconductor device having an upper and lower electrode formed of metal is provided. Portions of a conductive layer for a lower electrode on inner walls of holes are not removed. Portions of the conductive layer for a lower electrode outside the holes are selectively etched back and node-separated.

Abstract: A semiconductor device capable of preventing a ring defect and a method of manufacturing the same are provided. The semiconductor device includes a semiconductor substrate having a junction region, a planarization layer having a first contact hole portion through which the junction region is exposed, an interlayer dielectric layer formed on the planarization layer and having a second contact hole portion extended from the first contact hole portion, and contact spacers formed at the sidewalls of the first and second contact hole portions. Here, the contact spacers are formed to cover the interface between the planarization layer and the interlayer dielectric layer and the interface between the planarization layer and the semiconductor substrate.

Abstract: A method for manufacturing DRAM cells in a semiconductor wafer including MOS control transistors and capacitors, the source/drain regions and the gates of the control transistors being covered with a protection layer and with an insulating layer, in which the capacitors are formed at the level of openings formed in the insulating layer which extend to the protection layer covering the gates, and in which first capacitor electrodes are connected to source/drain regions of the control transistors by conductive vias crossing the insulating layer and the protection layer.

Abstract: The present invention is related to a method for fabricating a semiconductor device capable of preventing a bit line pattern from being attacked during a storage node contact hole formation. The method includes the steps of: forming a bit line insulation layer on a substrate structure having a plurality of plugs; forming a group of trenches exposing a group of the plugs by etching the bit line insulation layer; burying each trench by a conductive material to form a bit line electrically connected to the exposed plug; isolating the bit line by performing a chemical mechanical polishing process until the bit line insulation layer is exposed; forming an inter-layer insulation layer on the above structure including the bit line; and etching selectively the inter-layer insulation layer and the bit line insulation layer to form storage node contact holes exposing another group of the plugs.

Abstract: The invention provides robust and cost effective techniques to fabricate double-sided HSG electrodes for container capacitors. In one embodiment, this is accomplished by forming a layer of hemispherical silicon grain (HSG) polysilicon over interior surfaces of a container formed in a substrate. A barrier layer is then formed over the formed HSG polysilicon layer. Any HSG polysilicon and barrier layers formed over the substrate and around the container opening during the forming of the HSG polysilicon and barrier layers is then removed. A portion of outside surfaces of the formed HSG polysilicon is then exposed by removing the substrate, while the barrier layer is still on the interior surface of the container to prevent formation of sink holes and to prevent stringer problems during removal of the substrate. The barrier layer is then removed to expose the interior surfaces of the HSG polysilicon to form the double-sided HSG electrode.

Abstract: The present invention is related to a method for forming a storage node of a semiconductor device. The method includes the steps of: (a) forming a plurality of bit line patterns, each including a wire and a hard mask sequentially stacked on a surface of a substrate structure; (b) sequentially forming a first barrier layer and a first inter-layer insulation layer along a profile containing bit line patterns until filling spaces between the bit line patterns; (c) etching the first inter-layer insulation layer until a partial portion of the first inter-layer insulation layer remains on each space between the bit line patterns; (d) forming a second barrier layer on the first inter-layer insulation layer and the first barrier layer; and (e) etching the first and the second barrier layers and the remaining first inter-layer insulation layer to expose a surface of the substrate structure disposed between the bit line patterns.

Abstract: In order to fabricate a semiconductor component having a contact electrode that is T-shaped in cross section, in particular a field-effect transistor with a T gate, a method is described in which a self-aligning positioning of gate base and gate head is effected by means of a spacer produced on a material edge.

Abstract: A method used to manufacture a semiconductor device comprises providing a first conductive container capacitor top plate layer and etching the first conductive container capacitor top plate layer to form a plurality of openings therein. Subsequently, a container capacitor bottom plate layer is formed within the plurality of openings in the top plate layer such that the bottom plate layer defines a plurality of openings. A second conductive container capacitor top plate layer is formed within the plurality of openings in the bottom plate layer. The first conductive container capacitor top plate layer is electrically coupled with the second conductive container capacitor top plate layer. The first and second conductive container capacitor top plate layers and the container capacitor bottom plate layer form a plurality of container capacitors. A structure resulting from the method is also disclosed.

Abstract: A method for fabricating a capacitor in a semiconductor device is disclosed.

Abstract: A capacitor is fabricated over a first layer having a first conductive plug formed on a substrate in a semiconductor memory. On the first layer, a silicon nitride film, a first capacitor oxide film, and a second oxide film are sequentially formed. The first and the second oxide films have different wet etch rates. Dry and wet etchings are sequentially performed to the first and second oxide films to form a second contact hole. The second contact hole is then etched. Thereafter, a silicon film and a filler film are sequentially formed on the resultant surface of the structure. A cylindrical storage node electrode is then formed by etching a predetermined portion of the filler film and the silicon film. After removing the remaining filler film and the oxide films, a Ta2O5 dielectric film covering the storage node electrode and a TiN film for an upper electrode are then sequentially formed.

Abstract: The present teachings describe a container capacitor that utilizes an etchant permeable lower electrode for the formation of single or double-sided capacitors without excessive etching back of the periphery of the use of sacrificial spacers. The present teachings further describe a method of forming at least one capacitor structure on a substrate. For example, the method comprises forming at least one recess in the substrate, depositing a first conductive layer on the substrate so as to overlie the at least one recess, and defining at least one lower electrode within the at least one recess formed in the substrate by removing at least a portion of the first conductive layer. The method further comprises diffusing an etchant through the at least one lower electrode so as to remove at least a portion of the substrate to thereby at least partially isolate the at least one lower electrode.

Abstract: A method for forming a charge storage node is disclosed. The method for forming a charge storage node prevents the bridge between cells and maximize the hole size of a cell forming portion to thus improve the properties of a device and increase product yield by depositing an oxide film having a predetermined thickness and forming a contact hole in order to fill the hole of a notch type generated by the etching difference between a damaged sacrificial oxide film and an oxide film for capacitor formation deposited thereon after enlarging the hole size by washing and dipping processes before the formation of the charge storage node.

Abstract: A method for fabricating a semiconductor device is disclosed. A spacer is formed on the sidewall of the contact hole in which a storage node contact plug is buried. An etch barrier film and an insulating film are sequentially formed after the formation of the storage node contact plug. The insulating film and the etch barrier film are sequentially etched to form an opening part. Then a storage node is formed within the opening part which has been formed by an etching. Then prominences are formed on the surface of the storage node.

Abstract: Methods of forming electrical connections with an integrated circuitry substrate node location are described. According to one aspect of the invention, a substrate node location is laterally surrounded with insulating material and left outwardly exposed. Conductive material is deposited over the exposed node location. Subsequently, a photomaskless etch of the conductive material is conducted to a degree sufficient to leave a plug of conductive material over the node location. In a preferred implementation, the insulating material with which such node location is surrounded constitutes insulating material portions which are provided relative to conductive lines which are formed over the substrate. In another preferred implementation, such conductive lines form a grid of insulating material which, in turn, defines the node location.

Abstract: A semiconductor device is fabricated using a micro-masking structure. The micro-masking structure is formed along the sidewalls of a trench in a semiconductor substrate or along the sidewalls of an electrode disposed over the semiconductor substrate. The micro-masking structure exposes portions of the sidewalls and covers other portions of the sidewalls. Then the exposed portions of the sidewalls are recessed to form a plurality of recesses such that the sidewalls have an increase surface area. After the recessing, the micro-masking structure is removed. The recessed sidewalls provide enhanced capacitance.

Abstract: The preferred embodiment of the present invention provides unique structure for connecting between a storage capacitor and a transfer device in a memory cell and a method for fabricating the same. The preferred embodiment of the present invention forms a capacitor structure having a “lip” at its top on the side the connection is to be made. To form the connection, dopant is diffused from the lower surface of the capacitor step and into the substrate, forming a surface strap to connect between the storage capacitor and the transfer device. This surface strap has the advantage of being self aligned with the storage capacitor and the transfer device, facilitating higher memory cell densities. The present invention can be used to form connections between storage capacitors and memory cells in a wide variety of devices.

Abstract: Sputter etching of silicon oxide films is performed with an etching gas such as C4F8. Since a silicon nitride film is little etched at this time, when the etching is performed under a condition of sufficient overetching for the silicon oxide films, the silicon nitride film serves as an etching stopper, and the silicon oxide film on a platinum film and the silicon oxide film other than a portion below the platinum film are completely removed and the silicon oxide film remains only below the platinum film, to form a protrusion of a layer consisting of the silicon oxide film and the platinum film from a surface of the silicon nitride film. Thus, in patterning, a capacitor lower electrode by chemical etching, a nonuniform etching caused by temperature distribution on a substrate or among a plurality of substrates can be solved.

Abstract: In a DRAM memory cell that is a semiconductor memory device, a bit line connected to a bit line plug and local interconnect are provided on a first interlayer insulating film. A contact is not provided on a Pt film constituting an upper electrode, and a dummy lower electrode is in direct contact with a dummy barrier metal. That is, the upper electrode is connected to upper layer interconnect (Cu interconnect) by the dummy lower electrode, a dummy cell plug and the local interconnect. Since the Pt film is not exposed to a reducing atmosphere, deterioration of characteristics of a capacitive insulating film can be prevented.

Abstract: In order to improve the performance of a semiconductor integrated circuit device wherein a capacitor provided between storage nodes of an SRAM and a device having an analog capacitor are formed on a single substrate, a plug is formed in a silicon oxide film on a pair of n channel type MISFETs in a memory cell forming area, and a local wiring LIc for connecting respective gate electrodes and drains of the pair of n channel type MISFETs is formed over the silicon oxide film and the plug. Thereafter, a capacitive insulating film and an upper electrode are further formed over the local wiring LIc. According to the same process step as the local wiring, capacitive insulating film and upper electrode formed in the memory cell forming area, a local wiring LIc, a capacitive insulating film and an upper electrode are formed over a silicon oxide film in an analog capacitor forming area and a plug in the silicon oxide film.

Abstract: A method for fabricating capacitor capable of simplifying formation processes of ruthenium (Ru) layer for storage node electrode formation of capacitor comprises the steps of: forming a first insulating layer having a first opening exposing a predetermined region on a substrate; forming a conductive plug filled within the first opening; forming a second insulating layer having a second opening exposing the conductive plug on the first insulating layer; forming a conductive layer covering the second opening by sequentially performing PECVD and LPCVD processes on the second insulating layer; exposing the second insulating layer by performing etch back on the conductive layer; forming a storage node electrode of the capacitor by removing the second insulating layer; and forming a dielectric layer to cover the storage node electrode; and forming a plate electrode. In an alternative embodiment, a thermal treatment under an N2 gas supply is performed after the step of forming the conductive layer.

Abstract: A method of programming a first memory cell in an array of at least four memory cells in a semiconductor device, each memory cell including a polysilicon gate, first and second spaced-apart diffused regions, a silicide layer provided over the polysilicon gate, an oxide spacer provided contiguous with a vertical sidewall of the polysilicon gate, and a layer of phase change material provided over at least a portion of the silicide layer, contiguous with the oxide spacer, and over the first diffused region.

Abstract: A method for fabricating a capacitor of a semiconductor device is disclosed, in which it is possible to obtain reliability in an etch process, and to simplify manufacturing process steps.

Abstract: A ferroelectric capacitor encapsulation method for preventing hydrogen damage to electrodes and ferroelectric material of the capacitor. In general terms, the method for encapsulating a capacitor includes etching a bottom electrode of a capacitor to expose an underlying wafer surface. An undercut is etched between the capacitor and the wafer surface. The undercut is refilled with a barrier layer to reduce the diffusion of hydrogen from the surface of the wafer into the capacitor.

Abstract: Within a method for fabricating a microelectronic fabrication, and the microelectronic fabrication fabricated employing the method, there is formed within the microelectronic fabrication a capacitor structure which comprises a first capacitor plate layer having formed thereupon a capacitor dielectric layer in turn having formed thereupon a second capacitor plate layer, wherein each of the foregoing layers having an exposed sidewall to thus form a series of exposed sidewalls. The capacitor structure also comprises a silicon oxide dielectric layer formed passivating the series of exposed sidewalls of the first capacitor plate layer, the capacitor dielectric layer and the second capacitor plate layer a silicon oxide dielectric layer.

Abstract: Disclosed is a method of forming a capacitor in a semiconductor device.

Abstract: A rough polysilicon film located on the upper surface of an interlayer film is removed by a CMP process, so that storage nodes and an embedded TEOS film are formed. The embedded TEOS film is removed concurrently with the interlayer film located in a memory cell region by etching. An opening end of a groove, the upper surface of the embedded TEOS film and the upper surface of the interlayer film are arranged on substantially the same plane. In the memory cell region and a peripheral circuit region, a substantially flat interlayer insulation film is obtained. This solves the problems of a step, falling and the like in a semiconductor device including a capacitor element.

Abstract: Methods for manufacturing a storage node of a capacitor of a semiconductor device and a storage node manufactured by these methods are provided. An exemplary method for manufacturing a storage node of a capacitor of a semiconductor device includes forming a mold layer on a semiconductor substrate, forming a mold for the storage node by patterning the mold layer by a photolithography process, introducing a photomask which includes a plurality of light transmitting patterns separated from each other and which define the region to be occupied by the storage node, and forming a storage node that has the shape formed by the mold. The photolithography process is performed with the occurrence of a pattern bridge phenomenon, e.g., the transferred light transmitting patterns are connected to each other in a pattern transferred from the light transmitting patterns to the mold.

Abstract: A semiconductor device and method for fabricating same according to an embodiment of the invention includes: preparing a semiconductor substrate having a first contact pad and a second contact pad; forming a first insulating film on the substrate; etching the first insulating film to form a groove-shaped bit line pattern and a contact exposing the first contact pad and the second contact pad, respectively; simultaneously forming a contact plug and a bit line in the contact and the bit line pattern, respectively, the contact plug and the bitline having upper surfaces that are coplanar; and forming a bottom electrode for a capacitor that is connected to the first contact pad.

Abstract: A high dielectric constant memory cell capacitor and method for producing the same, wherein the memory cell capacitor utilizes relatively large surface area conductive structures of thin spacer width pillars or having edges without sharp corners that lead to electric field breakdown of the high dielectric constant material. The combination of high dielectric constant material in a memory cell along with a relatively large surface area conductive structure is achieved through the use of a buffer material as caps on the thin edge surfaces of the relatively large surface area conductive structures to dampen or eliminate the intense electric field which would be generated at the corners of the structures during the operation of the memory cell capacitor had the caps not been present.

Abstract: A semiconductor device for use in a memory cell including an active matrix provided with a silicon substrate, at least one transistor formed on the silicon substrate, a number of bottom electrodes formed over the transistors, a plurality of conductive plugs to electrically connect the bottom electrodes to the transistors, respectively, and an insulating layer formed around the conductive plugs. In the device, by carrying out a carbon treatment to top surface portions of the bottom electrode structure, it is possible to secure enough space to prevent the formation of bridges between the bottom electrodes.

Abstract: The present invention is directed toward methods of fabricating components for microelectronic devices, microelectronic devices including memory cells or other components, and computers including memory devices. For example, one embodiment is directed toward a method of fabricating a memory cell on a workpiece having a substrate, a plurality of active areas in the substrate, and a dielectric layer over the active areas. One embodiment of the method includes constructing bit line contact openings in the dielectric layer over first portions of the active areas and cell plug openings over second portions of the active areas. The method also includes depositing a first conductive material into the bit line contact openings to form bit line contacts and into the cell plug openings to form cell plugs. This embodiment continues by forming a trench through an upper portion of a plurality of the bit line contacts and portions of the dielectric layer between bit line contacts.

Abstract: A method used during the formation of a semiconductor device comprises providing a wafer substrate assembly comprising a plurality of digit line plug contact pads and capacitor storage cell contact pads which contact a semiconductor wafer. A dielectric layer is provided over the wafer substrate assembly and etched to expose the digit line plug contact pads, and a liner is provided in the opening. A portion of the digit line plug is formed, then the dielectric layer is etched again to expose the capacitor storage cell contact pads. A capacitor bottom plate is formed to contact the storage cell contact pads, then the dielectric layer is etched a third time using the liner and the bottom plate as an etch stop layer. A capacitor cell dielectric layer and capacitor top plate is formed which provides a double-sided container cell. An additional dielectric layer is formed, then the additional dielectric layer, cell top plate, and the cell dielectric are etched to expose the digit line plug portion.