Abstract: A semiconductor memory device includes a source region, a drain region, a channel region, a charge storage layer, and a control gate electrode. The source region and drain region are formed separately from each other in a surface of a semiconductor substrate. The channel region is formed in the semiconductor substrate and located between the source region and the drain region. The charge storage layer is formed on the channel region with a first insulating film interposed therebetween. The control gate electrode is formed on the charge storage layer with a second insulating film interposed therebetween. The control gate has an upper corner portion rounded with a radius of curvature of 5 nm or more.

Abstract: Etching is performed on an insulating layer 23 and a conductive layer 32 with a photoresist 41 as the mask, to form an opening 51 in the conductive layer 32. After removing the photoresist 41, another insulating layer 24 is formed all over, which is etched back so as to expose a surface of a conductive layer 31, to thereby cover the inner wall of the opening 51. Then etching is performed on the conductive layer 31 with the latter insulating layer 24 as the mask, so as to form another opening 52 in the conductive layer 31. Then still another insulating layer 25 is formed all over, which is then etched back so as to expose a surface of the conductive layer 32, to thereby fill the opening 52 with the last formed insulating layer 25.

Abstract: A field effect transistor and a method of fabricating the field effect transistor. The field effect transistor includes: a silicon body, a perimeter of the silicon body abutting a dielectric isolation; a source and a drain formed in the body and on opposite sides of a channel formed in the body; and a gate dielectric layer between the body and an electrically conductive gate electrode, a bottom surface of the gate dielectric layer in direct physical contact with a top surface of the body and a bottom surface the gate electrode in direct physical contact with a top surface of the gate dielectric layer, the gate electrode having a first region having a first thickness and a second region having a second thickness, the first region extending along the top surface of the gate dielectric layer over the channel region, the second thickness greater than the first thickness.

Abstract: Fabrication of recessed channel array transistors (RCAT) with a corner gate device includes forming pockets between a semiconductor fin that includes a gate groove and neighboring shallow trench isolations that extend along longs sides of the semiconductor fin. A protection liner covers the semiconductor fin and the trench isolations in a bottom portion of the gate groove and the pockets. An insulator collar is formed in the exposed upper sections of the gate groove and the pockets, wherein a lower edge of the insulator collar corresponds to a lower edge of source/drain regions formed within the semiconductor fin. The protection liner is removed. The bottom portion of the gate groove and the pockets are covered with a gate dielectric and a buried gate conductor layer. The protection liner avoids residuals of polycrystalline silicon between the active area in the semiconductor fin and the insulator collar.

Abstract: For enhancing the high performance of a non-volatile semiconductor memory device having an MONOS type transistor, a non-volatile semiconductor memory device is provided with MONOS type transistors having improved performance in which the memory cell of an MONOS non-volatile memory comprises a control transistor and a memory transistor. A control gate of the control transistor comprises an n-type polycrystal silicon film and is formed over a gate insulative film comprising a silicon oxide film. A memory gate of the memory transistor comprises an n-type polycrystal silicon film and is disposed on one of the side walls of the control gate. The memory gate comprises a doped polycrystal silicon film with a sheet resistance lower than that of the control gate comprising a polycrystal silicon film formed by ion implantation of impurities to the undoped silicon film.

Abstract: Methods for fabricating dual bit flash memory devices are provided. Method steps include forming a charge trapping layer overlying a substrate and fabricating two insulating members overlying the charge trapping layer. A polycrystalline silicon layer is provided overlying the charge trapping layer and about sidewalls of the insulating members. Sidewall spacers are formed overlying the polycrystalline silicon layer and about the sidewalls of the insulating members. A portion of the first polycrystalline silicon layer and a first portion of the charge trapping layer are removed. A first insulating layer is conformally deposited overlying the insulating members and the substrate. A gate spacer is formed between the two insulating members and overlying the first insulating layer. The two insulating members are removed and the charge trapping layer is etched to form charge storage nodes. Impurity dopants are implanted into the substrate to form impurity-doped bitline regions within the substrate.

Abstract: A semiconductor fabrication process includes forming polysilicon nanocrystals on a tunnel oxide overlying a first region of a substrate. A second dielectric is deposited overlying the first region and a second region. Without providing any protective layer overlying the second dielectric in the first region, an additional thermal oxidation step is performed without oxidizing the nanocrystals. A gate electrode film is then deposited over the second dielectric and patterned to form first and second gate electrodes. The second dielectric may be an annealed, CVD oxide. The additional thermal oxidation may include forming by dry oxidation a third dielectric overlying a third region of the semiconductor substrate. The dry oxidation produces a interfacial silicon oxide underlying the second dielectric in the second region. An upper surface of a fourth region of the substrate may then be exposed and a fourth dielectric formed on the upper surface in the fourth region.

Abstract: An integrated circuit and method of forming an integrated circuit having a memory portion minimizes an amount of oxidation of nanocluster storage elements in the memory portion. A first region of the integrated circuit has non-memory devices, each having a control electrode or gate formed of a single conductive layer of material. A second region of the integrated circuit has a plurality of memory cells, each having a control electrode of at least two conductive layers of material that are positioned one overlying another. The at least two conductive layers are at substantially a same electrical potential when operational and form a single gate electrode. In one form each memory cell gate has two polysilicon layers overlying a nanocluster storage layer.

Abstract: A method for forming a portion of a semiconductor device includes: patterning gate stack layers overlying a substrate into a gate stack; implanting dopant ions to form shallow source/drain extension implant regions in the substrate adjacent to the gate stack; oxidizing the gate stack at first oxidation conditions to form an oxidation layer on sidewalls of the gate stack; and oxidizing the gate stack at second oxidation conditions to form further oxidation of the oxidation layer on sidewalls of the gate stack. The second oxidation conditions are different from the first oxidation conditions.

Abstract: A method of manufacturing a high-voltage device DDD (Double Doped Drain) ion implantation process is performed at a tilt angle in order to form a smooth junction profile. Accordingly, the intensity of an electric field can be reduced and breakdown voltage margin can be secured.

Abstract: A field effect transistor includes a buried gate pattern that is electrically isolated by being surrounded by a tunneling insulating film. The field effect transistor also includes a channel region that is floated by source and drain regions, a gate insulating film, and the tunneling insulating film. The buried gate pattern and the tunneling insulating film extend into the source and drain regions. Thus, the field effect transistor efficiently stores charge carriers in the buried gate pattern and the floating channel region.

Abstract: A non-volatile memory device includes a first sensing line, a first word line, a depletion channel region, and impurity regions. The first sensing line and the first word line are formed adjacent to each other in parallel on a substrate. The first sensing line and the first word line have a tunnel oxide layer, a first conductive pattern, a dielectric layer pattern and a second conductive pattern sequentially stacked on the substrate. The depletion channel region is formed at an upper portion of the substrate under the first sensing line. The impurity regions are formed at upper portions of the substrate exposed by the first sensing line and the first word line.

Abstract: A method for fabricating a non-volatile memory is provided. A dielectric layer, a first conductive layer, and a mask layer are formed sequentially on a substrate and then patterned to form a number of openings and floating gates. In addition, spacers are formed on the sidewalls of the openings. A source/drain region is formed in the substrate underneath each of the openings. A thermal process is performed to oxidize the substrate exposed by the opening to form an insulating layer above the source/drain region. Afterward, the mask layer is removed and an inter-gate dielectric layer is formed to cover the surface of the first conductive layer and the surface of the insulating layer. Subsequently, a second conductive layer is formed on the inter-gate dielectric layer.

Abstract: The present disclosure relates to methods of forming a flash memory device. A plurality of cells, a plurality of select transistors, and a transistor are formed over a semiconductor substrate including a cell region and a peripheral region. An insulating layer is formed on the entire surface. Metal contact holes are etched and filled with a metal contact layer. Drain contact holes are also etched and filled with a drain contact layer. The order of the metal contact layer formation and drain contact layer formation can be reversed. A single chemical mechanical polishing step is performed to remove the top portions of the metal and drain contact layers, thereby exposing the top surface of the interlayer insulating layer and simultaneously forming both the metal and drain contacts.

Abstract: A flash memory device includes a cell string having a plurality of cell transistors connected in series, and a string selection transistor and a ground selection transistor connected to both ends of the cell string, respectively, wherein the cell transistor has a channel impurity concentration higher than a channel impurity concentration of at least one of the string selection transistor and the ground selection transistor.

Abstract: A method of forming a gate insulating layer and nitrogen density measuring method thereof, by which a transistor having enhanced electric characteristics can be fabricated without employing separate ion implantation in a manner of providing parameters for enhancing perfection of the transistor via nitridation measurement. The method includes forming a first oxide layer on a silicon substrate having first to fourth regions defined thereon, patterning the first oxide layer in the first and fourth regions to have a predetermined thickness, and forming a nitride layer on the oxide layer in the third and fourth regions.

Abstract: A nonvolatile semiconductor memory according to examples of the present invention comprises a memory cell and a peripheral transistor. The memory cell has a first intergate insulating film having a multilayer structure and provided on a floating gate electrode and an isolation insulating layer. The peripheral transistor has a second intergate insulating film having a multilayer structure and provided on a first gate electrode and a second isolation insulating layer. The first and second intergate insulating films have the same structure, and a lowermost insulating layer of the first intergate insulating film on the first isolation insulating layer is thinner than a lowermost insulating layer of the second intergate insulating film on the second isolation insulating layer.

Abstract: A semiconductor device comprising a first insulating film provided on a semiconductor substrate in a cell transistor region, a first conductive film provided on the first insulating film, an inter-electrode insulating film provided on the first conductive film, a second conductive film provided on the inter-electrode insulating film and having a first metallic silicide film on a top surface thereof, first source/drain regions formed on a surface of the semiconductor substrate, a second insulating film provided on the semiconductor substrate in at least one of a selection gate transistor region and a peripheral transistor region, a third conductive film provided on the second insulating film and having a second metallic silicide film having a thickness smaller than a thickness of the first metallic silicide film on a top surface thereof, and a second source/drain regions formed on the surface of the semiconductor substrate.

Abstract: A method for fabrication a memory having a memory area and a peripheral area includes forming a first gate insulating layer with a first thickness over a substrate of a first region in the peripheral area and a second insulating layer with a second thickness over the substrate of the memory region. Thereafter, a buried diffusion region is formed in the substrate of the memory area. A charge trapping layer and a third insulating layer are formed over the substrate. A gate insulating layer is formed in the second region in the peripheral area, wherein the first thickness is greater than a second thickness after removing the charge trapping layer and third insulating layer on the first and second region in the peripheral area. A conductive layer is formed over the substrate of the memory area and the peripheral area substantially after the gate insulating layer is formed.

Abstract: A method for forming a semiconductor device includes forming a first gate electrode over a semiconductor substrate, wherein the first gate electrode comprises silicon and forming a second gate electrode over the semiconductor substrate and adjacent the first gate electrode, wherein the second gate electrode comprises silicon. Nanoclusters are present in the first gate electrode. A peripheral transistor area is formed devoid of nanoclusters.

Abstract: The present invention provides a method and apparatus for forming a double-doped polysilicon floating gate in a semiconductor memory element. The method includes forming a first dielectric layer on a semiconductor substrate and forming a floating gate above the first dielectric layer, the floating gate comprised of a first layer doped with a first type of dopant material and a second layer doped with a second type of dopant material that is opposite the first type of dopant material in the first layer. The method further includes forming a second dielectric layer above the floating gate, forming a control gate above the second dielectric layer, and forming a source and a drain in the substrate.

Abstract: The present invention is a dual-level flash memory cell design that stores 3 or more bits of information per transistor. The dual-level memory cell stores two lower bits in a first level and stores an upper bit in a second level. The lower bits are programmed, erased and read by alternate modes of operation wherein active regions operate as source and drain, and then drain and source. The upper bit is programmed and erased independent of the lower bits. However, reading of the upper bit depends upon read values of the lower bits. Additional levels are employed to store more than 3 bits of information.

Abstract: Embodiments of the present invention are directed to methods for forming non-volatile memory devices. A substrate is provided that has a cell region, a first peripheral region, and second peripheral region. A tunnel insulating layer and a preliminary blocking insulating layer are formed on the substrate in the cell region. A blocking insulating layer and a conductive layer are formed on the substrate in the cell region, the first peripheral region, and the second peripheral region. The conductive layer and the blocking insulating layer in the first and second peripheral regions are removed to expose at least a portion of the substrate in the first and second peripheral regions, while leaving the conductive layer and the blocking insulating layer in the cell region.

Abstract: A method of manufacturing a NAND flash memory device, including the steps of providing a semiconductor substrate in which a cell region and a select transistor region are defined; simultaneously forming a plurality of cell gates on the semiconductor substrate of the cell region and forming selection gates on the semiconductor substrate of the select transistor region; forming an oxide film on the entire structure and then forming a nitride film; etching the nitride film so that the nitride film remains only between the selection gates and adjacent edge cell gates; and, blanket etching the oxide film to form spacers on sidewalls of the selection gates. Accordingly, uniform threshold voltage distributions can be secured, and process margins for a spacer etch target can be secured when etching the spacers. Furthermore, the nitride film partially remains between the edge cell gates and the selection gates even after the gate spacers are etched.

Abstract: Methods and apparatus are provided. A first dielectric plug is formed in a portion of a trench that extends into a substrate of a memory device so that an upper surface of the first dielectric plug is recessed below an upper surface of the substrate. The first dielectric plug has a layer of a first dielectric material and a layer of a second dielectric material formed on the layer of the first dielectric material. A second dielectric plug of a third dielectric material is formed on the upper surface of the first dielectric plug.

Abstract: A method manufactures a non-volatile memory device on a semiconductor substrate that includes a matrix of memory cells and associated circuitry. The method includes: forming a filling dielectric layer on the whole substrate until gates of the cells and a conductive layer of the circuitry are completely covered, removing the dielectric layer until upper portions of the gates of the cells and the conductive layer are exposed, defining a plurality of gate electrodes of the transistors of the circuitry in the conductive layer, and forming source and drain regions of the transistors of the circuitry in the substrate. The method also comprises: forming spacers on side walls of gate electrodes of the transistors of the circuitry, and forming a silicide layer on the electrodes of the cells, on the gate electrodes of the transistors of the circuitry and on the source and drain regions of the transistors of said circuitry.

Abstract: Manufacturing technique for an IC device which includes forming the first conductor film over a memory cell forming region and over a peripheral circuit forming region of a semiconductor substrate, patterning the first conductive film lying over the memory cell forming region to form a first conductive pattern which serves as a first or control gate electrode of a memory cell and leaving the first conductive film over the peripheral circuit forming region, forming a second conductive film over both the memory cell forming region and the first conductive film in the peripheral circuit forming region, etching the second conductive film to form a second or memory gate electrode of the memory cell on at least a side wall of the first conductive pattern, and followed by the formation of a gate electrode of a peripheral circuit transistor by etching the first conductive film in the peripheral circuit forming region.

Abstract: A method of fabricating a non-volatile memory integrated circuit device and a non-volatile memory integrated circuit device fabricated by using the method are provided. A device isolation region is formed in a substrate to define a cell array region and a peripheral circuit region. A plurality of first and second pre-stacked gate structures is formed in the cell array region, and each has a structure in which a lower structure, a conductive pattern and a first sacrificial layer pattern are stacked. Junction regions are formed in the cell array region. Spacers are formed on side walls of the first and second pre-stacked gate structures. A second sacrificial layer pattern filling each space between the second pre-stacked gate structures is formed. The first sacrificial layer pattern is removed from each of the first and second pre-stacked gate structures.

Abstract: A fabrication method for a non-volatile memory is provided. To fabricate the non-volatile memory, a plurality of first trenches and second trenches are formed in a substrate, wherein the second trenches are disposed above the first trenches and cross over the first trenches. Then, a tunneling layer and a charge storage layer are sequentially formed on both sidewalls of each second trench. An isolation layer is filled into the first trench. Furthermore, a charge barrier layer is formed on the sidewall of the second trench, and a gate dielectric layer is formed at the bottom of the second trench. A control gate layer is filled into the second trench. Finally, two first doping regions are formed in the substrate at both sides of the control gate layer.

Abstract: A method of selectively forming a spacer on a first class of transistors and devices formed by such methods. The method can include depositing a conformal first deposition layer on a substrate with different classes of transistors situated thereon, depositing a blocking layer to at least one class of transistors, dry etching the first deposition layer, removing the blocking layer, depositing a conformal second deposition layer on the substrate, dry etching the second deposition layer and wet etching the remaining first deposition layer. Devices may include transistors of a first class with larger spacers compared to spacers of transistors of a second class.

Abstract: A non-volatile memory device having a Polysilicon Oxide Nitride Oxide Semiconductor (SONOS) structure in which a charge trap layer is separated physically in a horizontal direction, and a method of manufacturing the same. The charge trap layer that traps electric charges toward the source and the drain is physically divided. It can fundamentally prevent the charges at both sides from being moved mutually. It is therefore possible to prevent interference between charges at both sides although the cell size is reduced.

Abstract: A semiconductor device is capable of being applied with both a positive and a negative voltage to its control gate, and writing to its memory requires a low voltage. A control gate is formed on a memory unit region of a field oxide film, and an inter-layer silicon oxide film is formed on its surface. A gate oxide film for a non-volatile memory is formed on a P substrate between N type diffusion layers. The floating gate is formed on the inter-layer silicon oxide film, the field oxide film, and the gate oxide film for the non-volatile memory. Since a large coupling ratio between the control gate and the floating gate is available on the field oxide film, memory rewriting requires only a low voltage. Further, since the control gate is formed by a poly silicon film, both a positive voltage and a negative voltage can be applied to the control gate.

Abstract: An information memory device capable of reading and writing of information by mechanical operation of a floating gate layer, in which a gate insulation film has a cavity (6), and a floating gate layer (5) having two stable deflection states in the cavity (6), the state stabilized by deflecting toward the channel side of transistor, and the state stabilized by deflecting toward the gate (7) side, writing and reading of information can be made by changing the stable deflection state of the floating gate layer (5) by Coulomb interactive force between the electrons (or positive holes 8) accumulated in the floating gate layer (5) and external electric field, and by reading the channel current change based on the state of the floating gate layer (5).

Abstract: A partial oxide film (31) with well regions formed therebeneath isolates transistor formation regions in an SOI layer (3) from each other. A p-type well region (11) is formed beneath part of the partial oxide film (31) which isolates NMOS transistors from each other, and an n-type well region (12) is formed beneath part of the partial oxide film (31) which isolates PMOS transistors from each other. The p-type well region (11) and the n-type well region (12) are formed in side-by-side relation beneath part of the partial oxide film (31) which provides isolation between the NMOS and PMOS transistors. A body region is in contact with the well region (11) adjacent thereto. An interconnect layer formed on an interlayer insulation film (4) is electrically connected to the body region through a body contact provided in the interlayer insulation film (4). A semiconductor device having an SOI structure reduces a floating-substrate effect.

Abstract: A method of fabricating a semiconductor device includes forming on a semiconductor substrate a gate electrode with a gate insulating film being interposed between the substrate and the electrode, forming an insulating film for element isolation protruding from a surface of the semiconductor substrate, forming an oxide film on the surface of the semiconductor substrate with the gate electrode and the element isolation insulating film having been formed, removing the oxide film in a region in which a self-aligned contact hole is to be formed while using a resist pattern for removing the oxide film formed in a region in which the self-aligned contact hole is formed, and etching a part of the element isolation insulating film protruding from the surface of the semiconductor substrate so that said part is substantially on a level with the surface of the semiconductor substrate, while using the resist pattern for removing the oxide film formed in the region in which the self-aligned contact hole is formed.

Abstract: A non-volatile semiconductor memory device includes a semiconductor substrate, a memory cell array formed on the semiconductor substrate, and including a first gate insulator having a first thickness. The device further includes a high-voltage transistor circuit formed on the semiconductor substrate, and including a second gate insulator having a second thickness greater than the first thickness, and a peripheral circuit formed on the semiconductor substrate, and including the second gate insulator.

Abstract: An electrically erasable programmable read-only memory (“CMOS NON-VOLATILE MEMORY”) cell is fabricated using standard CMOS fabrication processes. First and second polysilicon gates are patterned over an active area of the cell between source and drain regions. Thermal oxide is grown on the polysilicon gates to provide an isolating layer. Silicon nitride is deposited between the first and second polysilicon gates to form a lateral programming layer.

Abstract: A method of fabricating a semiconductor device is described. A substrate having a memory cell region and a high voltage circuit region are provided. First and second source/drain regions are formed in the substrate within these two regions. A silicon oxide layer, a first conductive layer and a top layer are sequentially formed over the substrate. A floating gate is defined in the memory cell region and the top layer and the first conductive layer of the high voltage circuit region are removed. The exposed silicon oxide layer is thickened. Thereafter, the top layer is removed and then a barrier layer is formed on the exposed surface of the floating gate. A second conductor layer is formed over the substrate, and then a gate is defined in the high voltage circuit region and a control gate is defined in the memory cell region.

Abstract: A semiconductor device has a gate contact structure, including a semiconductor substrate, a polycrystalline silicon layer used as a gate electrode of a transistor, a middle conductive layer, a top metal layer having an opening exposing the polycrystalline silicon layer, and a contact plug directly contacting the polycrystalline silicon layer through the opening.

Abstract: A method of fabricating a non-volatile memory cell on a semiconductor substrate is disclosed. An area of a first region of the semiconductor substrate designated for a layer of floating polysilicon is blocked while a second region of the semiconductor substrate designated for a layer of non-floating polysilicon is exposed. Exposed regions of the semiconductor substrate are doped with charges.

Abstract: A semiconductor device includes: a lower hydrogen-barrier film; a capacitor formed on the lower hydrogen-barrier film and including a lower electrode, a capacitive insulating film, and an upper electrode; an interlayer dielectric film formed so as to cover the periphery of the capacitor; and an upper hydrogen-barrier film covering the top and lateral portions of the capacitor. An opening, which exposes the lower hydrogen-barrier film where the lower hydrogen-barrier film is located around the capacitor, and which is tapered and flares upward, is formed in the interlayer dielectric film, and the upper hydrogen-barrier film is formed along the lateral and bottom faces of the opening, and is in contact with the lower hydrogen-barrier film in the opening.

Abstract: A nonvolatile memory cell according to the present invention comprises a bottom conductor, a semiconductor pillar, and a top conductor. The semiconductor pillar comprises a junction diode, including a bottom heavily doped region, a middle intrinsic or lightly doped region, and a top heavily doped region, wherein the conductivity types of the top and bottom heavily doped region are opposite. The junction diode is vertically oriented and is of reduced height, between about 500 angstroms and about 3500 angstroms. A monolithic three dimensional memory array of such cells can be formed comprising multiple memory levels, the levels monolithically formed above one another.

Abstract: According to the embodiments to the present disclosure, the process of making a dual strained channel semiconductor device includes integrating strained Si and compressed SiGe with trench isolation for achieving a simultaneous NMOS and PMOS performance enhancement. As described herein, the integration of NMOS and PMOS can be implemented in several ways to achieve NMOS and PMOS channels compatible with shallow trench isolation.

Abstract: NAND memory arrays and methods are provided. A plurality of first gate stacks is formed on a first dielectric layer that is formed on a substrate of a NAND memory array. The first dielectric layer and the plurality of first gate stacks formed thereon form a NAND string of memory cells of the memory array. A second gate stack is formed on a second dielectric layer that is formed on the substrate adjacent the first dielectric layer. The second dielectric layer with the second gate stack formed thereon forms a drain select gate adjacent an end of the NAND string. The second dielectric layer is thicker than the first dielectric layer.

Abstract: A method of fabricating a non-volatile memory is provided. In the fabricating method, a plurality of stack gate structures is formed on a substrate and a plurality of doped regions is formed in the substrate beside the stack gate structures. Then, a plurality of spacers is formed on the sidewalls of the stack gate structures. After that, a plurality of conductive pad layers is formed on the exposed doped regions. By forming the conductive pad layers, the resistance of the doped region in each memory cell can be reduced.

Abstract: Under one aspect, a field effect device includes a gate, a source, and a drain, with a conductive channel between the source and the drain; and a nanotube switch having a corresponding control terminal, said nanotube switch being positioned to control electrical conduction through said conductive channel. Under another aspect, a field effect device includes a gate having a corresponding gate terminal; a source having a corresponding source terminal; a drain having a corresponding drain terminal; a control terminal; and a nanotube switching element positioned between one of the gate, source, and drain and its corresponding terminal and switchable, in response to electrical stimuli at the control terminal and at least one of the gate, source, and drain terminals, between a first non-volatile state that enables current flow between the source and the drain and a second non-volatile state that disables current flow between the source and the drain.

Abstract: Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within wells defining the second type standard Vt devices, and each of the first and second type low Vt devices. Wells that define the locations of second type standard Vt devices are masked, and a second voltage threshold implant adjustment is performed to the wells defining the first type standard Vt devices, and each of the first and second type low Vt devices. Doped polysilicon gate stacks are then formed over the wells. Performance characteristics and control of each device Vt is controlled by regulating at least one of the first and second voltage threshold implant adjustments, and the polysilicon gate stack doping.

Abstract: Methods of forming integrated circuit devices are provided. A first mask layer is formed overlying a first portion of a semiconductor substrate. The first mask layer further overlies a second mask layer overlying a second portion of the semiconductor substrate. The first mask layer overlying the first portion of the semiconductor substrate is patterned to define areas for removal of one or more layers of material interposed between the semiconductor substrate and the first mask layer. Portions of the one or more layers of material exposed by the patterned first mask layer are removed to define elements of the integrated circuit device overlying the first portion of the semiconductor substrate.

Abstract: Methods and apparatus for providing a memory array fabrication process that concurrently forms memory array elements and peripheral circuitry. The invention relates to a method for fabricating memory arrays using a process that concurrently forms memory array elements and peripheral circuitry and results in a reduction in pitch.

Abstract: A method is provided for forming at least three devices with different gate oxide thicknesses and different associated operating voltages, in the same integrated circuit device. The method includes forming a plurality of gate oxides with different thicknesses in high voltage and low voltage areas in the same integrated circuit device. A dry etching operation is used to remove the relatively thick gate oxide from the high voltage area using photoresist masking of the low voltage area and a hard mask in the high voltage area, to mask the gate oxide films. A wet etching procedure is then used to remove the gate oxide film from the low voltage areas. The hard mask may be formed over a polysilicon structure.