Abstract: A device includes a semiconductor substrate, source and drain regions in the semiconductor substrate, a channel region in the semiconductor substrate between the source and drain regions through which charge carriers flow during operation from the source region to the drain region, and a drift region in the semiconductor substrate, on which the drain region is disposed, and through which the charge carriers drift under an electric field arising from application of a bias voltage between the source and drain regions. A PN junction along the drift region includes a first section at the drain region and a second section not at the drain region. The drift region has a lateral profile that varies such that the first section of the PN junction is shallower than the second section of the PN junction.

Abstract: A semiconductor device is provided. The device includes a semiconductor substrate, first and second projections extending upwardly from the substrate, the projections having respective first and second channel regions therein, and a first gate structure engaging the first projection adjacent the first channel region. The first gate structure includes a first dielectric material over the first channel region, a first opening over the first dielectric material and the first channel region, and a pure first metal with an n-type work function value conformally deposited in the first opening. The device also includes a second gate structure engaging the second projection adjacent the second channel region. The second gate structure includes a second dielectric material over the second channel region, a second opening over the second dielectric material and the second channel region, and a pure second metal with a p-type work function value conformally deposited in the second opening.

Abstract: A nonvolatile semiconductor memory transistor included in a nonvolatile semiconductor memory includes an island-shaped semiconductor having a source region, a channel region, and a drain region formed in this order from the substrate side, a hollow pillar-shaped floating gate arranged so as to surround the outer periphery of the channel region in such a manner that a tunnel insulating film is interposed between the floating gate and the channel region, and a hollow pillar-shaped control gate arranged so as to surround the outer periphery of the floating gate in such a manner that an inter-polysilicon insulating film is interposed between the control gate and the floating gate. The inter-polysilicon insulating film is arranged so as to be interposed between the floating gate and the upper, lower, and inner side surfaces of the control gate.

Abstract: Forming a photoresist on a region other than a region on a trench gate electrode for a mask, a third gate insulating film on the trench gate electrode is etched and removed. After that, a non-doped polycrystalline silicon layer is formed on second and third gate insulating films and also on the trench gate electrode, and, N-type and P-type high concentration impurities are introduced by an ion implantation with the use of separate masks on the polycrystalline silicon layer of NMOS transistors and PMOS transistors with a low breakdown voltage and a high breakdown voltage. Then, a second gate electrode is formed by anisotropic etching. With the steps as described above, a first gate electrode inside the trench and the second gate electrode to be used in the lateral MOS transistor are laminated, to thereby reduce fluctuations due to the etching.

Abstract: A super-junction trench MOSFET is disclosed for high voltage device by applying a first doped column region of first conductivity type between a pair of second doped column regions of second conductivity type adjacent to sidewalls of a pair of deep trenches with buried voids in each unit cell for super-junction. Meanwhile, at least one trenched gate and multiple trenched source-body contacts are formed in each unit cell between the pair of deep trenches.

Abstract: A method for forming an impurity region of a vertical transistor includes forming an impurity ion junction region within a semiconductor substrate, and forming a trench by etching the semiconductor substrate in which the impurity ion junction region is formed. The etching process is performed to remove a portion of the impurity ion junction region, so that a remaining portion of the impurity ion junction region is exposed to a lower side wall of the trench to serve as a buried bit line junction region.

Abstract: A nonvolatile semiconductor memory device includes a plurality of memory strings, each of which has a plurality of electrically rewritable memory cells connected in series; and select transistors, one of which is connected to each of ends of each of the memory strings. Each of the memory strings is provided with a first semiconductor layer having a pair of columnar portions extending in a perpendicular direction with respect to a substrate, and a joining portion formed so as to join lower ends of the pair of columnar portions; a charge storage layer formed so as to surround a side surface of the columnar portions; and a first conductive layer formed so as to surround the side surface of the columnar portions and the charge storage layer, and configured to function as a control electrode of the memory cells.

Abstract: Some embodiments include memory arrays. The memory arrays may have digit lines under vertically-oriented transistors, with the digit lines interconnecting transistors along columns of the array. Each individual transistor may be directly over only a single digit line, with the single digit line being entirely composed of one or more metal-containing materials. The digit lines can be over a deck, and electrically insulative regions can be directly between the digit lines and the deck. Some embodiments include methods of forming memory arrays. A plurality of linear segments of silicon-containing material may be formed to extend upwardly from a base of the silicon-containing material. The base may be etched to form silicon-containing footings under the linear segments, and the footings may be converted into metal silicide. The linear segments may be patterned into a plurality of vertically-oriented transistor pedestals that extend upwardly from the metal silicide footings.

Abstract: A semiconductor device with a semiconductor body and method for its production is disclosed. The semiconductor body includes drift zones of epitaxially grown semiconductor material of a first conduction type. The semiconductor body further includes charge compensation zones of a second conduction type complementing the first conduction type, which are arranged laterally adjacent to the drift zones. The charge compensation zones are provided with a laterally limited charge compensation zone doping, which is introduced into the epitaxially grown semiconductor material. The epitaxially grown semiconductor material includes 20 to 80 atomic % of the doping material of the drift zones and a doping material balance of 80 to 20 atomic % introduced by ion implantation and diffusion.

Abstract: In a SiC-based MISFET and a manufacturing process thereof, after the introduction of an impurity, extremely-high-temperature activation annealing is required. Accordingly, it is difficult to frequently use a self-alignment process as performed in a silicon-based MISFET manufacturing process. This results in the problem that, to control the characteristics of a device, a high-accuracy alignment technique is indispensable. In accordance with the present invention, in a semiconductor device such as a SiC-based vertical power MISFET using a silicon-carbide-based semiconductor substrate and a manufacturing method thereof, a channel region, a source region, and a gate structure are formed in mutually self-aligned relation.

Abstract: A method includes forming a gate structure over a semiconductor substrate. The gate structure defines a channel region in the semiconductor substrate. Trenches are formed in the semiconductor substrate, and the trenches are interposed by the channel region. A first semiconductor layer is epitaxially grown in the trenches, and the first semiconductor layer has a first dopant with a first dopant concentration. A second semiconductor layer is epitaxially grown over the first semiconductor layer, and the second semiconductor layer has a second dopant with a second dopant concentration. The second dopant has an electrical carrier type opposite to an electrical carrier type of the first dopant.

Abstract: Systems and methods of fabricating Wafer Level Chip Scale Packaging (WLCSP) devices with transistors having source, drain and gate contacts on one side of the transistor while still having excellent electrical performance with low drain-to-source resistance RDS(on) include using a two-metal drain contact technique. The RDS(on) is further improved by using a through-silicon-via (TSV) technique to form a drain contact or by using a copper layer closely connected to the drain drift.

Abstract: Various embodiments include methods and apparatuses, such as memory cells formed on two or more stacked decks. A method includes forming a first deck with first levels of conductor material and first levels of dielectric material over a substrate. Each level of the conductor material is separated from an adjacent level of conductor material by at least one of the first levels of dielectric material. A first opening is formed through the first levels of conductor material and dielectric material. A sacrificial material is formed at least partially filling the first opening. A second deck is formed over the first deck. The second deck has second levels of conductor material and second levels of dielectric material with each level of the conductor material being separated from an adjacent level of conductor material by at least one of the second levels of dielectric material. Additional apparatuses and methods are disclosed.

Abstract: A semiconductor device includes a semiconductor pattern on a substrate, gate structures on sidewalls of the semiconductor pattern, the gate structures being spaced apart from one another, insulating interlayers among the gate structures, wherein an uppermost insulating interlayer is lower than an upper face of the semiconductor pattern, a common source line contacting the substrate and protruding above the uppermost insulating interlayer, an etch stop layer pattern on the semiconductor pattern and on the common source line wherein the common source line protrudes above the uppermost insulating interlayer, an additional insulating interlayer on the uppermost insulating interlayer, and contact plugs extending through the additional insulating interlayer so as to make contact with the semiconductor pattern and the common source line, respectively.

Abstract: Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.

Abstract: A trench semiconductor power device having active cells under gate metal pad to increase total active area for lowering on-resistance is disclosed. The gate metal pad is not only for gate wire bonding but also for active cells disposition. Therefore, the device die can be shrunk so that the number of devices per wafer is increased for die cost reduction. Moreover, the device can be packaged into smaller type package for further cost reduction.

Abstract: A vertical semiconductor device and a method of making a vertical semiconductor device include a first semiconductor pattern formed on a substrate and a first gate structure formed on a sidewall of the first semiconductor pattern. A second semiconductor pattern is formed on the first semiconductor pattern. A plurality of insulating interlayer patterns is formed on sidewalls of the second semiconductor pattern. The insulating interlayer patterns are spaced apart from each other to define grooves between the insulating interlayer patterns. The plurality of second gate structures is disposed in the grooves, respectively.

Abstract: A method for producing a semiconductor device includes preparing a structure having a substrate, a planar semiconductor layer and a columnar semiconductor layer, forming a second drain/source region in the upper part of the columnar semiconductor layer, forming a contact stopper film and a contact interlayer film, and forming a contact layer on the second drain/source region. The step for forming the contact layer includes forming a pattern and etching the contact interlayer film to the contact stopper film using the pattern to form a contact hole for the contact layer and removing the contact stopper film remaining at the bottom of the contact hole by etching. The projection of the bottom surface of the contact hole onto the substrate is within the circumference of the projected profile of the contact stopper film formed on the top and side surface of the columnar semiconductor layer onto the substrate.

Abstract: A method for forming a trench structure is provided for a semiconductor and/or memory device, such as an DRAM device. In one embodiment, the method for forming a trench structure includes forming a trench in a semiconductor substrate, and exposing the sidewalls of the trench to an arsenic-containing gas to adsorb an arsenic containing layer on the sidewalls of the trench. A material layer is then deposited on the sidewalls of the trench to encapsulate the arsenic-containing layer between the material layer and sidewalls of the trench.

Abstract: It is intended to provide a semiconductor device including a MOS transistor, comprising: a semiconductor pillar; a bottom doped region formed in contact with a lower part of the semiconductor pillar; a first gate formed around a sidewall of the semiconductor pillar through a first dielectric film therebetween; and a top doped region formed so as to at least partially overlap a top surface of the semiconductor pillar, wherein the top doped region has a top surface having an area greater than that of the top surface of the semiconductor pillar.

Abstract: The present disclosure relates to a device and method for strain inducing or high mobility channel replacement in a semiconductor device. The semiconductor device is configured to control current from a source to a drain through a channel region by use of a gate. A strain inducing or high mobility layer produced in the channel region between the source and drain can result in better device performance compared to Si, faster devices, faster data transmission, and is fully compatible with the current semiconductor manufacturing infrastructure.

Abstract: An electronic apparatus includes a semiconductor substrate and first and second transistors disposed in the semiconductor substrate. The first transistor includes a channel region and a drain region adjacent the channel region. The second transistor includes a channel region, a false drain region adjacent the channel region, and a drain region electrically coupled to the channel region by a drift region such that the second transistor is configured for operation at a higher voltage level than the first transistor. The respective channel regions of the first and second transistors have a common configuration characteristic.

Abstract: Embodiments of the present invention relate to an improved package for a bi-directional and reverse blocking battery switch. According to one embodiment, two switches are oriented side-by-side, rather than end-to-end, in a die package. This configuration reduces the total switch resistance for a given die area, often reducing the resistance enough to avoid the use of backmetal in order to meet resistance specifications. Elimination of backmetal reduces the overall cost of the die package and removes the potential failure modes associated with the manufacture of backmetal. Embodiments of the present invention may also allow for more pin connections and an increased pin pitch. This results in redundant connections for higher current connections, thereby reducing electrical and thermal resistance and minimizing the costs of manufacture or implementation of the die package.

Abstract: A method of manufacturing a semiconductor device comprises forming memory cells on a memory cell region, alternately forming a sacrificial layer and an insulating interlayer on a connection region for providing wirings configured to electrically connect the memory cells, forming an etching mask pattern including etching mask pattern elements on a top sacrificial layer, forming blocking sidewalls on either sidewalls of each of the etching mask pattern element, forming a first photoresist pattern selectively exposing a first blocking sidewall furthermost from the memory cell region and covering the other blocking sidewalls, etching the exposed top sacrificial layer and an insulating interlayer to expose a second sacrificial layer, forming a second photoresist pattern by laterally removing the first photoresist pattern to the extent that a second blocking sidewall is exposed, and etching the exposed top and second sacrificial layers and the insulating interlayers to form a staircase shaped side edge portion.

Abstract: The present invention relates to a semiconductor device (1) comprising: at least a nanowire (2) configured to comprise: at least a source region (3) comprising a corresponding source semiconductor material, at least a drain region (4) comprising a corresponding drain semiconductor material and at least a channel region (5) comprising a corresponding channel semiconductor material, the channel region (5) being arranged between the source region (3) and the drain region (4), at least a gate electrode (6) that is arranged relative to the nanowire (2) to circumferentially surround at least a part of the channel region (5), and at least a strain gate (7) that is arranged relative to the nanowire (2) to circumferentially surround at least a part of a segment of the nanowire (2), the strain gate (7) being configured to apply a strain to the nanowire segment (8), thereby to facilitate at least an alteration of the energy bands corresponding to the source region (3) relative to the energy bands corresponding to the ch

Abstract: An integrated circuit device includes a plurality of pillars protruding from a substrate in a first direction. Each of the pillars includes source/drain regions in opposite ends thereof and a channel region extending between the source/drain regions. A plurality of conductive bit lines extends on the substrate adjacent the pillars in a second direction substantially perpendicular to the first direction. A plurality of conductive shield lines extends on the substrate in the second direction such that each of the shield lines extends between adjacent ones of the bit lines. Related fabrication methods are also discussed.

Abstract: A staggered column superjunction semiconductor device may include a cell region having one or more device cells. One or more device cells in the cell region include a semiconductor substrate configured to act as a drain and a semiconductor layer formed on the substrate. A first doped column may be formed in the semiconductor layer to a first depth and a second doped column may be formed in the semiconductor layer to a second depth. The first depth is greater than the second depth. The first and second columns are doped with dopants of a same second conductivity type and extend along a portion of a thickness of the semiconductor layer and are separated from each by a portion of the semiconductor layer.

Abstract: A device includes a semiconductor substrate, and a channel region of a transistor over the semiconductor substrate. The channel region includes a semiconductor material. An air gap is disposed under and aligned to the channel region, with a bottom surface of the channel region exposed to the air gap. Insulation regions are disposed on opposite sides of the air gap, wherein a bottom surface of the channel region is higher than top surfaces of the insulation regions. A gate dielectric of the transistor is disposed on a top surface and sidewalls of the channel region. A gate electrode of the transistor is over the gate dielectric.

Abstract: A Vertical Multiple Implanted Silicon Carbide Power MOSFET (VMIMOSFET) includes a first conductivity semiconductor substrate, a first conductivity semiconductor drift layer on the top of the substrate, a multitude of second conductivity layers implanted in the drift layer. The body layer is where the channel is formed. A first conductivity source layer is interspaced appropriately inside of the second conductivity layers. A gate oxide of a certain thickness and another oxide of a different thickness, a greater thickness than the gate oxide, placed in between the body layers but in such way that its shape does not distort the gate oxide in the channel. A charge compensated body layer of the second conductivity formed outside of the channel region and only at specific high electric field locations in the structure. The device and the manufacturing method deliver a power SiC MOSFET with increased frequency of operation and reduced switching losses.

Abstract: A method for fabricating a semiconductor device includes etching a substrate to form a plurality of bodies isolated by a first trench, forming a buried bit line gap-filling a portion of the first trench, etching the top portions of the bodies to form a plurality of pillars isolated by a plurality of second trenches extending across the first trench, forming a passivation layer gap-filling a portion of the second trenches, forming an isolation layer that divides each of the second trenches into isolation trenches over the passivation layer, and filling a portion of the isolation trenches to form a buried word line extending in a direction crossing over the buried bit line.

Abstract: A semiconductor device includes a first conductive-type semiconductor layer, a second conductive-type body region formed in a surficial portion of the semiconductor layer, a first conductive-type source region formed in a surficial portion of the body region, a gate insulating film provided on the semiconductor layer and containing nitrogen atoms, the gate insulating film including a first portion in contact with the semiconductor layer outside the body region, a second portion in contact with the body region, and a third portion in contact with the source region, and a gate electrode provided on the gate insulating film in an area extending across the semiconductor layer outside the body region, the body region, and the source region. The third portion of the gate insulating film has a thickness greater than the thickness of the first portion and the thickness of the second portion.

Abstract: In a vertical semiconductor device including a channel in an opening, a semiconductor device whose high-frequency characteristics can be improved and a method for producing the semiconductor device are provided. The semiconductor device includes n-type GaN-based drift layer 4/p-type GaN-based barrier layer 6/n-type GaN-based contact layer 7. An opening 28 extends from a top layer and reaches the n-type GaN-based drift layer. The semiconductor device includes a regrown layer 27 located so as to cover the opening, the regrown layer 27 including an electron drift layer 22 and an electron supply layer 26, a source electrode S, a drain electrode D, and a gate electrode G located on the regrown layer. Assuming that the source electrode serving as one electrode and the drain electrode serving as the other electrode constitute a capacitor, the semiconductor device includes a capacitance-decreasing structure that decreases the capacitance of the capacitor.

Abstract: A non-volatile semiconductor storage device according to one embodiment of the present application has a memory cell array that includes at least one memory string, a first select transistor, and a second select transistor on a substrate in a lattice form. The first select transistor is electrically connected to a first end of the memory string. The second select transistor is electrically connected to a second end of the memory string. The memory string includes a columnar portion. Multiple memory cells are formed in the columnar portion by multiple conductive layers, multiple insulating layers, a first insulating layer, a charge accumulation layer, a second insulating layer, and a memory channel layer, and are serially connected. The memory channel layer comprises silicon germanium doped with phosphorus.

Abstract: A capacitor-less memory cell, memory device, system and process of forming the capacitor-less memory cell includes forming the memory cell in an active area of a substantially physically isolated portion of the bulk semiconductor substrate. A pass transistor is formed on the active area for coupling with a word line. The capacitor-less memory cell further includes a read/write enable transistor vertically configured along at least one vertical side of the active area and operable during a reading of a logic state with the logic state being stored as charge in a floating body area of the active area, causing different determinable threshold voltages for the pass transistor.

Abstract: Disclosed are a semiconductor device and a method for producing a semiconductor device. A MOSFET may have a source region, a drift region and a drain region of a first conductivity type, a body region of a second conductivity type disposed between the source region and the drift region, and a gate electrode disposed adjacent to said body region. The gate electrode may be isolated from the body region by a dielectric, and have a source electrode contacting the source region and the body region. A self-locking JFET, associated with the MOSFET, may have a channel region of the first conductivity type, the channel region connected between the source electrode and the drift region, and coupled to and adjacent the body region.

Abstract: A semiconductor device which includes a buried layer having a first dopant type disposed in a substrate. The semiconductor device further includes a second layer having the first dopant type over the buried layer, wherein a dopant concentration of the buried layer is higher than a dopant concentration of the second layer. The semiconductor device further includes a first well of a second dopant type disposed in the second layer and a first source region of the first dopant type disposed in the first well and connected to a source contact on one side. The semiconductor device further includes a gate disposed on top of the well and the second layer and a metal electrode extending from the buried layer to a drain contact, wherein the metal electrode is insulated from the second layer and the first well by an insulation layer.

Abstract: A process for fabricating a field-effect transistor device (20) implemented on a network of vertical nanowires (24), includes: producing a source electrode (26) and a drain electrode (30) at each end of each nanowire (24) symmetrically relative to the gate electrode of each elementary transistor implemented on a nanowire; creating a gate electrode by depositing a layer (38) of conductive material around a layer (36) of dielectric material that surrounds a portion of each nanowire (24), a single conductive layer (38) being used for all of the nanowires and the thickness of the conductive layer corresponding to the gate length of the transistor device; and insulating each electrode with a planar layer (32, 34) of a dielectric material in order to form a nanoscale gate and in order to insulate the contacts of each elementary transistor between the gate and the source and the gate and the drain.

Abstract: A first conductive layer and an underlying charge storage layer are patterned to form a control gate in an NVM region. A first dielectric layer is formed over the control gate. A sacrificial layer is formed over the first dielectric layer and planarized. A patterned masking layer is formed over the sacrificial layer which includes a first portion which defines a select gate location laterally adjacent the control gate in the NVM region and a second portion which defines a logic gate in a logic region. Exposed portions of the sacrificial layer are removed such that a first portion remains at the select gate location. A second dielectric layer is formed over the first portion and planarized to expose the first portion. The first portion is removed to result in an opening at the select gate location. A gate dielectric layer and a select gate are formed in the opening.

Abstract: A semiconductor device includes a semiconductor body having a first surface defining a vertical direction and a source metallization arranged on the first surface. In a vertical cross-section the semiconductor body further includes: a drift region of a first conductivity type; at least two compensation regions of a second conductivity type each of which forms a pn-junction with the drift region and is in low resistive electric connection with the source metallization; a drain region of the first conductivity type having a maximum doping concentration higher than a maximum doping concentration of the drift region, and a third semiconductor layer of the first conductivity type arranged between the drift region and the drain region and includes at least one of a floating field plate and a floating semiconductor region of the second conductivity type forming a pn-junction with the third semiconductor layer.

Abstract: A method for fabricating a non-volatile memory device includes forming a stacked structure where a plurality of inter-layer dielectric layers and a plurality of second sacrificial layers are alternately stacked over the first gate electrode layer, forming a first channel hole that exposes the first sacrificial layer by penetrating through the stacked structure, forming a second channel hole by removing the exposed first sacrificial layer, forming an oxide layer by oxidizing a surface of the first gate electrode layer exposed through the first and second channel holes, forming a channel layer in the first and second channel holes, and forming second gate electrode layers in spaces from which the second sacrificial layers are removed, wherein a memory layer is interposed between the channel layer and the second gate electrode layer.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a stacked body, a second insulating layer, a select gate, a memory hole, a memory film, a channel body, a first semiconductor layer, and a second semiconductor layer. The select gate is provided on the second insulating layer. The memory film is provided on an inner wall of the memory hole. The channel body is provided inside the memory film. The first semiconductor layer is provided on an upper surface of the channel body. The second semiconductor layer is provided on the first semiconductor layer. The first semiconductor layer contains silicon germanium. The second semiconductor layer contains silicon germanium doped with a first impurity. A boundary between the first semiconductor layer and the second semiconductor layer is provided above a position of an upper end of the select gate.

Abstract: In one embodiment, a manufacturing method of a semiconductor memory device is disclosed. The method can include forming a stacked body on a substrate. The stacked body includes first silicon films containing impurities and having a concentration difference of the impurities provided among different layers, and non-doped second silicon films each provided between the first silicon films. The method can include forming a hole in the stacked body. The method can include removing the second silicon films by etching through the hole and forming an inter-electrode space between the first silicon films. The method can include forming a memory film including a charge storage film on a side wall of the hole and also forming at least a part of the memory film in the inter-electrode space.

Abstract: Embodiments described include straining transistor quantum well (QW) channel regions with metal source/drains, and conformal regrowth source/drains to impart a uni-axial strain in a MOS channel region. Removed portions of a channel layer may be filled with a junction material having a lattice spacing different than that of the channel material to causes a uni-axial strain in the channel, in addition to a bi-axial strain caused in the channel layer by a top barrier layer and a bottom buffer layer of the quantum well.

Abstract: Disclosed herein is a method of manufacturing a semiconductor device. The method comprises forming a first silicon film on a semiconductor substrate, forming a second silicon film on the first silicon film, forming a third silicon film on the second silicon film, and forming a first diffusion barrier film on the third silicon film. The method further comprises performing a thermal treatment to diffuse an impurity included in the second silicon film into at least the first silicon film and the semiconductor substrate, respectively.

Abstract: A method for manufacturing compatible vertical double diffused metal oxide semiconductor (VDMOS) transistor and lateral double diffused metal oxide semiconductor (LDMOS) transistor includes: providing a substrate having an LDMOS transistor region and a VDMOS transistor region; forming an N-buried region in the substrate; forming an epitaxial layer on the N-buried layer region; forming isolation regions in the LDMOS transistor region and the VDMOS transistor region; forming a drift region in the LDMOS transistor region; forming gates in the LDMOS transistor region and the VDMOS transistor region; forming PBODY regions in the LDMOS transistor region and the VDMOS transistor region; forming an N-type GRADE region in the LDMOS transistor region; forming an NSINK region in the VDMOS transistor region, where the NSINK region is in contact with the N-buried layer region; forming sources and drains in the LDMOS transistor region and the VDMOS transistor region; and forming a P+ region in the LDMOS transistor region,

Abstract: Disclosed is a method of forming a semiconductor device with drift regions of a first doping type and compensation regions of a second doping type, and a semiconductor device with drift regions of a first doping type and compensation regions of a second doping type.

Abstract: A semiconductor device includes a trench extending from a surface of a P-base layer to a surface of a P-well layer. The trench has a trench end portion defined in the surface of the P-well layer and in a direction in which the trench extends. The trench has first and second regions. The first region extends from the trench end portion to get into the surface of the P-base layer near a boundary between the P-base layer and the P-well layer. The second region extends in the surface of the P-base layer from an end portion of the first region. A trench width is greater in the first region than in the second region.

Abstract: In according with the present invention, a semiconductor device is formed as follows. A contact insulation layer is deposited on the top surface of said silicon layer. A contact mask is applied and following with a dry oxide etching to remove the contact insulation layer from contact open areas. The silicon layer is implanted with a source dopant through the contact open areas and the source dopant is diffused to form source regions, thereby a source mask is saved. A dry silicon etch is carried out to form trenched source-body contacts in the contact open areas, penetrating through the source regions and extending into the body regions.

Abstract: An integrated circuit (25) formed at a semiconducting surface of a substrate including a common p-layer (38) includes functional circuitry (24) formed on the p-layer (38) including a plurality of terminals (IN, OUT, I/O) coupled to the functional circuitry (24). At least one ESD protection cell (30; in more detail 200) is connected to at least one of the plurality of terminals of the functional circuitry (24). The protection cell includes at least a first Nwell (37) formed in the p-layer (38), a p-doped diffusion (36) within the first Nwell (37) to form at least one Nwell diode comprising an anode (37) and a cathode (36). An NMOS transistor 200 is formed in or on the p-layer (38) comprising a n+ source (43), n+ drain (44) and a channel region comprising a p-region (41) between the source and drain, and a gate electrode (45) on a gate dielectric (46) on the channel region.

Abstract: A nonvolatile memory device comprises a channel pattern, a first interlayer dielectric film and a second interlayer dielectric film spaced apart from each other and stacked over each other, a gate pattern disposed between the first interlayer dielectric film and the second interlayer dielectric film, a trap layer disposed between the gate pattern and the channel pattern and a charge spreading inhibition layer disposed between the channel pattern and the first interlayer dielectric film and between the channel pattern and the second interlayer dielectric film. The charge spreading inhibition layer may include charges inside or on its surface. The charge spreading inhibition layer includes at least one of a metal oxide film or a metal nitride film or a metal oxynitride film having a greater dielectric constant than a silicon oxide film.