Abstract: A threshold adjusting semiconductor material, such as a silicon/germanium alloy, may be provided selectively for one type of transistors on the basis of enhanced deposition uniformity. For this purpose, the semiconductor alloy may be deposited on the active regions of any transistors and may subsequently be patterned on the basis of a highly controllable patterning regime. Consequently, threshold variability may be reduced.

Abstract: A semiconductor device includes a semiconductor region, a source region, a drain region, a source extension region a drain extension region, a first gate insulation film, a second gate insulation film, and a gate electrode. The source region, drain region, source extension region and drain extension region are formed in a surface portion of the semiconductor region. The first gate insulation film is formed on the semiconductor region between the source extension region and the drain extension region. The first gate insulation film is formed of a silicon oxide film or a silicon oxynitride film having a nitrogen concentration of 15 atomic % or less. The second gate insulation film is formed on the first gate insulation film and contains nitrogen at a concentration of between 20 atomic % and 57 atomic %. The gate electrode is formed on the second gate insulation film.

Abstract: Semiconductor structures are disclosed that have embedded stressor elements therein. The disclosed structures include at least one FET gate stack located on an upper surface of a semiconductor substrate. The at least one FET gate stack includes source and drain extension regions located within the semiconductor substrate at a footprint of the at least one FET gate stack. A device channel is also present between the source and drain extension regions and beneath the at least one gate stack. The structure further includes embedded stressor elements located on opposite sides of the at least one FET gate stack and within the semiconductor substrate. Each of the embedded stressor elements includes a lower layer of a first epitaxy doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, and an upper layer of a second epitaxy doped semiconductor material located atop the lower layer.

Abstract: A transistor is provided that includes a silicon layer including a source region and a drain region, a gate stack disposed on the silicon layer between the source region and the drain region, and a sidewall spacer disposed on sidewalls of the gate stack. The gate stack includes a first layer of high dielectric constant material, a second layer comprising a metal or metal alloy, and a third layer comprising silicon or polysilicon. The sidewall spacer includes a high dielectric constant material and covers the sidewalls of at least the second and third layers of the gate stack. Also provided is a method for fabricating such a transistor.

Abstract: The field effect device comprises a sacrificial gate electrode having side walls covered by lateral spacers formed on a semiconductor material film. The source/drain electrodes are formed in the semiconductor material film and are arranged on each side of the gate electrode. A diffusion barrier element is implanted through the void left by the sacrificial gate so as to form a modified diffusion area underneath the lateral spacers. The modified diffusion area is an area where the mobility of the doping impurities is reduced compared with the source/drain electrodes.

Abstract: A semiconductor device manufacturing method includes the steps of: forming a transistor on a surface side of a silicon layer of a silicon-on-insulator substrate, the silicon-on-insulator substrate being formed by laminating a substrate, an insulating layer, and the silicon layer; forming a first insulating film covering the transistor and a wiring section including a part electrically connected to the transistor on the silicon-on-insulator substrate; measuring a threshold voltage of the transistor through the wiring section; forming a supporting substrate on a surface of the first insulating film with a second insulating film interposed between the supporting substrate and the first insulating film; removing at least a part of the substrate and the insulating layer on a back side of the silicon-on-insulator substrate; and adjusting the threshold voltage of the transistor on a basis of the measured threshold voltage.

Abstract: While embedded silicon germanium alloy and silicon carbon alloy provide many useful applications, especially for enhancing the mobility of MOSFETs through stress engineering, formation of alloyed silicide on these surfaces degrades device performance. The present invention provides structures and methods for providing unalloyed silicide on such silicon alloy surfaces placed on semiconductor substrates. This enables the formation of low resistance contacts for both mobility enhanced PFETs with embedded SiGe and mobility enhanced NFETs with embedded Si:C on the same semiconductor substrate. Furthermore, this invention provides methods for thick epitaxial silicon alloy, especially thick epitaxial Si:C alloy, above the level of the gate dielectric to increase the stress on the channel on the transistor devices.

Abstract: A method of forming a semiconductor device comprises providing a semiconductor substrate, providing a semiconductor layer of a first conductivity type over the semiconductor substrate, forming a first region of the first conductivity type in the semiconductor layer, and forming a control region over the semiconductor layer and over part of the first region. A mask layer is formed over the semiconductor layer and outlines a first portion of a surface of the semiconductor layer over part of the first region. Semiconductor material of a second conductivity type is provided to the outlined first portion to provide a second region in the semiconductor layer.

Abstract: A method of controlling gate induced drain leakage current of a transistor is disclosed. The method includes forming a dielectric region (516) on a surface of a substrate having a first concentration of a first conductivity type (P-well). A gate region (500) having a length and a width is formed on the dielectric region. Source (512) and drain (504) regions having a second conductivity type (N+) are formed in the substrate on opposite sides of the gate region. A first impurity region (508) having the first conductivity type (P+) is formed adjacent the source. The first impurity region has a second concentration greater than the first concentration.

Abstract: A short channel Lateral MOSFET (LMOS) and method are disclosed with interpenetrating drain-body protrusions (IDBP) for reducing channel-on resistance while maintaining high punch-through voltage. The LMOS includes lower device bulk layer; upper source and upper drain region both located atop lower device bulk layer; both upper source and upper drain region are in contact with an intervening upper body region atop lower device bulk layer; both upper drain and upper body region are shaped to form a drain-body interface; the drain-body interface has an IDBP structure with a surface drain protrusion lying atop a buried body protrusion while revealing a top body surface area of the upper body region; gate oxide-gate electrode bi-layer disposed atop the upper body region forming an LMOS with a short channel length defined by the horizontal length of the top body surface area delineated between the upper source region and the upper drain region.

Abstract: A method of controlling gate induced drain leakage current of a transistor is disclosed. The method includes forming a dielectric region (516) on a surface of a substrate having a first concentration of a first conductivity type (P-well). A gate region (500) having a length and a width is formed on the dielectric region. Source (512) and drain (504) regions having a second conductivity type (N+) are formed in the substrate on opposite sides of the gate region. A first impurity region (508) having the first conductivity type (P+) is formed adjacent the source. The first impurity region has a second concentration greater than the first concentration.

Abstract: Non-planar transistors, such as FinFETs, may be formed in a bulk configuration in the context of a replacement gate approach, wherein the semiconductor fins are formed during the replacement gate sequence. To this end, in some illustrative embodiments, a buried etch mask may be formed in an early manufacturing stage on the basis of superior process conditions.

Abstract: When forming sophisticated high-k metal gate electrode structures, a threshold adjusting semiconductor alloy may be formed on the basis of selective epitaxial growth techniques and a hard mask comprising at least two hard mask layers. The hard mask may be patterned on the basis of a plasma-based etch process, thereby providing superior uniformity during the further processing upon depositing the threshold adjusting semiconductor material. In some illustrative embodiments, one hard mask layer is removed prior to actually selectively depositing the threshold adjusting semiconductor material.

Abstract: According to one embodiment, a method of manufacturing a semiconductor device which includes a MISFET, includes: forming a gate insulating film on a semiconductor substrate; forming a gate electrode on the gate insulating film; implanting nitrogen equal to or more than 5.0e14 atoms/cm2 and equal to or less than 1.5e15 atoms/cm2 in the semiconductor substrate by tilted ion implantation in a direction from an outside to an inside with respect to side surfaces of the gate electrode; depositing a metal film including nickel on areas in which nitrogen atoms are implanted, the areas are in a semiconductor substrate on both sides of the gate electrode; and performing first heat processing of reacting the metal film and the semiconductor substrate and forming metal semiconductor compound layers, the shapes of the layers are controlled by the nitrogen profiles of the areas.

Abstract: Methods of forming, on a substrate, a first lateral high-voltage MOS transistor and a second lateral high-voltage MOS transistor complementary to said first one are disclosed. According to one embodiment, the method includes (1) providing a substrate of a first conductivity type including a first active region for said first lateral high-voltage MOS transistor and a second active region for said second lateral high-voltage MOS transistor and (2) forming at least one first doped region of the first conductivity type in the first active region and forming in the second active region a drain extension region of the second conductivity type extending from a substrate surface to an interior of the substrate, including a concurrent implantation of dopants through openings of one and the same mask into the first and second active regions.

Abstract: When forming sophisticated transistors, for instance comprising high-k metal gate electrode structures, a significant material loss of an embedded strain-inducing semiconductor material may be compensated for, or at least significantly reduced, by performing a second epitaxial growth step after the incorporation of the drain and source extension dopant species. In this manner, superior strain conditions may be achieved, while also the required drain and source dopant profile may be implemented.

Abstract: The present application discloses a method for manufacturing a gate-all-around field effect transistor, comprising the steps of forming a suspended fin in a semiconductor substrate; forming a gate stack around the fin; and forming source/drain regions in the fin on both sides of the gate stack, wherein an isolation dielectric layer is formed in a portion of the semiconductor substrate which is adjacent to bottom of both the fin and the gate stack. The present invention relates to a method for manufacturing a gate-all-around device on a bulk silicon substrate, which suppress a self-heating effect and a floating-body effect of the SOI substrate, and lower a manufacture cost. The inventive method is a conventional top-down process with respect to a reference plane, which can be implemented as a simple manufacture process, and is easy to be integrated into and compatible with a planar CMOS process. The inventive method suppresses a short channel effect and promotes miniaturization of MOSFETs.

Abstract: A low-temperature metal gate stack for a field-effect transistor that is electrically activated at temperatures below 1000° C. The metal gate stack is composed of low melting materials that can be deposited by physical vapor deposition (PVD) onto a substrate.

Abstract: The present application discloses a MOSFET and a method for manufacturing the same. The MOSFET comprises an SOI chip comprising a semiconductor substrate, a buried insulating layer on the semiconductor substrate, and a semiconductor layer on the buried insulating layer; source/drain regions formed in the semiconductor layer; a channel region formed in the semiconductor layer and located between the source/drain regions; and a gate stack comprising a gate dielectric layer on the semiconductor layer, and a gate conductor on the gate dielectric layer, wherein the MOSFET further comprises a backgate formed in a portion of the semiconductor substrate below the channel region, and the backgate has a non-uniform doping profile, and wherein the buried insulating layer serves as a gate dielectric layer of the backgate. The MOSFET has an adjustable threshold voltage by changing the type of dopant and/or the doping profile in the backgate, and reduces a leakage current of the semiconductor device.

Abstract: A method of forming an integrated circuit includes forming a gate structure over a substrate. Portions of the substrate are removed to form recesses adjacent to the gate structure. A dopant-rich layer having first type dopants is formed on a sidewall and a bottom of each of the recesses. A silicon-containing material structure is formed in each of the recesses. The silicon-containing material structure has second type dopants. The second type dopants are opposite to the first type dopants.

Abstract: An embodiment of a MOS device resistant to ionizing-radiation, has: a surface semiconductor layer with a first type of conductivity; a gate structure formed above the surface semiconductor layer, and constituted by a dielectric gate region and a gate-electrode region overlying the dielectric gate region; and body regions having a second type of conductivity, formed within the surface semiconductor layer, laterally and partially underneath the gate structure. In particular, the dielectric gate region is formed by a central region having a first thickness, and by side regions having a second thickness, smaller than the first thickness; the central region overlying an intercell region of the surface semiconductor layer, set between the body regions.

Abstract: A method of fabrication of an analog, asymmetric Metal-Oxide-Semiconductor-Field-Effect-Transistor (MOSFET) is provided. The method may comprise forming a first gate oriented in a first direction over an active region of a semiconductor substrate, forming a second gate extending perpendicular to the first gate over a second active region, using a dual-directional implant process to form a reduced-HALO doped area on a drain side of the first gate and also for a HALO doped area for the second gate, while the source side of the first gate is covered by a resist. Additionally, the method may comprise forming a HALO doped area on the source side of the first gate using a quad-directional implant process using the mask also used for HALO implants of other digital-logic devices on the substrate, while the drain side of the gate is blocked by a resist.

Abstract: An MOS transistor includes a doping profile that selectively increases the dopant concentration of the body region. The doping profile has a shallow portion that increases the dopant concentration of the body region just under the surface of the transistor under the gate, and a deep portion that increases the dopant concentration of the body region under the source and drain regions. The doping profile may be formed by implanting dopants through the gate, source region, and drain region. The dopants may be implanted in a high energy ion implant step through openings of a mask that is also used to perform another implant step. The dopants may also be implanted through openings of a dedicated mask.

Abstract: A static RAM cell may be formed on the basis of two double channel transistors and a select transistor, wherein a body contact may be positioned laterally between the two double channel transistors in the form of a dummy gate electrode structure, while a further rectangular contact may connect the gate electrodes, the source regions and the body contact, thereby establishing a conductive path to the body regions of the transistors. Hence, compared to conventional body contacts, a very space-efficient configuration may be established so that bit density in static RAM cells may be significantly increased.

Abstract: A junctionless metal-oxide-semiconductor transistor is described. In one aspect, a transistor device comprises a semiconductor material. The semiconductor material comprises first, second, and third portions. The second portion is located between the first and third portions. The first, second, and third portions are doped with dopants of the same polarity and the same concentration. The transistor device further comprises an electrode connected to the second portion. A current flows between the first and third portions when a voltage is applied to the electrode.

Abstract: Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.

Abstract: A protection film is formed on a semiconductor substrate. Impurity ions are implanted into the semiconductor substrate through the protection film. The impurity is activated to form an impurity layer. The protection film is removed after forming the impurity layer. The semiconductor substrate of a surface portion of the impurity layer is removed after removing the protection film. A semiconductor layer is epitaxially grown above the semiconductor substrate after removing the semiconductor substrate of the surface portion of the impurity layer.

Abstract: A semiconductor component and a method for manufacturing the semiconductor component, wherein the semiconductor component includes a transient voltage suppression structure that includes at least two diodes and a Zener diode. In accordance with embodiments, a semiconductor material is provided that includes an epitaxial layer. The at least two diodes and the Zener diode are created at the surface of the epitaxial layer, where the at least two diodes may be adjacent to the Zener diode.

Abstract: The semiconductor device includes a first transistor including a first impurity layer containing boron or phosphorus, a first epitaxial layer formed above the first impurity layer, a first gate electrode formed above the first epitaxial layer with a first gate insulating film formed therebetween and first source/drain regions, and a second transistor including a second impurity layer containing boron and carbon, or arsenic or antimony, a second epitaxial layer formed above the second impurity layer, a second gate electrode formed above the second epitaxial layer with a second gate insulating film thinner than the first gate insulating film formed therebetween, and second source/drain regions.

Abstract: Recessed channel array transistor (RCAT) structures and method of formation are generally described. In one example, an electronic device includes a semiconductor substrate, a first fin coupled with the semiconductor substrate, the first fin comprising a first source region and a first drain region, and a first gate structure of a recessed channel array transistor (RCAT) formed in a first gate region disposed between the first source region and the first drain region, wherein the first gate structure is formed by removing a sacrificial gate structure to expose the first fin in the first gate region, recessing a channel structure into the first fin, and forming the first gate structure on the recessed channel structure.

Abstract: The present invention discloses a method of manufacturing a depletion metal oxide semiconductor (MOS) device. The method includes: providing a substrate; forming a first conductive type well and an isolation region in the substrate to define a device area; defining a drift region, a source, a drain, and a threshold voltage adjustment region, and implanting second conductive type impurities to form the drift region, the source, the drain, and the threshold voltage adjustment region, respectively; defining a breakdown protection region between the drain and the threshold voltage adjustment region, and implanting first conductive type impurities to form the breakdown protection region; and forming a gate in the device area; wherein a part of the breakdown protection region is below the gate, and the breakdown protection region covers an edge of the threshold voltage adjustment region.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device. A method may include forming a first well by injecting first conduction type impurity ions on and/or over a semiconductor substrate, forming an extended drain region overlapped with a region of said first well by injecting second conduction type impurities on and/or over a semiconductor substrate, and/or forming a first conduction type second well on and/or over a semiconductor substrate under an extended drain region to overlap with another region of a first well by injecting second conduction type impurities on and/or over a semiconductor substrate. A method may include forming a gate over a first well overlapped with an extended drain region, and/or forming a drain region by injecting second conduction type impurities on and/or over an extended drain region at one side of a gate.

Abstract: A method of forming a semiconductor device includes: forming a channel of a field effect transistor (FET) in a substrate; forming a heavily doped region in the substrate; and forming recesses adjacent the channel and the heavily doped region. The method also includes: forming an undoped or lightly doped intermediate layer in the recesses on exposed portions of the channel and the heavily doped region; and forming source and drain regions on the intermediate layer such that the source and drain regions are spaced apart from the heavily doped region by the intermediate layer.

Abstract: The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS transistor. The carbon containing layer (110) will prevent the diffusion of dopants into the region (40) directly beneath the gate dielectric layer (50).

Abstract: A semiconductor device 1 according to one embodiment of the invention includes: a semiconductor substrate 10; a convex region 12 provided on the semiconductor substrate 10; a gate insulating film 100 provided on the convex region 12; a channel region 101 located in the convex region 12 under the gate insulating film 100; source/drain regions 115 provided on both sides of the convex region 12 and having extensions 115a on both sides of the channel region 101; and a halo layer 110 provided between the convex region 12 and the source/drain region 115 so as to contact with the convex region 12.

Abstract: Performance and/or uniformity of sophisticated transistors may be enhanced by incorporating a carbon species in the active regions of the transistors prior to forming complex high-k metal gate electrode structures. For example, a carbon species may be incorporated by ion implantation into the active region of a P-channel transistor and an N-channel transistor after selectively forming a threshold adjusted semiconductor material for the P-channel transistor, while the active region of the N-channel transistor is still masked.

Abstract: The present disclosure provides a semiconductor device that may include a substrate including a semiconductor layer overlying an insulating layer. A gate structure that is present on a channel portion of the semiconductor layer. A first dopant region is present in the channel portion of the semiconductor layer, in which the peak concentration of the first dopant region is present within the lower portion of the gate conductor and the upper portion of the semiconductor layer. A second dopant region is present in the channel portion of the semiconductor layer, in which the peak concentration of the second dopant region is present within the lower portion of the semiconductor layer.

Abstract: A method of forming a lateral DMOS transistor includes performing a low energy implantation using a first dopant type and being applied to the entire device area. The dopants of the low energy implantation are blocked by the conductive gate. The method further includes performing a high energy implantation using a third dopant type and being applied to the entire device area. The dopants of the high energy implantation penetrate the conductive gate and is introduced into the entire device active area including underneath the conductive gate. After annealing, a double-diffused lightly doped drain (DLDD) region is formed from the high and low energy implantations and is used as a drift region of the lateral DMOS transistor. The DLDD region overlaps with the body region at a channel region and interacts with the dopants of the body region to adjust a threshold voltage of the lateral DMOS transistor.

Abstract: A semiconductor device includes a semiconductor substrate having a drain region, a source region and an impurity diffusion region; an oxide film formed on the impurity diffusion region; a first protective film including a SiN film as a principle component and being formed on the oxide film; and a second protective film containing carbon and being formed on the first protective film. A method of manufacturing the semiconductor device, includes doping an impurity into a semiconductor substrate, thereby forming a drain region, a source region and an impurity diffusion region; forming an oxide film on the impurity diffusion region; forming a first protective film including a SiN film as a principle component on the oxide film; and forming a second protective film containing carbon on the first protective film.

Abstract: The present application discloses a semiconductor device comprising a fin of semiconductive material formed from a semiconductor layer over a semiconductor substrate and having two opposing sides perpendicular to the main surface of the semiconductor substrate; a source region and a drain region provided in the semiconductor substrate adjacent to two ends of the fin and being bridged by the fin; a channel region provided at the central portion of the fin; and a stack of gate dielectric and gate conductor provided at one side of the fin, where the gate conductor is isolated from the channel region by the gate dielectric, and wherein the stack of gate dielectric and gate conductor extends away from the one side of the fin in a direction parallel to the main surface of the semiconductor substrate, and insulated from the semiconductor substrate by an insulating layer.

Abstract: A transistor which includes halo regions disposed in a substrate adjacent to opposing sides of the gate. The halo regions have upper and lower regions. The upper region is a crystalline region with excess vacancies and the lower region is an amorphous region. Source/drain diffusion regions are disposed in the halo regions. The source/drain diffusion regions overlap the upper and lower halo regions. This architecture offers the minimal extension resistance as well as minimum lateral diffusion for better CMOS device scaling.

Abstract: A method of manufacturing N-type MOSFET includes: implanting a p-type dopant into in a surface layer of a semiconductor substrate to form a channel region; forming a gate insulating film including High-k material and a gate electrode on said channel region; implanting a p-type dopant into both ends of said channel region in an inner portion of said semiconductor substrate to form halo regions; implanting a p-type dopant into both ends of said channel region in a surface layer of said semiconductor substrate to form extension regions. One of said step of forming said channel region and said step of forming halo regions includes: implanting C into one of said channel region and said halo regions. An inclusion amount of said High-k material is an amount that increase of a threshold voltage caused by said High-k material being included in said gate insulating film compensates for decrease of said threshold voltage caused by said C being implanted.

Abstract: In sophisticated approaches for forming high-k metal gate electrode structures in an early manufacturing stage, a threshold adjusting semiconductor alloy may be deposited on the basis of a selective epitaxial growth process without affecting the back side of the substrates. Consequently, any negative effects, such as contamination of substrates and process tools, reduced surface quality of the back side and the like, may be suppressed or reduced by providing a mask material and preserving the material at least during the selective epitaxial growth process.

Abstract: A high voltage/power semiconductor device using a low voltage logic well is provided. The semiconductor device includes a substrate, a first well region formed by being doped in a first location on a surface of the substrate, a second well region formed by being doped with impurity different from the first well region's in a second location on a surface of the substrate, an overlapping region between the first well region and the second well region where the first well region and the second well region substantially coexist, a gate insulating layer formed on the surface of the first and the second well regions and the surface of the overlapping region, a gate electrode formed on the gate insulating layer, a source region formed on an upper portion of the first well region, and a drain region formed on an upper portion of the second well region.

Abstract: An LDMOS device and a method for fabricating the same that may include a first conductivity-type semiconductor substrate having an active area and a field area; a second conductivity-type deep well formed on the first conductivity-type semiconductor substrate; a second conductivity-type adjusting layer located in the second conductivity-type deep well; a first conductivity-type body formed in the second conductivity-type deep well; an insulating layer formed on the first conductivity-type semiconductor substrate in the active area and the field area; a gate area formed on the first conductivity-type semiconductor substrate in the active area; a second conductivity-type source area formed in the first conductivity-type body; a second conductivity-type drain area formed in the second conductivity-type deep well. Accordingly, such an LDMOS device has a high breakdown voltage without an increase in on-resistance.

Abstract: A FET comprising an LDD region having a high overlap extension beneath the gate thereof and a pit region on the surface of the substrate immediately below the gate and entirely surrounded by said LDD region. The surface dopant concentration is in the vicinity of the gate corner so as to reduce the local field strength, and thereby decrease the GIDL, whilst keeping high overlap extension so a to maintain a high Ion current. More particularly a region under the gate corner but enclosed by the conventional LDD is counterdoped. Counter-doping of the LDD is performed with a sufficiently low energy, a specific dose and a low angle that the counter-doped region is enclosed into the LDD (at the substrate/gate-oxide interface and keeping high overlap extension between the gate oxide and the non-counter-doped LDD). As an optimum, the counter-doped region is under the gate corner. In that way, high Ion current is ensure with a overlap length is not altered.

Abstract: A nonvolatile semiconductor memory has a semiconductor substrate, a first insulating film formed on a channel region on a surface portion of the semiconductor substrate, a charge accumulating layer formed on the first insulating film, a second insulating film formed on the charge accumulating layer, a control gate electrode formed on the second insulating film, and a third insulating film including an Si—N bond that is formed on a bottom surface and side surfaces of the charge accumulating layer.

Abstract: Provided is a method of fabricating a thin film transistor including source and drain electrodes, a novel channel layer, a gate insulating layer, and a gate electrode, which are formed on a substrate. The method includes the steps of forming the channel layer using an oxide semiconductor doped with boron; and patterning the channel layer. The channel layer formed is an oxide semiconductor thin film doped with boron. The electrical characteristics and high temperature stability of the thin film transistor are improved remarkably.

Abstract: A method of doping a semiconductor body is provided herein. In one embodiment, a semiconductor body is exposed to an activated hydrogen gas for a predetermined time period and temperature. The activated hydrogen gas that is configured to react with a surface of a semiconductor body. The activated hydrogen gas breaks existing bonds in the substrate (e.g., silicon-silicon bonds), thereby forming a reactive layer comprising weakened (e.g., silicon-hydrogen (Si—H) bonds, silanol (Si—OH) bonds) and/or dangling bonds (e.g., dangling silicon bonds). The dangling bonds, in addition to the easily broken weakened bonds, comprise reactive sites that extend into one or more surfaces of the semiconductor body. A reactant (e.g., n-type dopant, p-type dopant) may then be introduced to contact the reactive layer of the semiconductor body. The reactant chemically bonds to reactive sites comprised within the reactive layer, thereby resulting in a doped layer within the semiconductor body comprising the reactant.

Abstract: This invention discloses a method for manufacturing a one-time programmable (OTP) memory includes a first and second MOS transistors connected in parallel and controlled by a common gate formed with a single polysilicon stripe. The method further comprises a step of implanting a drift region in a substrate region below a drain and source of the first and second MOS transistors counter doping a lightly dope drain (LDD) encompassing and surrounding a drain and a source of the first MOS transistor having a different threshold voltage than the second MOS transistor not reached by the drift region.