Abstract: The present invention provides methods for the manufacture of a trench structure in a multilayer wafer that comprises a substrate, an oxide layer on the substrate and a semiconductor layer on the oxide layer. These methods include the steps of forming a trench through the semiconductor layer and the oxide layer and extending into the substrate, and of performing an anneal treatment of the formed trench such that at the inner surface of the trench some material of the semiconductor layer flows at least over a portion of the part of the oxide layer exposed at the inner surface of the trench. Substrates manufactured according to this invention are advantageous for fabricating various semiconductor devices, e.g., MOSFETs, trench capacitors, and the like.

Abstract: A semiconductor device has a substrate; a multi-layered interconnect formed on the substrate, and having a plurality of interconnect layers, each of which being configured by an interconnect and an insulating layer, stacked therein; a memory circuit formed in a memory circuit region on the substrate in a plan view, and having a peripheral circuit and at least one capacitor element embedded in the multi-layered interconnect; and a logic circuit formed in a logic circuit region on the substrate, wherein the capacitor element is configured by a lower electrode, a capacitor insulating film, an upper electrode, an embedded electrode and an upper interconnect; the top surface of the upper interconnect, and the top surface of the interconnect configuring the logic circuit formed in the same interconnect layer with the upper interconnect, are aligned to the same plane.

Abstract: The invention relates to a MEMS resonator comprising a first electrode, a movable element (48) comprising a second electrode, the movable element (48) at least being movable towards the first electrode, the first electrode and the movable element (48) being separated by a gap (46, 47) having sidewalls. According to the invention, the MEMS resonator is characterized in that the gap (46, 47) has been provided with a dielectric layer (60) on at least one of the sidewalls.

Abstract: A method of forming a semiconductor memory device includes sequentially forming an etch stop layer and then a mold layer, forming a plurality of line-shaped support structures and a first sacrificial layer filling gaps between the support structures on the mold layer, sequentially forming a plurality of line-shaped first mask patterns, a second sacrificial layer, and then second mask patterns on the support structures and on the first sacrificial layer, removing the second sacrificial layer, the first sacrificial layer, and the mold layer using the first mask patterns, the second mask patterns, and the support structures as masks, removing the first mask patterns and second mask patterns, filling the storage node electrode holes with a conductive material and etching back the conductive material to expose the support structures, and removing the first sacrificial layer and the mold layer to form pillar-type storage node electrodes supported by the support structures.

Abstract: A semiconductor device is manufactured by forming a hole as being extended through a first insulating film and an insulating interlayer stacked over a semiconductor substrate, allowing side-etching of the inner wall of the hole to proceed specifically in a portion of the insulating interlayer, to thereby form a structure having the first insulating film projected out from the edge towards the center of the hole; forming a lower electrode film as being extended over the top surface, side face and back surface of the first insulating film, and over the inner wall and bottom surface of the hole; filling a protective film in the hole; removing the lower electrode film specifically in portions fallen on the top surface and side face of the first insulating film; removing the protective film; and forming a cylindrical capacitor in the hole.

Abstract: A method of forming a non-volatile memory device includes the following steps. First and second cell gates are formed in a cell region. First and second peripheral gates are formed in a peripheral-region. A first insulating layer is formed over the first and second cell gates and the first and second peripheral gates. A second conductive layer is formed over the first insulating layer. A third insulating layer is formed over the second conductive layer. Selected portions of the third insulating layer, the second conductive layer, and the first insulating layer are removed to form an inter-gate plug provided between the first and second cell gates. The inter-gate plug completely fills a space defined between the first and second cell gates.

Abstract: Capacitors may be formed in the metallization system of semiconductor devices without requiring a modification of the hard mask patterning process for forming vias and trenches in the dielectric material of the metallization layer under consideration. To this end, a capacitor opening is formed prior to actually forming the hard mask for patterning the trench and via openings, wherein the hard mask material may thus preserve integrity of the capacitor opening and may remain as a portion of the electrode material after filling in the conductive material for the metal lines, vias and the capacitor electrode.

Abstract: Provided is a method of fabricating a semiconductor microstructure, the method including forming a lower material layer on a semiconductor substrate, the lower material layer including a nitride of a Group III-element; forming a mold material layer on the lower material layer; forming an etching mask on the mold material layer, the etching mask being for forming a structure in the mold material layer; anisotropic-etching the mold material layer and the lower material layer by using the etching mask; and isotropic-etching the mold material layer and the lower material layer.

Abstract: A novel and useful apparatus for and method of providing noise isolation between integrated circuit devices on a semiconductor chip. The invention addresses the problem of noise generated by digital switching devices in an integrated circuit chip that may couple through the silicon substrate into sensitive analog circuits (e.g., PLLs, transceivers, ADCs, etc.) causing a significant degradation in performance of the sensitive analog circuits. The invention utilizes a deep trench capacitor (DTCAP) device connected to ground to isolate victim circuits from aggressor noise sources on the same integrated circuit chip. The deep penetration of the capacitor creates a grounded shield deep in the substrate as compared with other prior art shielding techniques.

Abstract: In accordance with an aspect of the invention, a method is provided for fabricating a semiconductor chip including a trench capacitor. In such method, a monocrystalline semiconductor region can be etched in a vertical direction through an opening in a dielectric layer to form a trench exposing a rough surface of monocrystalline semiconductor material. The trench has an initial lateral dimension in a first direction transverse to the vertical direction. The semiconductor material exposed at the surface of the trench then is etched in a crystallographic orientation-dependent manner to expose a multiplicity of crystal facets of the semiconductor material at the trench surface. A dopant-containing liner may then be deposited to line the surface of the trench and a temperature of the substrate then be elevated to drive a dopant from the dopant-containing liner into the semiconductor region adjacent to the surface. During such step, typically a portion of the semiconductor material exposed at the wall is oxidized.

Abstract: A method for fabricating a capacitor includes forming a sacrificial layer having a plurality of trenches on an upper portion of a substrate, forming storage nodes in the trenches, exposing upper portions of the storage nodes by removing a portion of the sacrificial layer, forming supporters to support the exposed upper portions of the storage nodes, removing the sacrificial layer under the supporters, and removing the supporters.

Abstract: Disclosed are embodiments for a container capacitor structure in which at least two container capacitors, e.g., an inner and outer container capacitor, are made concentric and nested with respect to one another. The nested capacitors are formed in one embodiment by defining a hole in a dielectric layer for the nested container capacitors in the vicinity of two capacitor contact plugs. An outer capacitor plate is formed by etching back poly 1 to leave it substantially on the vertical edges of the hole and in contact with one of the plugs. At least one sacrificial sidewall is formed on the poly 1, and poly 2 is deposited over the sidewalls to form an inner capacitor plate in contact with the other plug. The structure is planarized, the sacrificial sidewalls are removed, a capacitor dielectric is formed, and is topped with poly 3. Additional structures such as a protective layer (to prevent poly 1-to-poly 2 shorting) and a conductive layer (to strap the plugs to their respective poly layers) can also be used.

Abstract: A deep trench varactor structure compatible with a deep trench capacitor structure and methods of manufacturing the same are provided. A buried plate layer is formed on a second deep trench, while the first trench is protected from formation of any buried plate layer. The inside of the deep trenches is filled with a conductive material to form inner electrodes. At least one doped well is formed outside and abutting portions of the first deep trench and constitutes at least one outer varactor electrode. Multiple doped wells may be connected in parallel to provide a varactor having complex voltage dependency of capacitance. The buried plate layer and another doped well connected thereto constitute an outer electrode of a linear capacitor formed on the second deep trench.

Abstract: A semiconductor device includes: a first interlayer insulating film; a first conductive member provided lower than the first interlayer insulating film; a contact plug that penetrates through the first interlayer insulating film, and is electrically connected to the first conductive member, the contact plug including a small-diameter part, and a large-diameter part arranged on the small-diameter part, an outer diameter of the large-diameter part being larger than an outer diameter of the small-diameter part, and the outer diameter of the large-diameter part being larger than an outer diameter of a connection face between the second conductive member and the large-diameter part; and a second conductive member that is provided on the first interlayer insulating film, and is electrically connected to the contact plug.

Abstract: A termination structure with multiple embedded potential spreading capacitive structures (TSMEC) and method are disclosed for terminating an adjacent trench MOSFET atop a bulk semiconductor layer (BSL) with bottom drain electrode. The BSL has a proximal bulk semiconductor wall (PBSW) supporting drain-source voltage (DSV) and separating TSMEC from trench MOSFET. The TSMEC has oxide-filled large deep trench (OFLDT) bounded by PBSW and a distal bulk semiconductor wall (DBSW). The OFLDT includes a large deep oxide trench into the BSL and embedded capacitive structures (EBCS) located inside the large deep oxide trench and between PBSW and DBSW for spatially spreading the DSV across them. In one embodiment, the EBCS contains interleaved conductive embedded polycrystalline semiconductor regions (EPSR) and oxide columns (OXC) of the OFLDT, a proximal EPSR next to PBSW is connected to an active upper source region and a distal EPSR next to DBSW is connected to the DBSW.

Abstract: A process for fabrication of a semiconductor device that includes forming a first trench in a semiconductor body, forming spaced spacers in the first trench, and forming a narrower second trench at the bottom of the first trench using the spacers as a mask.

Abstract: A method of fabricating an LFCC device includes forming a first trench in a substrate that extends vertically from an upper surface to a depth within the substrate, the first trench having first sidewalls, a first bottom, and a pattern formed on the first sidewalls near the first bottom of the trench, and forming an oxide layer on the first sidewalls and first bottom of the first trench that leaves a second trench located within the first trench and is separated from the first trench by the oxide layer. The second trench has second sidewalls that are substantially vertical without showing the pattern and a second bottom that is substantially flat. The pattern compensates for the difference in oxidation rates between the bottom of the first trench and the first sidewalls. The LFCC structure includes a first trench with the pattern.

Abstract: A method of forming a SOI substrate, diodes in the SOI substrate and electronic devices in the SOI substrate and an electronic device formed using the SOI substrate. The method of forming the SOI substrate includes forming an oxide layer on a silicon first substrate; ion-implanting hydrogen through the oxide layer into the first substrate, to form a fracture zone in the substrate; forming a doped dielectric bonding layer on a silicon second substrate; bonding a top surface of the bonding layer to a top surface of the oxide layer; thinning the first substrate by thermal cleaving of the first substrate along the fracture zone to form a silicon layer on the oxide layer to formed a bonded substrate; and heating the bonded substrate to drive dopant from the bonding layer into the second substrate to form a doped layer in the second substrate adjacent to the bonding layer.

Abstract: Embodiments of the present invention generally relates to an apparatus and a method for processing semiconductor substrates. Particularly, embodiments of the present invention relates to methods and apparatus for trench and via profile modification prior to filling the trench and via. One embodiment of the present invention comprises forming a sacrifice layer to pinch off a top opening of a trench structure by exposing the trench structure to an etchant. In one embodiment, the etchant is configured to remove the first material by reacting with the first material and generating a by-product, which forms the sacrifice layer.

Abstract: Method of manufacturing a MEMS device integrated in a silicon substrate. In parallel to the manufacturing of the MEMS device passive components as trench capacitors with a high capacitance density can be processed. The method is especially suited for MEMS resonators with resonance frequencies in the range of 10 MHz.

Abstract: A process of forming a semiconductive capacitor device for a memory circuit includes forming a first capacitor cell recess and a second capacitor cell recess that are spaced apart by a capacitor cell boundary of a first height. The process includes lowering the first height of the capacitor cell boundary to a second height. A common plate capacitor bridges between the first recess and the second recess over the boundary above the second height and below the first height.

Abstract: A semiconductor component includes a semiconductor body, in which are formed: a substrate of a first conduction type, a buried semiconductor layer of a second conduction type arranged on the substrate, and a functional unit semiconductor layer of a third conduction type arranged on the buried semiconductor layer, in which at least two semiconductor functional units arranged laterally alongside one another are provided. The buried semiconductor layer is part of at least one semiconductor functional unit, the semiconductor functional units being electrically insulated from one another by an isolation structure which permeates the functional unit semiconductor layer, the buried semiconductor layer, and the substrate. The isolation structure includes at least one trench and an electrically conductive contact to the substrate, the contact to the substrate being electrically insulated from the functional unit semiconductor layer and the buried layer by the at least one trench.

Abstract: A method for fabricating a memory cell is provided. A trench is formed in a semiconductor structure that comprises a semiconductor layer, and a trench capacitor is formed in the trench. Conductivity determining impurities are implanted into the semiconductor structure to create a well region in the semiconductor layer that is directly coupled to the trench capacitor. A gate structure is formed overlying a portion of the well region. Conductivity determining ions are then implanted into other portions of the well region to form a source region and a drain region, and to define an active body region between the source region and the drain region. The active body region directly contacts the trench capacitor.

Abstract: A method for manufacturing a semiconductor device comprises depositing an absorption barrier layer of a dielectric film on a semiconductor substrate including a bottom electrode contact plug so as to separate the dielectric films between capacitors without having any influence of a bias of the adjacent capacitor, thereby improving a refresh characteristic of cells.

Abstract: Disclosed is a semiconductor component arrangement and a method for producing a semiconductor component arrangement. The method comprises producing a trench transistor structure with at least one trench disposed in the semiconductor body and with at least an gate electrode disposed in the at least one trench. An electrode structure is disposed in at least one further trench and comprises at least one electrode. The at least one trench of the transistor structure and the at least one further trench are produced by common process steps. Furthermore, the at least one electrode of the electrode structure and the gate electrode are produced by common process steps.

Abstract: A single crystal silicon etching method includes providing a single crystal silicon substrate having at least one trench therein. The substrate is exposed to a buffered fluoride etch solution which undercuts the silicon to provide lateral shelves when patterned in the <100> direction. The resulting structure includes an undercut feature when patterned in the <100> direction.

Abstract: Methods to form memory devices having a MIM capacitor with a recessed electrode are described. In one embodiment, a method of forming a MIM capacitor with a recessed electrode includes forming an excavated feature defined by a lower portion that forms a bottom and an upper portion that forms sidewalls of the excavated feature. The method includes depositing a lower electrode layer in the feature, depositing an electrically insulating layer on the lower electrode layer, and depositing an upper electrode layer on the electrically insulating layer to form the MIM capacitor. The method includes removing an upper portion of the MIM capacitor to expose an upper surface of the electrode layers and then selectively etching one of the electrode layers to recess one of the electrode layers. This recess isolates the electrodes from each other and reduces the likelihood of a current leakage path between the electrodes.

Abstract: Disclosed are a capacitor for a semiconductor device and a manufacturing method thereof. The capacitor includes a second oxide layer filling a first trench in a semiconductor substrate; second and third trenches in an active region at opposing sides of the second oxide layer in the first trench; a third oxide layer on the semiconductor substrate and on inner surfaces of the second and third trenches; and a polysilicon layer on the third oxide layer to fill the second and third trenches.

Abstract: A manufacturing method for double-side capacitor of stack DRAM has steps of: forming a sacrificial structure in the isolating trench and the capacitor trenches; forming a first covering layer and a second covering layer on the sacrificial structure; modifying a part of the second covering layer; removing the un-modified second covering layer and the first covering layer to expose the sacrificial structure; removing the exposed part of the sacrificial structure to expose the electrode layer; removing the exposed electrode layer to expose the oxide layer; and removing the oxide layer and sacrificial structure to form the double-side capacitors.

Abstract: A process for making a dielectric material where a precursor polymer selected from poly(phenylene vinylene) polyacetylene, poly(p-phenylene), poly(thienylene vinylene), poly(1,4-naphthylene vinylene), and poly(p-pyridine vinylene) is energized said by exposure by radiation or increase in temperature to a level sufficient to eliminate said leaving groups contained within the precursor polymer, thereby transforming the dielectric material into a conductive polymer. The leaving group in the precursor polymer can be a chloride, a bromide, an iodide, a fluoride, an ester, an xanthate, a nitrile, an amine, a nitro group, a carbonate, a dithiocarbamate, a sulfonium group, an oxonium group, an iodonium group, a pyridinium group, an ammonium group, a borate group, a borane group, a sulphinyl group, or a sulfonyl group.

Abstract: An through-substrate via fabrication method requires forming a through-substrate via hole in a semiconductor substrate, depositing an electrically insulating, continuous and substantially conformal isolation material onto the substrate and interior walls of the via using ALD, depositing a conductive material into the via and over the isolation material using ALD such that it is electrically continuous across the length of the via hole, and depositing a polymer material over the conductive material such that any continuous top-to-bottom openings present in the via holes are filled by the polymer material. The basic fabrication method may be extended to provide vias with multiple conductive layers, such as coaxial and triaxial vias.

Abstract: A method for fabricating a reservoir capacitor of a semiconductor device where a first peripheral circuit region and a second peripheral circuit region are defined comprises: forming a gate on an upper portion of a semiconductor substrate of the second peripheral circuit region; forming an interlayer insulating film on the entire upper portion of the semiconductor substrate including the gate; etching the interlayer insulating film of the second peripheral circuit region to form a bit line contact hole; forming a bit line material and a sacrificial film on the upper portion of the interlayer insulating film including the bit line contact hole; and etching the sacrificial film of the first peripheral circuit region to form a trench that exposes the bit line material.

Abstract: Methods and structures for a semiconductor device can use mask openings of varying widths to form structures of different depths, different materials, and different functionality. For example, processes and structures for forming shallow trench isolation, deep isolation, trench capacitors, base, emitter, and collector, among other structures for a lateral bipolar transistor are described.

Abstract: An electropolishing process for high resolution patterning of noble metals, such as platinum, for forming various semiconductor devices, such as capacitors or wiring patterns is disclosed.

Abstract: A method for forming a memory device is provided by first forming at least one trench in a semiconductor substrate. Next, a lower electrode is formed in the at least one trench, and thereafter a conformal dielectric layer is formed on the lower electrode. An upper electrode is then formed on the conformal dielectric layer. The forming of the upper electrode may include a conformal deposition of metal nitride layer, and a non-conformal deposition of an electrically conductive material atop the metal nitride layer, in which the electrically conductive material encloses the at least one trench.

Abstract: Passive, high density, 3d IC capacitor stacks and methods that provide the integration of capacitors and integrated circuits in a wafer to wafer bonding process that provides for the integration of capacitors formed on one wafer, alone or with active devices, with one or more integrated circuits on one or more additional wafers that may be stacked in accordance with the process. Wafer to wafer bonding is preferably by thermo-compression, with grinding and chemical mechanical polishing being used to simply aspects of the process of fabrication. Various features and alternate embodiments are disclosed.

Abstract: A semiconductor structure formation method and operation method. The structure includes (i) a dielectric layer, (ii) a bottom capacitor plate and an electrically conductive line on the dielectric layer, (iii) a top capacitor plate on top of the bottom capacitor plate, (iv) a gap region, and (v) a solder ball on the dielectric layer. The dielectric layer includes a top surface that defines a reference direction perpendicular to the top surface. The top capacitor plate overlaps the bottom capacitor plate in the reference direction. The gap region is sandwiched between the bottom capacitor plate and the top capacitor plate. The gap region does not include any liquid or solid material. The solder ball is electrically connected to the electrically conductive line. The top capacitor plate is disposed between the dielectric layer and the solder ball.

Abstract: A multi-dielectric film including at least one first dielectric film that is a composite film made of zirconium-hafnium-oxide and at least one second dielectric film that is a metal oxide film made of amorphous metal oxide. Adjacent ones of the dielectric films are made of different materials.

Abstract: By forming a first portion of a substrate contact in an SOI device on the basis of a trench capacitor process, the overall manufacturing process for patterning contact elements may be enhanced since the contacts may only have to extend down to the level of the semiconductor layer. Since the lower portion of the substrate contact may be formed concurrently with the fabrication of trench capacitors, complex patterning steps may be avoided which may otherwise have to be introduced when the substrate contacts are to be formed separately from contact elements connecting to the device level.

Abstract: An improved semiconductor device, including a capacitor structure. The device has a first electrode member, which has a first length and a first width. The device also has a second electrode member, which has a second length and a second width. Additionally, the device includes a capacitor dielectric material provided between the first electrode member and the second electrode member according to a specific embodiment. Depending upon the embodiment, the capacitor dielectric material is made of a suitable material or materials such as Al2O3, HfO2, SiN, NO, Al2O3/HfO2, AlNyOx, ZrO2, any combinations of these, and the like. The device further includes a plurality of silicon nanocrystals spatially disposed in an area associated with the first width and the first length of the first electrode member. Each one of the nanocrystals has a size of about 20 nanometers and less according to a specific embodiment.

Abstract: In a semiconductor integrated circuit device and a method of formation thereof, a semiconductor device comprises: a semiconductor substrate; an insulator at a top portion of the substrate, defining an insulator region; a conductive layer pattern on the substrate, the conductive layer pattern being patterned from a common conductive layer, the conductive layer pattern including a first pattern portion on the insulator in the insulator region and a second pattern portion on the substrate in an active region of the substrate, wherein the second pattern portion comprises a gate of a transistor in the active region; and a capacitor on the insulator in the insulator region, the capacitor including: a lower electrode on the first pattern portion of the conductive layer pattern, a dielectric layer pattern on the lower electrode, and an upper electrode on the dielectric layer pattern.

Abstract: A flash memory device may include a device isolation layer and an active area formed over a semiconductor substrate, a memory gate formed over the active area, and a control gate formed over the semiconductor substrate including the memory gate, wherein the active area, where a source contact is to be formed, has the same interval spacing as a bit line, and a common source line area, where the source contact is to be formed, has an impurity area connecting neighboring active areas.

Abstract: A trench-type storage device includes a trench in a substrate (100), with bundles of carbon nanotubes (202) lining the trench and a trench conductor (300) filling the trench. A trench dielectric (200) may be formed between the carbon nanotubes and the sidewall of the trench. The bundles of carbon nanotubes form an open cylinder structure lining the trench. The device is formed by providing a carbon nanotube catalyst structure on the substrate and patterning the trench in the substrate; the carbon nanotubes are then grown down into the trench to line the trench with the carbon nanotube bundles, after which the trench is filled with the trench conductor.

Abstract: A deep trench is formed to a depth midway into a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A top semiconductor layer is laterally recessed by an isotropic etch that is selective to the buried insulator layer. The deep trench is then etched below a bottom surface of the buried insulator layer. Ion implantation is performed at an angle into the deep trench to dope the sidewalls of the deep trench beneath the buried insulator layer, while the laterally recessed sidewalls of the top semiconductor layer are not implanted with dopant ions. A node dielectric and trench fill materials are deposited into the deep trench. A buried strap has an upper buried strap sidewall that is offset from a lower buried strap sidewall and a deep trench sidewall.

Abstract: Trench capacitors and methods of manufacturing the trench capacitors are provided. The trench capacitors are very dense series capacitor structures with independent electrode contacts. In the method, a series of capacitors are formed by forming a plurality of insulator layers and a plurality of electrodes in a trench structure, where each electrode is formed in an alternating manner with each insulator layer. The method further includes planarizing the electrodes to form contact regions for a plurality of capacitors.

Abstract: Techniques for manufacturing an electronic device. In certain embodiments, a substrate includes a lower patterned layer that has a target conductor. A hybrid-vertical contact may be disposed directly on the target conductor. The hybrid vertical contact may include a lower-vertical contact directly on the target conductor and an upper-vertical contact directly on the lower-vertical contact. The upper-vertical contact may have an upper width that is greater than a lower width of the lower-vertical contact.

Abstract: A deep trench device with a single sided connecting structure. The device comprises a substrate having a trench therein. A buried trench capacitor is disposed in a lower portion of the trench. An asymmetric collar insulator is disposed on an upper portion of the sidewall of the trench. A connecting structure is disposed in the upper portion of the trench, comprising an epitaxial silicon layer disposed on and adjacent to a relatively low portion of the asymmetric collar insulator and a connecting member disposed between the epitaxial silicon layer and a relatively high portion of the asymmetric collar insulator. A conductive layer is disposed between the relatively high and low portions of the asymmetric collar insulator, to electrically connect the buried trench capacitor and the connecting structure. A cap layer is disposed on the connecting structure. A fabrication method for a deep trench device is also disclosed.

Abstract: By controlling buried plate doping level and bias condition, different capacitances can be obtained from capacitors on the same chip with the same layout and deep trench process. The capacitors may be storage capacitors of DRAM/eDRAM cells. The doping concentration may be less than 3E19cm?3, a voltage difference between the biases of the buried electrodes may be at least 0.5V, and a capacitance of one capacitor may be at least 1.2 times, such as 2.0 times the capacitance of another capacitor.

Abstract: A method of making planar-type bottom electrode for semiconductor device is disclosed. A sacrificial layer structure is formed on a substrate. Multiple first trenches are defined in the sacrificial layer structure, wherein those first trenches are arranged in a first direction. The first trenches are filled with insulating material to form an insulating layer in each first trench. Multiple second trenches are defined in the sacrificial layer structure between the insulating layers, and are arranged in a second direction such that the second trenches intersect the first trenches. The second trenches are filled with bottom electrode material to form a bottom electrode layer in each second trench. The insulating layers separate respectively the bottom electrode layers apart from each other. Lastly, removing the sacrificial layer structure defines a receiving space by two adjacent insulating layers and two adjacent bottom electrode layers.

Abstract: A semiconductor device includes a first insulating layer, a capacitor, an adhesive layer, and an intermediate layer. The first insulating layer may include a first insulating film. The first insulating layered structure has a first hole. The capacitor is disposed in the first hole. The capacitor may include bottom and top electrodes and a capacitive insulating film. The capacitive insulating film is sandwiched between the bottom and top electrodes. The adhesive layer contacts with the bottom electrode. The adhesive layer has adhesiveness to the bottom electrode. The intermediate layer is interposed between the adhesive layer and the first insulating film. The intermediate layer contacts with the adhesive layer and with the first insulating film. The intermediate layer has adhesiveness to the adhesive layer and to the first insulating film.