Mesa Formation Patents (Class 438/39)
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Publication number: 20140302628Abstract: A method of manufacturing an optical semiconductor device including: forming a mesa structure including a first conductivity type cladding layer, an active layer and a second conductivity type cladding layer in this order on a first conductivity type semiconductor substrate, an upper most surface of the mesa structure being constituted of an upper face of the second conductivity type cladding layer; growing a first burying layer burying both sides of the mesa structure at higher position than the active layer; forming an depressed face by etching both edges of the upper face of the second conductivity type cladding layer; and growing a second burying layer of the first conductivity type on the depressed face of the second conductivity type cladding layer and the first burying layer.Type: ApplicationFiled: June 20, 2014Publication date: October 9, 2014Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.Inventors: Tatsuya Takeuchi, Taro Hasegawa
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Patent number: 8853669Abstract: A method of fabricating a substrate for a semipolar III-nitride device, comprising patterning and forming one or more mesas on a surface of a semipolar III-nitride substrate or epilayer, thereby forming a patterned surface of the semipolar III-nitride substrate or epilayer including each of the mesas with a dimension l along a direction of a threading dislocation glide, wherein the threading dislocation glide results from a III-nitride layer deposited heteroepitaxially and coherently on a non-patterned surface of the substrate or epilayer.Type: GrantFiled: October 26, 2011Date of Patent: October 7, 2014Assignee: The Regents of the University of CaliforniaInventors: James S. Speck, Anurag Tyagi, Steven P. Denbaars, Shuji Nakamura
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Patent number: 8846428Abstract: A method for manufacturing a light emitting diode chip includes the following steps: providing an epitaxial structure having an epitaxial layer; forming a first electrode and a second electrode on the epitaxial layer; coating an inert layer on the epitaxial structure, the first electrode and the second electrode continuously; annealing the first electrode and the second electrode; and removing the inert layer coated on the first electrode and the second electrode to expose the first electrode and the second electrode.Type: GrantFiled: July 16, 2013Date of Patent: September 30, 2014Assignee: Advanced Optoelectronic Technology, Inc.Inventors: Ya-Chi Lien, Tzu-Chien Hung
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Patent number: 8841152Abstract: Method for making a patterned thin film of an organic semiconductor. The method includes condensing a resist gas into a solid film onto a substrate cooled to a temperature below the condensation point of the resist gas. The condensed solid film is heated selectively with a patterned stamp to cause local direct sublimation from solid to vapor of selected portions of the solid film thereby creating a patterned resist film. An organic semiconductor film is coated on the patterned resist film and the patterned resist film is heated to cause it to sublime away and to lift off because of the phase change.Type: GrantFiled: May 7, 2012Date of Patent: September 23, 2014Assignee: Massachusetts Institute of TechnologyInventors: Matthias Erhard Bahlke, Marc A. Baldo, Hiroshi Antonio Mendoza
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Patent number: 8829543Abstract: A semiconductor light emitting device including a first type doped semiconductor layer, a light emitting layer, a second type doped semiconductor layer, and a reflection layer is provided. The first type doped semiconductor layer has a mesa portion and a depression portion. The light emitting layer is disposed on the mesa portion and has a first surface, a second surface and a first side surface connecting the first surface with the second surface. The second type doped semiconductor layer is disposed on the light emitting layer and has a third surface, a fourth surface and a second side surface connecting the third surface with the fourth surface. Observing from a viewing direction parallel to the light emitting layer, the reflection layer covers at least part of the first side surface and at least part of the second side surface. A flip chip package device is also provided.Type: GrantFiled: March 6, 2013Date of Patent: September 9, 2014Assignee: Genesis Photonics Inc.Inventors: Yun-Li Li, Chih-Ling Wu, Yi-Ru Huang, Yu-Yun Lo
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Patent number: 8831062Abstract: A semiconductor laser diode comprises a semiconductor body having an n-region and a p-region laterally spaced apart within the semiconductor body. The laser diode is provided with an active region between the n-region and the p-region having a front end and a back end section, an n-metallization layer located adjacent the n-region and having a first injector for injecting current into the active region, and a p-metallization layer opposite to the n-metallization layer and adjacent the p-region and having a second injector for injecting current into the active region. The thickness and/or width of at least one metallization layer is chosen so as to control the current injection in a part of the active region near at least one end of the active region compared to the current injection in another part of the active region. The width of the at least one metallization layer is larger than a width of the active region.Type: GrantFiled: April 6, 2011Date of Patent: September 9, 2014Assignee: II-VI Laser Enterprise GmbHInventors: Hans-Ulrich Pfeiffer, Andrew Cannon Carter, Jörg Troger, Norbert Lichtenstein, Michael Schwarz, Abram Jakubowicz, Boris Sverdlov
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Publication number: 20140248729Abstract: According to one embodiment, a semiconductor device includes a substrate and a stacked body on the substrate via a joining metal layer. The stacked body includes a device portion and a peripheral portion. The device portion includes from a bottommost layer to a topmost layer included in the stacked body. The peripheral portion surrounding and provided around the device portion; the peripheral portion is a portion of the bottommost layer to the topmost layer included in the stacked body and includes a portion of a semiconductor layer in contact with the joining metal layer.Type: ApplicationFiled: May 15, 2014Publication date: September 4, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Akihiro Fujiwara, Takashi Hakuno, Tokuhiko Matsunaga, Kimitaka Yoshimura, Katsufumi Kondo
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Patent number: 8823032Abstract: A light-emitting diode (LED) element is provided. The LED element includes a substrate, a diode structure layer and several light-guide structures. The light-guide structures are formed on at least one of the substrate and the diode structure layer. Each light-guide structure has an inner sidewall, and several spiral slits formed on the inner side wall.Type: GrantFiled: September 5, 2012Date of Patent: September 2, 2014Assignee: Industrial Technology Research InstituteInventors: Chun-Ting Chen, Wei-Chih Shen, Li-Wen Lai
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Patent number: 8809089Abstract: A disclosed method of manufacturing a surface emitting laser includes laminating a transparent dielectric layer on an upper surface of a laminated body; forming a first resist pattern on an upper surface of the dielectric layer, the first resist pattern including a pattern defining an outer perimeter of a mesa structure and a pattern protecting a region corresponding to one of the relatively high reflection rate part and the relatively low reflection rate part included in an emitting region; etching the dielectric layer by using the first resist pattern as an etching mask; and forming a second resist pattern protecting a region corresponding to an entire emitting region. These steps are performed before the mesa structure is formed.Type: GrantFiled: July 12, 2013Date of Patent: August 19, 2014Assignee: Ricoh Company, Ltd.Inventors: Hiroyoshi Shouji, Shunichi Sato, Akihiro Itoh, Kazuhiro Harasaka
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Patent number: 8802468Abstract: A semiconductor light emitting device includes a lower cladding layer, an active layer, and an AlGaAs upper cladding layer mounted on a GaAs substrate. The semiconductor light emitting device has a ridge structure including the AlGaAs upper cladding layer. The semiconductor light emitting device further includes an InGaAs etching stop layer provided in contact with the lower side of the AlGaAs upper cladding layer. The InGaAs etching stop layer has a band gap greater than that of the active layer.Type: GrantFiled: June 5, 2013Date of Patent: August 12, 2014Assignees: Fujitsu Limited, The University of TokyoInventors: Nobuaki Hatori, Tsuyoshi Yamamoto, Hisao Sudo, Yasuhiko Arakawa
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Publication number: 20140197373Abstract: A light-receiving device includes a light-receiving layer having an undoped multi-quantum well structure; a cap layer disposed on the light-receiving layer, the cap layer including a semiconductor layer doped with a p-type impurity; a mesa structure including the cap layer; a p-type region extending from the p-type semiconductor layer toward the light-receiving layer, the p-type region including the p-type impurity diffused from the semiconductor layer in the mesa structure; a p-n junction formed at an end of the p-type region; and an electrode disposed on the cap layer of the mesa structure. The mesa structure is defined by a trench surrounding the mesa. The trench has a bottom that reaches the vicinity of an upper surface of the light-receiving layer. The p-n junction is located in the light-receiving layer or at the boundary between the light-receiving layer and the cap layer disposed on the light-receiving layer.Type: ApplicationFiled: January 14, 2014Publication date: July 17, 2014Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Yasuhiro IGUCHI, Youichi NAGAI
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Patent number: 8774571Abstract: An optical device includes a substrate and a first optical waveguide including a mesa. The mesa includes a first lower clad layer portion, a first core layer portion, and a first upper clad layer portion. The first lower clad layer portion, the first core layer portion, and the first upper clad layer portion are disposed in this order from the substrate side. The optical device also includes a first etch stop layer configured to stop etching when the first optical waveguide is formed. The first etch stop layer being laminated over the substrate. The first optical waveguide is laminated on the first etch stop layer.Type: GrantFiled: August 21, 2012Date of Patent: July 8, 2014Assignee: Oclaro Japan, Inc.Inventors: Kazunori Shinoda, Shigeki Makino, Hideo Arimoto
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Publication number: 20140183590Abstract: A nitride semiconductor light emitting device and a method of manufacturing the same are disclosed. The nitride semiconductor light emitting device includes an n-type nitride layer; an active layer formed on the n-type nitride layer; a p-type nitride layer formed on the active layer; a current blocking pattern formed on the p-type nitride layer; a transparent conductive pattern formed to cover upper sides of the p-type nitride layer and the current blocking pattern, and having a contact hole through which a portion of the current blocking pattern is exposed; and a p-electrode pad formed on the current blocking pattern and the transparent conductive pattern, and directly connected to the current blocking pattern. The nitride semiconductor light emitting device can improve long term durability by securing excellent light scattering properties while enhancing adhesion of a p-electrode pad.Type: ApplicationFiled: December 20, 2013Publication date: July 3, 2014Applicant: ILJIN LED CO., LTD.Inventors: Seung-Yong KIM, Jeong-Woo HONG
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Patent number: 8765501Abstract: Methods of epitaxy of gallium nitride, and other such related films, and light emitting diodes on patterned sapphire substrates, and other such related substrates, are described.Type: GrantFiled: February 28, 2011Date of Patent: July 1, 2014Assignee: Applied Materials, Inc.Inventors: Jie Su, Tuoh-Bin Ng, Olga Kryliouk, Sang Won Kang, Jie Cui
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Patent number: 8766281Abstract: A light emitting diode chip includes a substrate, an epitaxial layer, two inclined plane units, and two electrode units. The substrate has top and bottom surfaces. The epitaxial layer is disposed on the top surface of the substrate. Each of the inclined plane units is inclined downwardly and outwardly from the epitaxial layer toward the bottom surface of the substrate, and includes an inclined sidewall formed on the epitaxial layer, and a substrate inclined wall formed on the substrate. Each of the electrode units includes an electrode disposed on the epitaxial layer, and a conductive portion extending from the electrode to the substrate inclined wall along corresponding one of the inclined plane units.Type: GrantFiled: December 13, 2012Date of Patent: July 1, 2014Assignees: Lite-On Electronics (Guangzhou) Limited, Lite-On Technology Corp.Inventor: Chih-Chiang Kao
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Patent number: 8759121Abstract: An LED array includes a substrate and a plurality of LEDs formed on the substrate. The LEDs are electrically connected with each other. Each of the LEDs includes a connecting layer, an n-type GaN layer, an active layer, and a p-type GaN layer formed on the substrate in sequence. The connecting layer is etchable by alkaline solution. A bottom surface of the n-type GaN layer which connects the connecting layer has a roughened exposed portion. The bottom surface of the n-type GaN layer has an N-face polarity. A method for manufacturing the LED array is also provided.Type: GrantFiled: December 9, 2011Date of Patent: June 24, 2014Assignee: Advanced Optoelectronic Technology, Inc.Inventors: Tzu-Chien Hung, Chia-Hui Shen
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Patent number: 8735194Abstract: Provided is a method of manufacturing a display apparatus, including forming a drive circuit and a light-emitting portion on a substrate in which the forming the light-emitting portion includes forming a transparent anode electrode for applying a charge to an emission layer, forming a first coating layer and a second coating layer on the transparent anode electrode, removing the first coating layer by etching using the second coating layer as a mask, and forming a layer including the emission layer on a part of the transparent anode electrode from which the first coating layer is removed. A surface of the transparent anode electrode becomes as clean as a surface cleaned with ultraviolet irradiation.Type: GrantFiled: October 1, 2008Date of Patent: May 27, 2014Assignee: Canon Kabushiki KaishaInventors: Kenji Takahashi, Masafumi Sano
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Patent number: 8728839Abstract: Some embodiments include methods of forming memory cells. Programmable material may be formed directly adjacent another material. A dopant implant may be utilized to improve adherence of the programmable material to the other material by inducing bonding of the programmable material to the other material, and/or by scattering the programmable material and the other material across an interface between them. The memory cells may include first electrode material, first ovonic material, second electrode material, second ovonic material and third electrode material. The various electrode materials and ovonic materials may join to one another at boundary bands having ovonic materials embedded in electrode materials and vice versa; and having damage-producing implant species embedded therein. Some embodiments include ovonic material joining dielectric material along a boundary band, with the boundary band having ovonic material embedded in dielectric material and vice versa.Type: GrantFiled: June 14, 2013Date of Patent: May 20, 2014Assignee: Micron Technology, Inc.Inventors: Camillo Bresolin, Valter Soncini, Davide Erbetta
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Patent number: 8728837Abstract: A method of forming an optical device includes generating a device precursor having a layer of a light-transmitting medium on a base. The method also includes forming an etch stop on the layer of light-transmitting medium. An active medium is grown on the etch stop and on the light-transmitting medium such that the light-transmitting medium is between the base and the grown active medium. The grown active medium is etched down to the etch stop so as to define a ridge in the active medium. The ridge of active medium defines a portion of a component waveguide that will guide a light signal through an active component on the device.Type: GrantFiled: May 23, 2012Date of Patent: May 20, 2014Assignee: Kotura, Inc.Inventors: Joan Fong, Wei Qian, Dazeng Feng, Mehdi Asghari
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Patent number: 8716044Abstract: A p-type cladding layer (3) of p-type semiconductor is formed over a substrate. An active layer (5) including a p-type semiconductor region is disposed over the p-type cladding layer. A buffer layer (10) of non-doped semiconductor is disposed over the active layer. A ridge-shaped n-type cladding layer (11) of n-type semiconductor is disposed over a partial surface of the buffer layer. The buffer layer on both sides of the ridge-shaped n-type cladding layer is thinner than the buffer layer just under the ridge-shaped n-type cladding layer.Type: GrantFiled: September 16, 2013Date of Patent: May 6, 2014Assignee: Fujitsu LimitedInventors: Tsuyoshi Yamamoto, Hisao Sudo
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Patent number: 8703512Abstract: A light emitting device may include a substrate, an n-type clad layer, an active layer, and a p-type clad layer. A concave-convex pattern having a plurality of grooves and a mesa between each of the plurality of grooves may be formed on the substrate, and a reflective layer may be formed on the surfaces of the plurality of grooves or the mesa between each of the plurality of grooves. Therefore, light generated in the active layer may be reflected by the reflective layer, and extracted to an external location.Type: GrantFiled: July 25, 2013Date of Patent: April 22, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-won Lee, Bok-ki Min, Jun-youn Kim, Young-jo Tak, Hyung-su Jeong
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Patent number: 8698190Abstract: A lighting device is formed using a light-emitting element by a more simplified method. The lighting device includes a light-emitting element including a light-emitting layer between a first electrode and a second electrode, a substrate provided with the light-emitting element and an uneven region around the periphery of the light-emitting element, a sealing substrate facing the substrate, connection electrodes connected to the first electrode and the second electrode and formed over the uneven region, and a sealant for bonding the substrate and the sealing substrate. The connection electrodes are each formed using a conductive paste, and the sealant is in contact with the connection electrodes and the uneven region provided around the periphery of the light-emitting element.Type: GrantFiled: June 7, 2012Date of Patent: April 15, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kohei Yokoyama, Hisao Ikeda, Shinichi Hirasa
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Patent number: 8686451Abstract: An optoelectronic component (100) comprises a first semiconductor layer stack (101), which has an active layer (110) designed for the emission of radiation and a main area (111). A separating layer (103) is arranged on said main area, said separating layer forming a semitransparent mirror. The optoelectronic component comprises a second semiconductor layer stack (102), which is arranged at the separating layer and which has a further active layer (120) designed for the emission of radiation.Type: GrantFiled: January 19, 2009Date of Patent: April 1, 2014Assignee: OSRAM Opto Semiconductor GmbHInventors: Nikolaus Gmeinwieser, Berthold Hahn
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Patent number: 8685805Abstract: Provided is a semiconductor device. The semiconductor device includes a semiconductor substrate, a first isolation dielectric pattern on the semiconductor substrate, and an active pattern on the first isolation dielectric pattern. A semiconductor pattern is interposed between the semiconductor substrate and the first isolation dielectric pattern, and a second isolation dielectric pattern is interposed between the semiconductor substrate and the semiconductor pattern. The semiconductor substrate and the semiconductor pattern are electrically connected by a connection pattern.Type: GrantFiled: August 11, 2011Date of Patent: April 1, 2014Assignee: Samsung Electronics Co., Ltd.Inventor: Chang-Woo Oh
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Patent number: 8686457Abstract: A light emitting element having a recess-protrusion structure on a substrate is provided. A semiconductor light emitting element 100 has a light emitting structure of a semiconductor 20 on a first main surface of a substrate 10. The first main surface of the substrate 10 has substrate protrusion portion 11, the bottom surface 14 of each protrusion is wider than the top surface 13 thereof in a cross-section, or the top surface 13 is included in the bottom surface 14 in a top view of the substrate. The bottom surface 14 has an approximately polygonal shape, and the top surface 13 has an approximately circular or polygonal shape with more sides than that of the bottom surface 14.Type: GrantFiled: February 5, 2013Date of Patent: April 1, 2014Assignee: Nichia CorporationInventors: Shunsuke Minato, Junya Narita, Yohei Wakai, Yukio Narukawa, Motokazu Yamada
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Patent number: 8679906Abstract: In one embodiment, there is an asymmetric multi-gated transistor that has a semiconductor fin with a non-uniform doping profile. A first portion of the fin has a higher doping concentration while a second portion of the fin has a lower doping concentration. In another embodiment, there is an asymmetric multi-gated transistor with gate dielectrics formed on the semiconductor fin that vary in thickness. This asymmetric multi-gated transistor has a thin gate dielectric formed on a first side portion of the semiconductor fin and a thick gate dielectric formed on a second side portion of the fin.Type: GrantFiled: November 4, 2009Date of Patent: March 25, 2014Assignee: International Business Machines CorporationInventor: Kangguo Cheng
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Patent number: 8679881Abstract: A growth method for reducing defect density of GaN includes steps of: sequentially forming a buffer growth layer, a stress release layer and a first nanometer cover layer on a substrate, wherein the first nanometer cover layer has multiple openings interconnected with the stress release layer; growing a first island in each of the openings; growing a first buffer layer and a second nanometer cover layer on the first island; and growing a second island to form a dislocated island structure. Thus, through the first nanometer cover layer and the second nanometer cover layer, multiple dislocated island structures can be directly formed to reduce manufacturing complexity as well as increase yield rate by decreasing manufacturing environment variation. Further, the epitaxial lateral over growth (ELOG) approach also effectively enhances characteristics of GaN optoelectronic semiconductor elements.Type: GrantFiled: July 3, 2013Date of Patent: March 25, 2014Assignee: Tekcore Co., Ltd.Inventors: Jen-Inn Chyi, Lung-Chieh Cheng, Hsueh-Hsing Liu, Geng-Yen Lee
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Patent number: 8679986Abstract: Provided is a method for manufacturing a semiconductor device so as not expose a semiconductor layer to moisture and the number of masks is reduced. For example, a first conductive film, a first insulating film, a semiconductor film, a second conductive film, and a mask film are formed. The first mask film is processed to form a first mask layer. Dry etching is performed on the first insulating film, the semiconductor film, and the second conductive film with the use of the first mask layer to form a thin film stack body, so that a surface of the first conductive film is at least exposed. Sidewall insulating layers covering side surfaces of the thin film stack body are formed. The first conductive film is side-etched to form a first electrode. A second electrode layer is formed with the second mask layer.Type: GrantFiled: September 24, 2011Date of Patent: March 25, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Takafumi Mizoguchi, Kojiro Shiraishi
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Publication number: 20140077234Abstract: An apparatus comprises a substrate, a first buried layer formed over the substrate, the first buried layer comprising one or more raised mesa structures, a second buried layer formed over the first buried layer, an active layer formed over the second buried layer, and a capping layer formed over the active layer. The apparatus may further comprise a third buried layer formed over the active layer, the third buried layer comprising one or more raised mesa structures, and a fourth buried layer formed over the third buried layer. The one or more raised mesa structures of the first buried layer may be offset from the one or more raised mesa structures of the third buried layer.Type: ApplicationFiled: September 14, 2012Publication date: March 20, 2014Applicant: LSI CorporationInventor: Joseph M. Freund
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Patent number: 8664086Abstract: A method for manufacturing a semiconductor thin film device includes: forming a buffer layer on an Si (111) substrate and a single crystal semiconductor layer on the buffer layer; forming an island including the semiconductor layer, buffer layer, and a portion of the substrate; forming a coating layer on the island; etching the substrate along its Si (111) plane to release the island from the substrate, the coating layer serving as a mask; and bonding the released island to another substrate, a released surface of the released island contacting the another substrate. A semiconductor device includes a single crystal semiconductor layer other than Si, which has a semiconductor device formed on a front surface of an Si (111) layer lying in a (111) plane. The layer is bonded to another substrate with a back surface contacting the another substrate or a bonding layer formed on the another substrate.Type: GrantFiled: April 27, 2010Date of Patent: March 4, 2014Assignee: Oki Data CorporationInventor: Mitsuhiko Ogihara
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Patent number: 8647901Abstract: There is provided a method of forming a nitride semiconductor layer, including the steps of firstly providing a substrate on which a patterned epitaxy layer with a pier structure is formed. A protective layer is then formed on the patterned epitaxy layer, exposing a top surface of the pier structure. Next, a nitride semiconductor layer is formed over the patterned epitaxy layer connected to the nitride semiconductor layer through the pier structure, wherein the nitride semiconductor layer, the pier structure, and the patterned epitaxy layer together form a space exposing a bottom surface of the nitride semiconductor layer. Thereafter, a weakening process is performed to remove a portion of the bottom surface of the nitride semiconductor layer and to weaken a connection point between the top surface of the pier structure and the nitride semiconductor layer. Finally, the substrate is separated from the nitride semiconductor layer through the connection point.Type: GrantFiled: June 11, 2008Date of Patent: February 11, 2014Assignee: Industrial Technology Research InstituteInventors: Yih-Der Guo, Chih-Ming Lai, Jenq-Dar Tsay, Po-Chun Liu
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Patent number: 8633041Abstract: A method for manufacturing a quantum cascade laser includes the steps of forming a semiconductor stacked structure including a first semiconductor region and a second semiconductor region; forming an etching mask having a striped pattern on the second semiconductor region; forming a semiconductor mesa structure having a mesa shape in cross section by etching the first and second semiconductor regions using the etching mask; forming an insulating layer over a top portion and side surfaces of the semiconductor mesa structure and the first semiconductor region; forming an opening in a portion of the insulating layer that is disposed on the top portion of the semiconductor mesa structure; and forming an electrode over the inside of the opening of the insulating layer, the top portion and side surfaces of the semiconductor mesa structure, and the first semiconductor region.Type: GrantFiled: May 17, 2012Date of Patent: January 21, 2014Assignee: Sumitomo Electric Industries, Ltd.Inventor: Yukihiro Tsuji
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Patent number: 8628988Abstract: A method of fabricating a semiconductor laser device by forming a semiconductor structure at least part of which is in the form of a mesa structure having a flat top. The steps include depositing a passivation layer over the mesa structure, forming a contact opening in the passivation layer on the flat top of the mesa structure; and depositing a metal contact portion, with the deposited metal contact portion contacting the semiconductor structure via the contact opening. The contact opening formed through the passivation layer has a smaller area than the flat top of the mesa structure to allow for wider tolerances in alignment accuracy. The metal contact portion comprises a platinum layer between one or more gold layers to provide an effective barrier against Au diffusion into the semiconductor material.Type: GrantFiled: December 21, 2011Date of Patent: January 14, 2014Assignee: Emcore CorporationInventors: Jia-Sheng Huang, Phong Thai
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Publication number: 20140008609Abstract: A method of fabricating a light emitting device, comprising: providing a substrate; forming an undoped semiconductor layer on the substrate; forming a patterned metal layer on the undoped semiconductor layer; using the patterned metal layer as a mask to etch the undoped semiconductor layer and forming a plurality of nanorods on the substrate; and forming an light emitting stack on the plurality of nanorods to form a plurality of voids between the light emitting stack and the plurality of nanorods.Type: ApplicationFiled: July 2, 2013Publication date: January 9, 2014Inventors: Ching Hsueh Chiu, Po Min Tu, Hao Chung Kuo, Chun Yen Chang, Shing Chung Wang
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Patent number: 8617912Abstract: A method for manufacturing a semiconductor laser includes the steps of preparing a mold with a pattern surface having recesses, forming a stacked semiconductor layer including a grating layer, forming a resin part on the grating layer, forming a resin pattern portion on the resin part, forming a diffraction grating by etching the grating layer using the resin part as a mask, and forming a mesa-structure on the stacked semiconductor layer. Each of the recesses includes two end portions and a middle portion between the two end portions. A depth of at least one of the two end portions from the pattern surface is greater than that of the middle portion. The step of forming the mesa-structure includes the step of etching the stacked semiconductor layer so as to remove end portions of the diffraction grating in a direction orthogonal to a periodic direction thereof.Type: GrantFiled: June 21, 2012Date of Patent: December 31, 2013Assignee: Sumitomo Electric Industries, Ltd.Inventor: Masaki Yanagisawa
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Publication number: 20130343417Abstract: An optical semiconductor device includes: a semiconductor substrate; a semiconductor laser part on the semiconductor substrate and having a vertical ridge; and an optical modulator part on the semiconductor substrate, having an inverted-mesa ridge, and modulating light emitted by the semiconductor laser part.Type: ApplicationFiled: February 28, 2013Publication date: December 26, 2013Applicant: Mitsubishi Electric CorporationInventor: Kazuhisa Takagi
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Patent number: 8609447Abstract: A disclosed method of manufacturing a surface emitting laser includes laminating a transparent dielectric layer on an upper surface of a laminated body; forming a first resist pattern on an upper surface of the dielectric layer, the first resist pattern including a pattern defining an outer perimeter of a mesa structure and a pattern protecting a region corresponding to one of the relatively high reflection rate part and the relatively low reflection rate part included in an emitting region; etching the dielectric layer by using the first resist pattern as an etching mask; and forming a second resist pattern protecting a region corresponding to an entire emitting region. These steps are performed before the mesa structure is formed.Type: GrantFiled: March 15, 2010Date of Patent: December 17, 2013Assignee: Ricoh Company, Ltd.Inventors: Hiroyoshi Shouji, Shunichi Sato, Akihiro Itoh, Kazuhiro Harasaka
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Patent number: 8604497Abstract: A radiation-emitting thin-film semiconductor chip with an epitaxial multilayer structure (12), which contains an active, radiation-generating layer (14) and has a first main face (16) and a second main face (18)—remote from the first main face—for coupling out the radiation generated in the active, radiation-generating layer. Furthermore, the first main face (16) of the multilayer structure (12) is coupled to a reflective layer or interface, and the region (22) of the multilayer structure that adjoins the second main face (18) of the multilayer structure is patterned one- or two-dimensionally with convex elevations (26).Type: GrantFiled: September 26, 2003Date of Patent: December 10, 2013Assignee: OSRAM Opto Semiconductors GmbHInventors: Dominik Eisert, Berthold Hahn, Volker Härle
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Patent number: 8598447Abstract: Provided is a photoelectric conversion device in which the conductivity after hydrogen-plasma exposure is set within an appropriate range, thereby suppressing the leakage current and improving the conversion efficiency. A photoelectric conversion device includes, on a substrate, a photoelectric conversion layer having at least two power generation cell layers, and an intermediate contact layer provided between the power generation cell layers. The intermediate contact layer mainly contains a compound represented by Zn1-xMgxO (0.096?x?0.183).Type: GrantFiled: August 20, 2009Date of Patent: December 3, 2013Assignee: Mitsubishi Heavy Industries, Ltd.Inventors: Kengo Yamaguchi, Satoshi Sakai, Shigenori Tsuruga
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Patent number: 8592843Abstract: Embodiments relate to a light emitting device, a light emitting device package, and a lighting system. The light emitting device comprises: a light emitting structure including a first conductive type semiconductor layer, an active layer over the first conductive type semiconductor layer, and a second conductive type semiconductor layer over the active layer; a dielectric layer formed in each of a plurality of cavities defined by removing a portion of the light emitting structure; and a second electrode layer over the dielectric layer.Type: GrantFiled: October 21, 2010Date of Patent: November 26, 2013Assignee: LG Innotek Co., Ltd.Inventor: Sung Min Hwang
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Patent number: 8580591Abstract: The invention concerns a method of manufacturing a vertical PIN diode comprising: providing an epitaxial wafer comprising a vertically stacked N-type layer, intrinsic layer and P-type layer; forming an anode contact of the vertical PIN diode by forming an anode metallization on a first portion of the P-type layer defining an anode region; forming an electrically insulating layer around the anode region such that a first portion of the intrinsic layer extends vertically between the N-type layer and the anode region and second portions of the intrinsic layer extend vertically between the N-type layer and the electrically insulating layer; forming a trench in the electrically insulating layer and in the second portions of the intrinsic layer so as to expose a portion of the N-type layer defining a cathode region and to define a sacrificial side-guard ring consisting of a portion of the electrically insulating layer that extends laterally between the trench and the anode region and laterally surrounds said anodeType: GrantFiled: June 28, 2011Date of Patent: November 12, 2013Assignee: Selex Sistemi Integrati S.p.A.Inventors: Marco Peroni, Alessio Pantellini
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Patent number: 8569115Abstract: A compliant bipolar micro device transfer head array and method of forming a compliant bipolar micro device transfer array from an SOI substrate are described. In an embodiment, a compliant bipolar micro device transfer head array includes a base substrate and a patterned silicon layer over the base substrate. The patterned silicon layer may include first and second silicon interconnects, and first and second arrays of silicon electrodes electrically connected with the first and second silicon interconnects and deflectable into one or more cavities between the base substrate and the silicon electrodes.Type: GrantFiled: July 6, 2012Date of Patent: October 29, 2013Assignee: LuxVue Technology CorporationInventors: Dariusz Golda, Andreas Bibl
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Patent number: 8563334Abstract: A Light-Emitting Diode (LED) is formed on a sapphire substrate that is removed from the LED by grinding and then etching the sapphire substrate. The sapphire substrate is ground first to a first specified thickness using a single abrasive or multiple abrasives. The remaining sapphire substrate is removed by dry etching or wet etching.Type: GrantFiled: September 14, 2010Date of Patent: October 22, 2013Assignee: TSMC Solid State Lighting Ltd.Inventors: Hung-Wen Huang, Hsing-Kuo Hsia, Ching-Hua Chiu
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Patent number: 8558243Abstract: A micro light emitting diode (LED) and a method of forming an array of micro LEDs for transfer to a receiving substrate are described. The micro LED structure may include a micro p-n diode and a metallization layer, with the metallization layer between the micro p-n diode and a bonding layer. A conformal dielectric barrier layer may span sidewalls of the micro p-n diode. The micro LED structure and micro LED array may be picked up and transferred to a receiving substrate.Type: GrantFiled: December 7, 2012Date of Patent: October 15, 2013Assignee: LuxVue Technology CorporationInventors: Andreas Bibl, John A. Higginson, Hung-Fai Stephen Law, Hsin-Hua Hu
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Publication number: 20130267054Abstract: A semiconductor light emitting device includes a lower cladding layer, an active layer, and an AlGaAs upper cladding layer mounted on a GaAs substrate. The semiconductor light emitting device has a ridge structure including the AlGaAs upper cladding layer. The semiconductor light emitting device further includes an InGaAs etching stop layer provided in contact with the lower side of the AlGaAs upper cladding layer. The InGaAs etching stop layer has a band gap greater than that of the active layer.Type: ApplicationFiled: June 5, 2013Publication date: October 10, 2013Inventors: Nobuaki Hatori, Tsuyoshi Yamamoto, Hisao Sudo, Yasuhiko Arakawa
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Patent number: 8552436Abstract: A micro light emitting diode (LED) and a method of forming an array of micro LEDs for transfer to a receiving substrate are described. The micro LED structure may include a micro p-n diode and a metallization layer, with the metallization layer between the micro p-n diode and a bonding layer. A conformal dielectric barrier layer may span sidewalls of the micro p-n diode. The micro LED structure and micro LED array may be picked up and transferred to a receiving substrate.Type: GrantFiled: December 7, 2012Date of Patent: October 8, 2013Assignee: LuxVue Technology CorporationInventors: Andreas Bibl, John A. Higginson, Hung-Fai Stephen Law, Hsin-Hua Hu
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Publication number: 20130244363Abstract: A method for producing an optical semiconductor device includes the steps of forming a semiconductor structure; forming a mask on the semiconductor structure; etching the semiconductor structure with the mask to form first and second stripe-shaped grooves and a mesa portion; forming a protective film on a top surface and side surfaces of the mesa portion; forming a resin portion on the protective film; etching the resin portion and the protective film formed on the top surface; forming an upper electrode on the top surface; and forming an electrical interconnection on the resin portion. The resin portion has an inclined surface region that rises from a first point above the mesa portion toward a second point above the first stripe-shaped groove. The step of etching the resin portion and the protective film includes the substeps of etching the resin portion and simultaneously etching the resin portion and the protective film.Type: ApplicationFiled: March 7, 2013Publication date: September 19, 2013Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Yoshihiro YONEDA, Hirohiko KOBAYASHI, Ryuji MASUYAMA
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Patent number: 8530358Abstract: The present invention discloses a manufacturing method of vertical cavity surface emitting laser. The method includes following steps: providing a substrate; forming an epitaxial layer stack including an aluminum-rich layer; forming an ion-doping mask including a ring-shaped opening; doping ions in the epitaxial layer stack through the ring-shaped opening and forming a ring-shaped ion-doped region over the aluminum-rich layer; forming an etching mask on the ion-doping mask for covering the ring-shaped opening of the ion-doping mask; etching the epitaxial layer stack through the etching mask and ion-doping mask for forming an island platform; oxidizing the aluminum-rich layer for forming a ring-shaped oxidized region. In addition, the present invention also discloses a vertical cavity surface emitting laser manufactured by the above mentioned method.Type: GrantFiled: September 13, 2011Date of Patent: September 10, 2013Assignee: True Light CorporationInventors: Po-Han Chen, Cheng-Ju Wu, Jin-Shan Pan
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Patent number: 8525201Abstract: A light emitting device may include a substrate, an n-type clad layer, an active layer, and a p-type clad layer. A concave-convex pattern having a plurality of grooves and a mesa between each of the plurality of grooves may be formed on the substrate, and a reflective layer may be formed on the surfaces of the plurality of grooves or the mesa between each of the plurality of grooves. Therefore, light generated in the active layer may be reflected by the reflective layer, and extracted to an external location.Type: GrantFiled: May 27, 2010Date of Patent: September 3, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-won Lee, Bok-ki Min, Jun-youn Kim, Young-jo Tak, Hyung-su Jeong
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Patent number: 8525150Abstract: A semiconductor light emission device is disclosed. The semiconductor light emission device includes: a substrate; a current concentration preventing pattern formed in a mesh net shape on the substrate; an n-type clad layer formed on the substrate loaded with the current concentration preventing pattern; an active layer and a p-type clad layer sequentially formed on the n-type clad layer; an n-type electrode formed on a part of the n-type clad layer which is exposed by partially etching the p-type clad layer and active layer; and a p-type electrode formed on the p-type clad layer. The current concentration preventing pattern is formed in a double layer structure which includes a first layer formed from one material of SiO and SiN and on the substrate, and a second layer formed from a metal material and on the first layer.Type: GrantFiled: October 20, 2010Date of Patent: September 3, 2013Assignee: LG Display Co., Ltd.Inventors: Min Ki Yoo, Koo Hwa Lee, Rok Hee Lee, Geun Woo Lee