Mesa Formation Patents (Class 438/39)
  • Publication number: 20110298006
    Abstract: A semiconductor light emitting device includes a nitride semiconductor layer including a first cladding layer, an active layer, and a second cladding layer, and a current blocking layer configured to selectively inject a current into the active layer. The second cladding layer has a stripe-shaped ridge portion. The current blocking layer is formed in regions on both sides of the ridge portion, and is made of zinc oxide having a crystalline structure.
    Type: Application
    Filed: June 15, 2011
    Publication date: December 8, 2011
    Applicant: PANASONIC CORPORATION
    Inventors: Hiroyuki HAGINO, Hiroshi OHNO, Kazuhiko YAMANAKA, Nobuaki NAGAO, Takahiro HAMADA
  • Publication number: 20110274130
    Abstract: The present disclosure relates to a diode laser and a method for producing the same. In one embodiment, the diode laser, comprises a passive pedestal layer structure, an active ridge layer structure positioned over the passive pedestal layer structure, a p-contact contacting a top side of the active ridge layer structure, a first n-contact disposed on a first side of the active ridge layer structure, a second n-contact disposed on a second side of the active ridge layer structure and, an n-final-metal layer connecting the first n-contact metal and the second n-contact metal, wherein the n-final-metal layer is continuous over the active ridge layer structure.
    Type: Application
    Filed: April 29, 2011
    Publication date: November 10, 2011
    Inventors: Joseph Hy Abeles, Zane Alan Shellenbarger, Winston Kong Chan, Alan Michael Braun
  • Patent number: 8053262
    Abstract: A method for manufacturing a nitride semiconductor laser element having a nitride semiconductor layer including at least an active layer provided on a substrate, a pair of cavity planes formed on the nitride semiconductor layer, and a protruding part where part of the substrate protrudes from said cavity plane, said method comprises: a step of forming the nitride semiconductor layer on the substrate; a first etching step of forming a first groove by etching at least the nitride semiconductor layer; and a second etching step of forming the cavity plane, in the second etching step, the inner wall of the first groove and part of the nitride semiconductor layer surface adjacent to the first groove are etched to form a second groove, and form the upper face of the protruding part.
    Type: Grant
    Filed: April 28, 2009
    Date of Patent: November 8, 2011
    Assignee: Nichia Corporation
    Inventor: Shingo Tanisaka
  • Publication number: 20110263061
    Abstract: There is provided a semiconductor light emitting device having a patterned substrate and a manufacturing method of the same. The semiconductor light emitting device includes a substrate; a first conductivity type nitride semiconductor layer, an active layer and a second conductivity type nitride semiconductor layer sequentially formed on the substrate, wherein the substrate is provided on a surface thereof with a pattern having a plurality of convex portions, wherein out of the plurality of convex portions of the pattern, a distance between a first convex portion and an adjacent one of the convex portions is different from a distance between a second convex portion and an adjacent one of the convex portions.
    Type: Application
    Filed: July 5, 2011
    Publication date: October 27, 2011
    Applicant: SAMSUNG LED CO., LTD.
    Inventors: Sun Woon KIM, Hyun Kyung Kim, Hyung Ky Back, Jae Ho Han
  • Publication number: 20110261848
    Abstract: A method of manufacturing an optical semiconductor device includes: forming a mesa structure having an n-type cladding layer, an active layer and a p-type cladding layer in this order on a substrate; forming a p-type semiconductor layer on a side face of the mesa structure and a plane area located at both sides of the mesa structure, the p-type semiconductor layer having a thickness of 5 nm to 45 nm on the plane area; and forming a current blocking semiconductor layer on the p-type semiconductor layer so as to bury the mesa structure, a product of the thickness of the p-type semiconductor layer and a concentration of p-type impurity of the p-type semiconductor layer on the plane area being 2.5×1019 nm/cm3 or less.
    Type: Application
    Filed: April 25, 2011
    Publication date: October 27, 2011
    Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Tatsuya Takeuchi
  • Publication number: 20110261852
    Abstract: A semiconductor laser element includes a first electrode, a second electrode, a first reflecting mirror, a second reflecting mirror, and a resonator. The resonator includes an active layer, a current confinement layer, a first semiconductor layer having a first doping concentration formed at a side opposite to the active layer across the current confinement layer, and a second semiconductor layer having a second doping concentration higher than the first doping concentration formed between the first semiconductor layer and the current confinement layer. The first electrode is provided to contact a part of a surface of the first semiconductor layer. The first semiconductor layer has a diffusion portion into which a component of the first electrode diffuses. The second semiconductor layer contacts the diffusion portion. The second semiconductor layer is positioned at a node of a standing wave at a time of laser oscillation of the semiconductor laser element.
    Type: Application
    Filed: December 10, 2009
    Publication date: October 27, 2011
    Applicant: FURUKAWA ELECTRIC CO., LTD
    Inventors: Suguru Imai, Keishi Takaki, Norihiro Iwai, Kinuka Tanabe, Hitoshi Shimizu, Hirotatsu Ishii
  • Publication number: 20110261855
    Abstract: A method of manufacturing an optical semiconductor device including: forming a mesa structure including a first conductivity type cladding layer, an active layer and a second conductivity type cladding layer in this order on a first conductivity type semiconductor substrate, an upper most surface of the mesa structure being constituted of an upper face of the second conductivity type cladding layer; growing a first burying layer burying both sides of the mesa structure at higher position than the active layer; forming an depressed face by etching both edges of the upper face of the second conductivity type cladding layer; and growing a second burying layer of the first conductivity type on the depressed face of the second conductivity type cladding layer and the first burying layer.
    Type: Application
    Filed: April 26, 2011
    Publication date: October 27, 2011
    Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventors: Tatsuya Takeuchi, Taro Hasegawa
  • Patent number: 8044381
    Abstract: A light-emitting diode (LED) includes a p-type layer, an n-type layer, and an active layer arranged between the p-type layer and the n-type layer. The active layer includes at least one quantum well adjacent to at least one modulation-doped layer. Alternatively, or in addition thereto, at least one surface of the n-type layer or the p-type layer is texturized to form a textured surface facing the active layer.
    Type: Grant
    Filed: July 30, 2007
    Date of Patent: October 25, 2011
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Michael Renne Ty Tan, Shih-Yuan Wang, Alexandre M. Bratkovski, David A. Fattal
  • Publication number: 20110256651
    Abstract: A light-emitting device comprises a lattice structure to minimize the horizontal waveguide effect by reducing light traveling distance in the light-absorption medium of the light-emitting devices, and to enhance light extraction from the light-emitting layer. The lattice structure includes sidewalls and/or rods embedded in the light-absorption medium and dividing the light-absorption medium into a plurality of area units. The area units are completely isolated or partially separated from each other by the sidewalls. Also provided is a method of fabricating a light-emitting device that comprises a lattice structure, which lattice structure includes sidewalls and/or rods embedded in the light-absorption medium and dividing the light-absorption medium into a plurality of area units.
    Type: Application
    Filed: August 20, 2010
    Publication date: October 20, 2011
    Applicant: INVENLUX CORPORATION
    Inventors: CHUNHUI YAN, JIANPING ZHANG
  • Patent number: 8039282
    Abstract: In a method of fabricating a semiconductor optical device, a semiconductor region is formed by growing an InP lower film, a active region, an InP upper film and a capping film on a substrate sequentially. Material of the capping film is different from that of InP. Next, a mask is formed on the capping film, and the semiconductor region is etched using the mask to form a semiconductor stripe mesa, which includes an InP lower cladding layer, a active layer, an InP upper cladding layer and a capping layer. The active layer comprises aluminum-based III-V compound. A width of the top surface of the capping layer is greater than that of a width of the bottom surface of the capping layer. A width of the top surface of the InP upper cladding layer is smaller than that of the bottom surface of the InP upper cladding layer. The minimum width of the semiconductor mesa is in the InP upper cladding layer.
    Type: Grant
    Filed: March 30, 2009
    Date of Patent: October 18, 2011
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Manabu Yoshimura, Nobuyuki Ikoma, Kenji Hiratsuka
  • Patent number: 8034648
    Abstract: Optimizing the regrowth over epitaxial layers during manufacture of a distributed feedback laser. In one example embodiment, a method for depositing an InP regrowth layer on an epitaxial base portion of a distributed feedback laser includes growing a first portion of the regrowth layer at an initial substrate temperature of approximately 580 degrees Celsius to a thickness between approximately 300 Angstroms and approximately 900 Angstroms, increasing the substrate temperature from the initial substrate temperature to an increased substrate temperature of approximately 660 degrees Celsius, growing a second portion of the regrowth layer at the increased substrate temperature, doping a first part of an uppermost layer of the regrowth layer at a concentration of approximately 8.00*10^17/cm3 at the increased substrate temperature, and doping a second part of the uppermost layer of the regrowth layer at a concentration between approximately 1.90*10^18/cm3 and approximately 2.
    Type: Grant
    Filed: May 15, 2007
    Date of Patent: October 11, 2011
    Assignee: Finisar Corporation
    Inventors: Yuk Lung Ha, David Bruce Young, Ashish Verma, Roman Dimitrov
  • Patent number: 8026156
    Abstract: In a method for fabricating a nitride-based compound layer, first, a GaN substrate is prepared. A mask layer with a predetermined pattern is formed on the GaN substrate to expose a partial area of the GaN substrate. Then a buffer layer is formed on the partially exposed GaN substrate. The buffer layer is made of a material having a 10% or less lattice mismatch with GaN. Thereafter, the nitride-based compound is grown laterally from a top surface of the buffer layer toward a top surface of the mask layer and the nitride-based compound layer is vertically grown to a predetermined thickness. Also, the mask layer and the buffer layer are removed via wet-etching to separate the nitride-based compound layer from the GaN substrate.
    Type: Grant
    Filed: June 23, 2009
    Date of Patent: September 27, 2011
    Assignee: Samsung LED Co., Ltd.
    Inventors: Soo Min Lee, Cheol Kyu Kim, Jaeun Yoo, Sung Hwan Jang, Masayoshi Koike
  • Publication number: 20110220867
    Abstract: A light emitting device with an ultraviolet light-emitting structure having a first layer with a first conductivity, a second layer with a second conductivity; and a light emitting quantum well region between the first layer and second layer. A first electrical contact is in electrical connection with the first layer and a second electrical contact is in electrical connection with the second layer. A template serves as a platform for the light-emitting structure. The template has a micro-undulated buffer layer with AlxInyGa1-x-yN, wherein 0<x?1, 0?y?1 and 0<x+y?1, and a second buffer layer over the micro-undulated buffer layer. The second buffer layer is made of AlxInyGa1-x-yN, wherein 0<x?1, 0?y?1, 0<x+y?1. When an electrical potential is applied to the first electrical contact and the second electrical contact the device emits ultraviolet light.
    Type: Application
    Filed: March 27, 2009
    Publication date: September 15, 2011
    Inventors: Asif Khan, Qhalid Fareed
  • Publication number: 20110215294
    Abstract: According to one embodiment, a semiconductor light emitting device, including a light emission portion including a first semiconductor layer with a first conductive type, a light emission layer on the first semiconductor layer, a second semiconductor layer with a second conductive type on the light emission layer and a transparent electrode on the second semiconductor layer, and a plurality of light outlet holes inside the light emission portion, the plurality of light outlet holes communicating with the first semiconductor layer from a surface side of the transparent electrode, at least a part of light emitted from the light emission layer being extracted from the plurality of the outlet holes to outside.
    Type: Application
    Filed: February 11, 2011
    Publication date: September 8, 2011
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Takeyuki SUZUKI, Hidefumi YASUDA, Yuko KATO
  • Patent number: 8012779
    Abstract: A vertical GaN-based LED comprises an n-electrode; an n-type GaN layer formed under the n-electrode, the n-type GaN layer having an irregular-surface structure which includes a first irregular-surface structure having irregularities formed at even intervals and a second irregular-surface structure having irregularities formed at uneven intervals, the second irregular-surface structure being formed on the first irregular-surface structure; an active layer formed under the n-type GaN layer; a p-type GaN layer formed under the active layer; a p-electrode formed under the p-type GaN layer; and a structure support layer formed under the p-electrode.
    Type: Grant
    Filed: July 24, 2007
    Date of Patent: September 6, 2011
    Assignee: Samsung LED Co., Ltd.
    Inventors: Seok Beom Choi, Bang Won Oh, Jong Gun Woo, Doo Go Baik
  • Patent number: 8008685
    Abstract: Provided are a light emitting device, a method of manufacturing the light emitting device, a light emitting device package, and a lighting system. The light emitting device comprises a light emitting structure layer including a first conductive type semiconductor layer, a second conductive type semiconductor layer, an active layer between the first conductive type semiconductor layer and the second conductive type layer. At least one lateral surface of the light emitting structure layer has cleavage planes of an A-plane and an M-plane.
    Type: Grant
    Filed: January 7, 2011
    Date of Patent: August 30, 2011
    Assignee: LG Innotek Co., Ltd.
    Inventor: Dae Sung Kang
  • Patent number: 8008101
    Abstract: The present invention relates to a gallium nitride (GaN) compound semiconductor light emitting element (LED) and a method of manufacturing the same. The present invention provides a vertical GaN LED capable of improving the characteristics of a horizontal LED by means of a metallic protective film layer and a metallic support layer. According to the present invention, a thick metallic protective film layer with a thickness of at least 10 microns is formed on the lateral and/or bottom sides of the vertical GaN LED to protect the element against external impact and to easily separate the chip. Further, a metallic substrate is used instead of a sapphire substrate to efficiently release the generated heat to the outside when the element is operated, so that the LED can be suitable for a high-power application and an element having improved optical output characteristics can also be manufactured. A metallic support layer is formed to protect the element from being distorted or damaged due to impact.
    Type: Grant
    Filed: January 28, 2010
    Date of Patent: August 30, 2011
    Assignees: Seoul Opto Device Co., Ltd., Postech Foundation
    Inventor: Jong-Lam Lee
  • Patent number: 7998771
    Abstract: Provided is a method of manufacturing a light emitting diode using a nitride semiconductor, which including the steps of: forming n- and p-type current spreading layers using a hetero-junction structure; forming trenches by dry-etching the n- and p-type current spreading layers; forming an n-type metal electrode layer in the trench of the n-type current spreading layer; forming a p-type metal electrode layer in the trench of the p-type current spreading layer; and forming a transparent electrode layer on the p-type metal electrode layer, thereby improving current spreading characteristics as compared with the conventional method of manufacturing the light emitting diode, and enhancing operating characteristics of the light emitting diode.
    Type: Grant
    Filed: November 26, 2007
    Date of Patent: August 16, 2011
    Assignee: Electronics and Telecommunications Research Institute
    Inventor: Sung Bum Bae
  • Patent number: 7998770
    Abstract: A semiconductor light-emitting device with a new layer structure is disclosed, where the current leaking path is not caused to enhance the current injection efficiency within the active layer. The device provides a mesa structure containing active layer and a p-type lower cladding layer on a p-type substrate and a burying layer doped with iron (Fe) to bury the mesa structure, where the burying layer shows a semi-insulating characteristic. The device also provides an n-type blocking layer arranged so as to cover at least a portion of the p-type buffer lower within the mesa structure. The n-type blocking layer prevents the current leaking from the burying layer to the p-type buffer layer, and the semi-insulating burying layer that covers the rest portion of the mesa structure not covered by the n-type blocking layer prevents the current leaking from the n-type blocking layer to the n-type cladding layer within the mesa structure.
    Type: Grant
    Filed: May 16, 2008
    Date of Patent: August 16, 2011
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Atsushi Matsumura, Tomokazu Katsuyama
  • Patent number: 7998761
    Abstract: The present invention relates to a light emitting diode with enhanced luminance and light emitting performance due to increase in efficiency of current diffusion into an ITO layer, and a method of fabricating the light emitting diode. According to the present invention, there is manufactured at least one light emitting cell including an N-type semiconductor layer, an active layer and a P-type semiconductor layer on a substrate. The method of the present invention comprises the steps of (a) forming at least one light emitting cell with an ITO layer formed on a top surface of the P-type semiconductor layer; (b) forming a contact groove for wiring connection in the ITO layer through dry etching; and (c) filling the contact groove with a contact connection portion made of a conductive material for the wiring connection.
    Type: Grant
    Filed: December 8, 2006
    Date of Patent: August 16, 2011
    Assignee: Seoul Opto Device Co., Ltd.
    Inventors: Dae Won Kim, Yeo Jin Yoon, Duck Hwan Oh, Jong Hwan Kim
  • Patent number: 7999340
    Abstract: An apparatus and method for forming optical black pixels having uniformly low dark current. Optical Black opacity is increased without having to increase Ti/TiN layer thickness. A hybrid approach is utilized combining a Ti/TiN OB layer in conjunction with in-pixel metal stubs that further occlude the focal radius of each pixel's incoming light beam. Additional metal layers can be used to increase the opacity into the infrared region.
    Type: Grant
    Filed: March 7, 2007
    Date of Patent: August 16, 2011
    Assignee: AltaSens, Inc.
    Inventors: Giuseppe Rossi, Lester Kozlowski, Henry Lin, John Richardson, Gregory Chow, Gaurang Patel
  • Publication number: 20110193126
    Abstract: A semiconductor light-emitting element comprises: a semiconductor substrate; a semiconductor laminated structure including a first conductivity-type semiconductor layer, an active layer, a second conductivity-type semiconductor layer, and a contact layer that are sequentially laminated on the semiconductor substrate; a ridge portion in an upper portion of the semiconductor laminated structure; a channel portion adjoining opposite sides of the ridge portion; a terrace portion adjoining opposite sides of the channel portion and, with the channel portion, sandwiching the ridge portion; a first insulating film covering the channel portion and having openings on the ridge portion and the terrace portion; a single-layer adhesive layer on the first insulating film; a Pd electrode on the ridge portion and a part of the single-layer adhesive layer and electrically connected to the contact layer of the ridge portion; and a second insulating layer covering a portion not covered by the Pd electrode of the single-layer ad
    Type: Application
    Filed: October 26, 2010
    Publication date: August 11, 2011
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Takafumi Oka, Shinji Abe, Kazushige Kawasaki, Hitoshi Sakuma
  • Publication number: 20110188525
    Abstract: A laser device having a wave emission within a frequency range of 0.5 to 5 THz, includes a semiconductor heterostructure having a cylindrical form with a circular cross-section and including: a first optically nonlinear semiconductor material layer including an emitting medium configured to emit at least two optical whispering gallery modes belonging to the near-infrared spectrum, the two whispering gallery modes being confined within the first layer and enabling the generation, within the first layer, of radiation within an electromagnetic whispering gallery mode having a frequency of 0.
    Type: Application
    Filed: May 12, 2009
    Publication date: August 4, 2011
    Inventors: Julien Claudon, Jean-Michel Gérard, Vincent Berger, Giuseppe Leo, Alessio Andronico
  • Patent number: 7977134
    Abstract: A nitride-based semiconductor LED includes a substrate; an n-type nitride semiconductor layer formed on the substrate; an active layer and a p-type nitride semiconductor layer that are sequentially formed on a predetermined region of the n-type nitride semiconductor layer; a transparent electrode formed on the p-type nitride semiconductor layer; a p-electrode pad formed on the transparent electrode, the p-electrode pad being spaced from the outer edge line of the p-type nitride semiconductor layer by 50 to 200 ?m; and an n-electrode pad formed on the n-type nitride semiconductor layer.
    Type: Grant
    Filed: October 6, 2006
    Date of Patent: July 12, 2011
    Assignee: Samsung LED Co., Ltd.
    Inventors: Hyuk Min Lee, Hyun Kyung Kim, Dong Joon Kim, Hyoun Soo Shin
  • Publication number: 20110165712
    Abstract: Provided is a producing of a surface-emitting laser capable of aligning a center axis of a surface relief structure with that of a current confinement structure with high precision to reduce a surface damage during the producing. The producing of the laser having the relief provided on a laminated semiconductor layer and a mesa structure, the process comprising the steps of: forming, on the layer, one of a first dielectric film and a first resist film having a first pattern for defining the mesa and a second pattern for defining the relief and then forming the other one of the films; forming a second resist film to cover the second pattern and expose the first pattern; and forming the mesa by removing the layer under the first pattern using the second resist film.
    Type: Application
    Filed: January 3, 2011
    Publication date: July 7, 2011
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: Tatsuro Uchida
  • Publication number: 20110163421
    Abstract: Semiconductor micro- and nanotubes allow the incorporation of ordered structures such as quantum wells and quantum dots into them providing the potential for ultralow threshold micro- and nanoscale lasers for use in applications such as future ultrahigh-speed photonic systems as well as quantum information processing. According to the invention a means of manufacturing these with high reproducibility, low processing complexity, and at high densities is provided. Also provided is a means of releasing these micro- and nanotubes with low stress and a method of “pick-and-place” allowing micro- and nanotubes to be exploited in devices integrated on substrates that are either incompatible with the manufacturing technique or where the area of substrate required to manufacture them is detrimental to the cost or performance of the circuit.
    Type: Application
    Filed: January 4, 2011
    Publication date: July 7, 2011
    Applicant: The Royal Institution for the Advancement of Learning / McGill University
    Inventor: Zetian Mi
  • Patent number: 7964423
    Abstract: The invention relates to a semiconductor device and a method for manufacturing the semiconductor device, which includes: an insulating film over a substrate; a first pixel electrode embedded in the insulating film; an island-shaped single-crystal semiconductor layer over the insulating film; a gate insulating film and a gate electrode; an interlayer insulating film which covers the island-shaped single-crystal semiconductor layer and the gate electrode; a wiring which electrically connects a high-concentration impurity region and the first pixel electrode to each other; a partition which covers the interlayer insulating film, the island-shaped single-crystal semiconductor layer, and the gate electrode and has an opening in a region over the first pixel electrode; a light-emitting layer formed in a region which is over the pixel electrode and surrounded by the partition; and a second pixel electrode electrically connected to the light-emitting layer.
    Type: Grant
    Filed: June 9, 2008
    Date of Patent: June 21, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Kengo Akimoto
  • Patent number: 7964424
    Abstract: A method for manufacturing a nitride semiconductor light-emitting element comprises: forming a semiconductor laminated structure wherein an n-type nitride semiconductor epitaxial layer, an active layer, and a p-type nitride semiconductor epitaxial layer are laminated on a substrate; forming a p-type electrode having a first electrode layer containing Pd and a second electrode layer containing Ta on the p-type nitride semiconductor epitaxial layer; heat treating at a temperature between 400° C. and 600° C. in ambient containing oxygen after forming the p-type electrode; and forming a pad electrode containing Au on the p-type electrode after the heat treating.
    Type: Grant
    Filed: November 5, 2008
    Date of Patent: June 21, 2011
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kyozo Kanamoto, Katsuomi Shiozawa, Kazushige Kawasaki, Shinji Abe, Hitoshi Sakuma
  • Publication number: 20110140127
    Abstract: A semiconductor light-emitting device and a method for manufacturing the same is disclosed, which improves light extraction efficiency by forming a plurality of protrusions on a surface of a substrate for growing a nitride semiconductor material thereon, the semiconductor light-emitting device comprising a substrate; one or more first protrusions on the substrate, each first protrusion having a recess through which a surface of the substrate is exposed planarly; a first semiconductor layer on the substrate including the first protrusions; an active layer on the first semiconductor layer; a second semiconductor layer on the active layer; a first electrode on a predetermined portion of the first semiconductor layer, wherein the active layer and second semiconductor layer are not formed on the predetermined portion of the first semiconductor layer; and a second electrode on the second semiconductor layer.
    Type: Application
    Filed: July 15, 2010
    Publication date: June 16, 2011
    Inventors: Su Hyoung Son, Kyoung Jin Kim, Eun Mi Ko, Ung Lee
  • Publication number: 20110142089
    Abstract: A first semiconductor layer, an active layer, a second semiconductor layer, and a contact layer are sequentially stacked on a substrate. A ridge portion extending between both facets of a resonator is provided in the second semiconductor layer and the contact layer. A current confining layer is formed to be in contact with the ridge portion. The current confining layer has an opening on an upper surface of the ridge portion. A first electrode in contact with the contact layer is formed in the opening. A second electrode is provided on the first electrode. A non-current injection portion in contact with the contact layer is provided on the upper surface of the ridge portion near the resonator facet. The current confining layer and the non-current injection portion are formed of the same dielectric film. The second electrode is spaced apart from an upper surface region of the non-current injection portion.
    Type: Application
    Filed: November 1, 2010
    Publication date: June 16, 2011
    Inventor: Akiyoshi KUDO
  • Patent number: 7960198
    Abstract: A wide bandgap semiconductor device with surge current protection and a method of making the device are described. The device comprises a low doped n-type region formed by plasma etching through the first epitaxial layer grown on a heavily doped n-type substrate and a plurality of heavily doped p-type regions formed by plasma etching through the second epitaxial layer grown on the first epitaxial layer. Ohmic contacts are formed on p-type regions and on the backside of the n-type substrate. Schottky contacts are formed on the top surface of the n-type region. At normal operating conditions, the current in the device flows through the Schottky contacts. The device, however, is capable of withstanding extremely high current densities due to conductivity modulation caused by minority carrier injection from p-type regions.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: June 14, 2011
    Assignee: Semisouth Laboratories
    Inventors: Igor Sankin, Joseph Neil Merrett
  • Patent number: 7947520
    Abstract: In the method of making a semiconductor laser, a semiconductor region is grown on an active layer, and a part of the semiconductor region is etched to form a ridge structure. An insulating film is formed over the ridge structure, and a resin layer of photosensitive material is formed to bury the ridge structure. A cured resin portion and an uncured resin portion are formed in the resin layer by performing lithographic exposure of the resin layer, and the uncured resin portion is on the top of the ridge structure. The uncured resin portion is removed to form a dent which is provided on the top of the ridge structure. An overall surface of the cured resin portion and dent is etched to form an etched resin layer. An opening is formed in the etched resin layer by thinning the cured resin portion, and a part of the insulating film is exposed in the opening of the etched resin layer. The part of the insulating film is etched using the etched resin layer as a mask to form an opening in the insulating film.
    Type: Grant
    Filed: October 31, 2008
    Date of Patent: May 24, 2011
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hideki Yagi, Toshio Nomaguchi, Kenji Hiratsuka
  • Patent number: 7943406
    Abstract: A semiconductor light emitting diode includes a semiconductor substrate, an epitaxial layer of n-type Group III nitride on the substrate, a p-type epitaxial layer of Group III nitride on the n-type epitaxial layer and forming a p-n junction with the n-type layer, and a resistive gallium nitride region on the n-type epitaxial layer and adjacent the p-type epitaxial layer for electrically isolating portions of the p-n junction. A metal contact layer is formed on the p-type epitaxial layer. Some embodiments include a semiconductor substrate, an epitaxial layer of n-type Group III nitride on the substrate, a p-type epitaxial layer of Group III nitride on the n-type epitaxial layer and forming a p-n junction with the n-type layer, wherein portions of the epitaxial region are patterned into a mesa and wherein the sidewalls of the mesa comprise a resistive Group III nitride region for electrically isolating portions of the p-n junction.
    Type: Grant
    Filed: December 4, 2008
    Date of Patent: May 17, 2011
    Assignee: Cree, Inc.
    Inventors: David Beardsley Slater, Jr., John Adam Edmond, Alexander Suvorov, Iain Hamilton
  • Patent number: 7943407
    Abstract: A method for manufacturing a semiconductor laser includes the steps of forming a mask layer having a stripe-shaped mask portion corresponding to a ridge stripe to be formed on a nitride-based group III-V compound semiconductor layer, etching the nitride-based group III-V compound semiconductor layer to a predetermined depth using the mask layer to form the ridge stripe, forming a resist to cover the mask layer and the nitride-based group III-V compound semiconductor layer, etching-back the resist until the stripe-shaped mask portion of the mask layer is exposed, removing the exposed mask portion of the mask layer by etching to expose the upper surface of the ridge stripe, forming a metal film on the resist and the exposed ridge stripe to form an electrode on the ridge stripe, removing the resist together with the metal film formed thereon, and removing the mask layer by etching.
    Type: Grant
    Filed: November 16, 2009
    Date of Patent: May 17, 2011
    Assignee: Sony Corporation
    Inventors: Tsuyoshi Fujimoto, Nozomi Ohashi, Masaru Kuramoto, Eiji Nakayama
  • Patent number: 7939448
    Abstract: A manufacturing method of a semiconductor device includes a first electrode formation step of forming a control gate electrode above a surface of a semiconductor substrate with a control gate insulating film interposed between the control gate electrode and the semiconductor substrate, a step of forming a storage node insulating film on the surface of the semiconductor substrate, and a second electrode formation step of forming a memory gate electrode on a surface of the storage node insulating film. The second electrode formation step includes a step of forming a memory gate electrode layer on the surface of the storage node insulating film, a step of forming an auxiliary film, having an etching rate slower than that of the memory gate electrode layer, on a surface of the memory gate electrode layer, and a step of performing anisotropic etching on the memory gate electrode layer and the auxiliary film.
    Type: Grant
    Filed: September 23, 2010
    Date of Patent: May 10, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Tsutomu Okazaki, Motoi Ashida, Hiroji Ozaki, Tsuyoshi Koga, Daisuke Okada
  • Patent number: 7935553
    Abstract: A method of making a semiconductor device includes forming a first photoresist layer over an underlying layer, patterning the first photoresist layer into a first photoresist pattern, wherein the first photoresist pattern comprises a plurality of spaced apart first photoresist features located over the underlying layer, and etching the underlying layer using the first photoresist pattern as a mask to form a plurality of first spaced apart features. The method further includes removing the first photoresist pattern, forming a second photoresist layer over the plurality of first spaced apart features, and patterning the second photoresist layer into a second photoresist pattern, wherein the second photoresist pattern comprises a plurality of second photoresist features covering edge portions of the plurality of first spaced apart features.
    Type: Grant
    Filed: May 10, 2010
    Date of Patent: May 3, 2011
    Assignee: SanDisk 3D LLC
    Inventors: Roy E. Scheuerlein, Steven Radigan
  • Patent number: 7936019
    Abstract: A power source and methods thereof includes a structure comprising one or more p type layers, one or more n type layers, and one or more intrinsic layers and at least one source of radiation is disposed on at least a portion of the structure. Each of the p type layers is separated from each of the n type layers by one of the intrinsic layers.
    Type: Grant
    Filed: July 13, 2005
    Date of Patent: May 3, 2011
    Assignees: Rochester Institute of Technology, Glenn Research Center
    Inventors: Ryne P. Raffaelle, David Wilt
  • Publication number: 20110095262
    Abstract: A semiconductor light emission device is disclosed. The semiconductor light emission device includes: a substrate; a current concentration preventing pattern formed in a mesh net shape on the substrate; an n-type clad layer formed on the substrate loaded with the current concentration preventing pattern; an active layer and a p-type clad layer sequentially formed on the n-type clad layer; an n-type electrode formed on a part of the n-type clad layer which is exposed by partially etching the p-type clad layer and active layer; and a p-type electrode formed on the p-type clad layer. The current concentration preventing pattern is formed in a double layer structure which includes a first layer formed from one material of SiO and SiN and on the substrate, and a second layer formed from a metal material and on the first layer.
    Type: Application
    Filed: October 20, 2010
    Publication date: April 28, 2011
    Inventors: Min Ki Yoo, Koo Hwa Lee, Rok Hee Lee, Geun Woo Lee
  • Patent number: 7915622
    Abstract: A high fill factor textured light emitting diode structure comprises: a first textured cladding and contact layer (2) comprising a doped III-V or II-VI group compound semiconductor or alloys of such semiconductors deposited by epitaxial lateral overgrowth (ELOG) onto a patterned substrate (1); a textured undoped or doped active layer (3) comprising a III-V or II-VI group semiconductor or alloys of such semiconductors and where radiative recombination of electrons aid holes occurs or intersubband transition occurs; and a second textured cladding and contact layer (4) comprising a doped III-V or II-VI group semiconductor or alloys of such semiconductors.
    Type: Grant
    Filed: September 27, 2005
    Date of Patent: March 29, 2011
    Assignee: Nanogan Limited
    Inventor: Wang Nang Wang
  • Patent number: 7910407
    Abstract: A non-volatile memory device includes a first electrode, a diode steering element, at least three resistivity switching storage elements, and a second electrode. The diode steering element electrically contacts the first electrode and the at least three resistivity switching storage elements. The second electrode electrically contacts only one of the at least three resistivity switching storage elements.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: March 22, 2011
    Assignee: SanDisk 3D LLC
    Inventor: Roy E. Scheuerlein
  • Publication number: 20110064100
    Abstract: An optical device having a structured active region configured for one or more selected wavelengths of light emissions and formed on an off-cut m-plane gallium and nitrogen containing substrate.
    Type: Application
    Filed: September 15, 2010
    Publication date: March 17, 2011
    Applicant: Kaai, Inc.
    Inventors: James W. Raring, Nick Pfister, Mathew Schmidt, Christiane Poblenz
  • Publication number: 20110064102
    Abstract: An optical device having a structured active region configured for one or more selected wavelengths of light emissions and formed on an off-cut m-plane gallium and nitrogen containing substrate.
    Type: Application
    Filed: September 17, 2010
    Publication date: March 17, 2011
    Applicant: Kaai, Inc.
    Inventors: James W. Raring, Nick Pfister, Mathew Schmidt, Christiane Poblenz
  • Patent number: 7902071
    Abstract: A method for forming a trench-gated field effect transistor (FET) includes the following steps. Using a first mask, defining and simultaneously forming a plurality of active gate trenches and at least one gate runner trench extending to a first depth within a silicon region such that (i) the at least one gate runner trench has a width greater than a width of each of the plurality of active gate trenches, and (ii) the plurality of active gate trenches are contiguous with the at least one gate runner trench; and using the first mask and a second mask for protecting the at least one gate runner trench, further extending only the plurality of active gate trenches to a second and final depth within the silicon region.
    Type: Grant
    Filed: July 6, 2010
    Date of Patent: March 8, 2011
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Bruce Douglas Marchant
  • Patent number: 7897422
    Abstract: A new structure of a semiconductor optical device and a method to produce the device are disclosed. One embodiment of the optical device of the invention provides a blocking region including, from the side close to the mesa, a p-type first layer and a p-type second layer. The first layer is co-doped with an n-type impurity and a p-type impurity. The doping concentration of the p-type impurity in the first layer is smaller than that in the second layer, so, the first layer performs a function of a buffer layer for the Zn diffusion from the second layer to the active layer in the mesa structure.
    Type: Grant
    Filed: April 22, 2008
    Date of Patent: March 1, 2011
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Kenji Hiratsuka
  • Publication number: 20110042711
    Abstract: The present invention relates to III-nitride semiconductor light emitting device and a method for fabricating the same. The III-nitride semiconductor light emitting device includes: a substrate; a plurality of III-nitride semiconductor layers grown over the substrate and including an active layer for generating light by recombination of electrons and holes; and a protrusion formed on a surface of the substrate over which the semiconductor layers are to be grown, a section of the protrusion which is in parallel to the growth direction of the semiconductor layers being formed in a triangular shape.
    Type: Application
    Filed: December 31, 2009
    Publication date: February 24, 2011
    Applicant: WOOREE LST CO., LTD.
    Inventors: Yu-hang CHOI, Chae-seok LIM, Keuk KIM, Chi-kwon PARK
  • Patent number: 7892860
    Abstract: A method for forming a semiconductor laser chip is provided that can suppress layer discontinuity and simultaneously reduce fabrication variations in the light radiation angle in the horizontal direction. The method includes a step of forming, on an n-type GaAs substrate, a semiconductor element layer composed of a plurality of semiconductor layers including an etching marker layer, a step of forming, in a contact layer in the semiconductor element layer, a depressed portion having a depth not reaching the etching marker layer, and a step of forming a ridge portion by etching the semiconductor element layer by dry etching while monitoring, with laser light, the etching depth in the bottom region of the depressed portion.
    Type: Grant
    Filed: March 28, 2008
    Date of Patent: February 22, 2011
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Susumu Ohmi, Katsuhiko Kishimoto
  • Patent number: 7888149
    Abstract: Provided is a surface emitting laser or the like capable of suppressing horizontal misalignment between the surface relief structure and the current confining structure to make higher the precision of the alignment, to thereby obtain single transverse mode characteristics with stability. The surface emitting laser having a semiconductor layer laminated therein includes: a first etching region formed by etching a part of the upper mirror; and a second etching region formed by performing etching from a bottom portion of the first etching region to a semiconductor layer for forming a current confining structure, in which a depth of the second etching region is smaller than a depth of the first etching region.
    Type: Grant
    Filed: September 18, 2009
    Date of Patent: February 15, 2011
    Assignee: Canon Kabushiki Kaisha
    Inventor: Mitsuhiro Ikuta
  • Patent number: 7884466
    Abstract: According to the present invention, a recess portion is formed in a package substrate which is formed of a multilayer organic substrate having a multilayer wiring, and an LSI chip is accommodated within the recess portion. Wiring traces are formed on the upper surface of a resin which seals the LSI chip connected to the multilayer wiring. The wiring traces are connected to terminal wiring traces connected to the multilayer wiring on the front face of the package substrate and to front-face bump electrodes for external connection on the upper surface of the resin. On the back face side of the package substrate, back-face bump electrodes for external connection are formed and connected to the multilayer wiring.
    Type: Grant
    Filed: April 9, 2007
    Date of Patent: February 8, 2011
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Masamichi Ishihara, Fumihiko Ooka, Yoshihiko Ino
  • Patent number: 7883910
    Abstract: A light emitting diode (LED) structure, a LED packaging structure, and a method of forming LED structure are disclosed. The LED structure includes a sub-mount, a stacked structure, an electrode, an isolation layer and a conductive thin film layer. The sub-mount has a first surface and a second surface opposite the first surface. The stacked structure has a first semiconductor layer, an active layer and a second semiconductor layer that are laminated on the first surface. The electrode is disposed apart from the stacked structure on the first surface. The isolation layer is disposed on the first surface to surround the stacked structure as well as cover the lateral sides of the active layer. The conductive thin film layer connects the electrode to the stacked structure and covers the stacked structure.
    Type: Grant
    Filed: February 3, 2009
    Date of Patent: February 8, 2011
    Assignee: Industrial Technology Research Institute
    Inventors: Yao-Jun Tsai, Chen-Peng Hsu, Hung-Lieh Hu, Ji-Feng Chen
  • Publication number: 20110013660
    Abstract: An optoelectronic semiconductor body comprises a substrate (10), which has on a first main area (12) an epitaxial semiconductor layer sequence (20), suitable for generating electromagnetic radiation, in a first region (14) and a first trench (24) in a second region (22) adjacent to the first region (14), and at least one second trench (30) arranged outside the first region (14). The invention also relates to an optoelectronic semiconductor body and a method for producing an optoelectronic semiconductor body.
    Type: Application
    Filed: February 11, 2009
    Publication date: January 20, 2011
    Applicant: Osram Opto Semiconductors GmbH
    Inventors: Stefanie Brüninghoff, Christoph Eichler