Mesa Formation Patents (Class 438/39)
  • Patent number: 8519412
    Abstract: A semiconductor light-emitting device and a method for manufacturing the same is disclosed, which improves light extraction efficiency by forming a plurality of protrusions on a surface of a substrate for growing a nitride semiconductor material thereon, the semiconductor light-emitting device comprising a substrate; one or more first protrusions on the substrate, each first protrusion having a recess through which a surface of the substrate is exposed planarly; a first semiconductor layer on the substrate including the first protrusions; an active layer on the first semiconductor layer; a second semiconductor layer on the active layer; a first electrode on a predetermined portion of the first semiconductor layer, wherein the active layer and second semiconductor layer are not formed on the predetermined portion of the first semiconductor layer; and a second electrode on the second semiconductor layer.
    Type: Grant
    Filed: July 15, 2010
    Date of Patent: August 27, 2013
    Assignee: LG Display Co., Ltd.
    Inventors: Su Hyoung Son, Kyoung Jin Kim, Eun Mi Ko, Ung Lee
  • Patent number: 8513035
    Abstract: The present invention relates to illuminating field, especially relates to LED chip, LED and a method of manufacturing LED chip, the method of manufacturing LED chip comprises: forming a first semiconductor layer, a luminous layer and a second semiconductor layer sequentially on a substrate; forming a phosphor powder layer on the second semiconductor layer; removing a part of the phosphor powder layer and a part of the second semiconductor layer to form at least one groove which exposes a part of the second semiconductor layer; removing a part of the phosphor powder layer, a part of the second semiconductor layer, a part of the luminous layer and a part of the first semiconductor layer to form at least one unfilled corner which exposes a part of the first semiconductor layer; forming a first electrode in the unfilled corner, and forming a second electrode in the groove.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: August 20, 2013
    Assignee: Shenzhen Refond Optoelectronics Co., Ltd.
    Inventor: Zhaoxin Xiao
  • Patent number: 8501508
    Abstract: Embodiments described include straining transistor quantum well (QW) channel regions with metal source/drains, and conformal regrowth source/drains to impart a uni-axial strain in a MOS channel region. Removed portions of a channel layer may be filled with a junction material having a lattice spacing different than that of the channel material to causes a uni-axial strain in the channel, in addition to a bi-axial strain caused in the channel layer by a top barrier layer and a bottom buffer layer of the quantum well.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: August 6, 2013
    Assignee: Intel Corporation
    Inventors: Prashant Majhi, Mantu Hudait, Jack T. Kavalieros, Ravi Pillarisetty, Marko Radosavljevic, Gilbert Dewey, Titash Rakshit, Willman Tsai
  • Patent number: 8501510
    Abstract: An optoelectronic component with three-dimension quantum well structure and a method for producing the same are provided, wherein the optoelectronic component comprises a substrate, a first semiconductor layer, a transition layer, and a quantum well structure. The first semiconductor layer is disposed on the substrate. The transition layer is grown on the first semiconductor layer, contains a first nitride compound semiconductor material, and has at least a texture, wherein the texture has at least a first protrusion with at least an inclined facet, at least a first trench with at least an inclined facet and at least a shoulder facet connected between the inclined facets. The quantum well structure is grown on the texture and shaped by the protrusion, the trench and the shoulder facet.
    Type: Grant
    Filed: May 17, 2012
    Date of Patent: August 6, 2013
    Assignee: Hermes-Epitek Corp.
    Inventors: Benson Chao, Chung-Hua Fu, Shih-Chieh Jang
  • Patent number: 8497552
    Abstract: A semiconductor device may include a semiconductor buffer layer having a first conductivity type and a semiconductor mesa having the first conductivity type on a surface of the buffer layer. In addition, a current shifting region having a second conductivity type may be provided adjacent a corner between the semiconductor mesa and the semiconductor buffer layer, and the first and second conductivity types may be different conductivity types. Related methods are also discussed.
    Type: Grant
    Filed: July 30, 2009
    Date of Patent: July 30, 2013
    Assignee: Cree, Inc.
    Inventors: Qingchun Zhang, Anant K. Agarwal
  • Patent number: 8497141
    Abstract: A method of manufacturing a semiconductor device capable of largely increasing the yield and a semiconductor device manufactured by using the method is provided. After a semiconductor layer is formed on a substrate, as one group, a plurality of functional portions with at least one parameter value different from each other is formed in the semiconductor layer for every unit chip area. Then, a subject that is changed depending on the parameter value is measured and evaluated and after that, the substrate is divided for every chip area so that a functional portion corresponding with a given criterion as a result of the evaluation is not broken. Thereby, at least one functional portion corresponding with a given criterion can be formed by every chip area by appropriately adjusting each parameter value.
    Type: Grant
    Filed: August 8, 2011
    Date of Patent: July 30, 2013
    Assignee: Sony Corporation
    Inventors: Yuji Masui, Takahiro Arakida, Yoshinori Yamauchi, Kayoko Kikuchi, Rintaro Koda, Norihiko Yamaguchi
  • Patent number: 8492783
    Abstract: The present invention provides a light-emitting device which includes, in the order mentioned, a light-emitting layer containing a light-emitting portion, an intermediate layer, and a fine concavo-convex pattern, wherein the intermediate layer is disposed over a second surface of the light-emitting layer which surface is opposite to a first surface of the light-emitting layer, wherein the fine concavo-convex pattern has a cross-sectional shape which has portions projected and recessed with respect to the light-emitting layer, and reflects light emitted from the light-emitting layer, and wherein at least part of the intermediate layer has a refractive index of 0.9n to 1.1n, where n denotes a refractive index of the light-emitting portion with respect to light which has a main light-emitting wavelength.
    Type: Grant
    Filed: September 2, 2009
    Date of Patent: July 23, 2013
    Assignee: UDC Ireland Limited
    Inventor: Yoshihisa Usami
  • Patent number: 8486743
    Abstract: Some embodiments include methods of forming memory cells. Programmable material may be formed directly adjacent another material. A dopant implant may be utilized to improve adherence of the programmable material to the other material by inducing bonding of the programmable material to the other material, and/or by scattering the programmable material and the other material across an interface between them. The memory cells may include first electrode material, first ovonic material, second electrode material, second ovonic material and third electrode material. The various electrode materials and ovonic materials may join to one another at boundary bands having ovonic materials embedded in electrode materials and vice versa; and having damage-producing implant species embedded therein. Some embodiments include ovonic material joining dielectric material along a boundary band, with the boundary band having ovonic material embedded in dielectric material and vice versa.
    Type: Grant
    Filed: March 23, 2011
    Date of Patent: July 16, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Camillo Bresolin, Valter Soncini, Davide Erbetta
  • Patent number: 8481352
    Abstract: The present invention provides a method of fabricating a light emitting diode chip having an active layer between an N type semiconductor layer and a P type semiconductor layer. The method comprises the steps of preparing a substrate; laminating the semiconductor layers on the substrate, the semiconductor layers having the active layer between the N type semiconductor layer and the P type semiconductor layer; and forming grooves on the semiconductor layers laminated on the substrate until the substrate is exposed, whereby inclined sidewalls are formed by the grooves in the semiconductor layers divided into a plurality of chips. According to embodiments of the present invention, a sidewall of a semiconductor layer formed on a substrate of a light emitting diode chip is inclined with respect to the substrate, whereby its directional angle is widened as compared with a light emitting diode chip without such inclination.
    Type: Grant
    Filed: April 19, 2011
    Date of Patent: July 9, 2013
    Assignee: Seoul Opto Device Co., Ltd.
    Inventors: Jun Hee Lee, Jong Kyu Kim, Yeo Jin Yoon
  • Patent number: 8481342
    Abstract: A method for manufacturing a semiconductor device, includes: a step of etching a Si (111) substrate along a (111) plane of the Si (111) substrate to separate a Si (111) thin-film device having a separated surface along the (111) plane.
    Type: Grant
    Filed: March 24, 2010
    Date of Patent: July 9, 2013
    Assignee: Oki Data Corporation
    Inventors: Mitsuhiko Ogihara, Tomohiko Sagimori, Takahito Suzuki, Masataka Muto
  • Publication number: 20130163631
    Abstract: A method of fabricating a semiconductor laser device by forming a semiconductor structure at least part of which is in the form of a mesa structure having a flat top. The steps include depositing a passivation layer over the mesa structure, forming a contact opening in the passivation layer on the flat top of the mesa structure; and depositing a metal contact portion, with the deposited metal contact portion contacting the semiconductor structure via the contact opening. The contact opening formed through the passivation layer has a smaller area than the flat top of the mesa structure to allow for wider tolerances in alignment accuracy. The metal contact portion comprises a platinum layer between one or more gold layers to provide an effective barrier against Au diffusion into the semiconductor material.
    Type: Application
    Filed: December 21, 2011
    Publication date: June 27, 2013
    Applicant: Emcore Corporation
    Inventors: Jia-Sheng Huang, Phong Thai
  • Patent number: 8470625
    Abstract: A method of fabricating semiconductor light emitting device forms a laminated film by laminating an n-type nitride semiconductor layer, an active layer and a p-type nitride semiconductor layer in order on a uneven main surface of a first substrate, forms a plurality of first electrodes, on an upper surface of the p-type nitride semiconductor layer, forms a first metal layer to cover surfaces of the plurality of first electrodes and the p-type nitride semiconductor layer, forms a second metal layer on an upper surface of the second substrate, joins the first and second metal layers by facing the first and second substrates, cuts the first substrate or forming a groove on the first substrate along a border of the light emitting element from a surface side opposite to the first metal layer on the first substrate, and irradiates a laser toward areas of the light emitting devices from a surface side opposite to the first metal layer on the first substrate to peel off the first substrate.
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: June 25, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kotaro Zaima, Toru Gotoda, Toshiyuki Oka, Shinya Nunoue
  • Publication number: 20130156060
    Abstract: A laser diode device includes: a semiconductor substrate including a semi-polar surface, the semiconductor substrate being formed of a hexagonal III-nitride semiconductor; an epitaxial layer including a light emitting layer, the epitaxial layer being formed on the semi-polar surface of the semiconductor substrate, and the epitaxial layer including a ridge section; a first electrode formed on a top surface of the ridge section; an insulating layer covering the epitaxial layer in an adjacent region of the ridge section and a side surface of the ridge section, the insulating layer covering part or all of side surfaces of the first electrode continuously from the epitaxial layer; a pad electrode formed to cover a top surface of the first electrode and the insulating layer, the pad electrode being electrically connected to the first electrode; and a second electrode formed on a surface, of the semiconductor substrate, opposite to the semi-polar surface.
    Type: Application
    Filed: December 7, 2012
    Publication date: June 20, 2013
    Applicants: SUMITOMO ELECTRIC INDUSTRIES, LTD., SONY CORPORATION
    Inventors: SONY CORPORATION, Sumitomo Electric Industries, Ltd.
  • Patent number: 8461040
    Abstract: A method of forming a shielded gate field effect transistor includes: forming a plurality of active gate trenches in a silicon region; lining lower sidewalls and bottom of the active gate trenches with a shield dielectric; using a CMP process, filling a bottom portion of the active gate trenches with a shield electrode comprising polysilicon; forming an interpoly dielectric (IPD) over the shield electrode in the active gate trenches; lining upper sidewalls of the active gate trenches with a gate dielectric; and forming a gate electrode over the IPD in an upper portion of the active gate trenches.
    Type: Grant
    Filed: March 7, 2011
    Date of Patent: June 11, 2013
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Thomas E. Grebs, Rodney S. Ridley, Nathan Lawrence Kraft
  • Patent number: 8460977
    Abstract: A method of forming an electronic device, including forming a preliminary buffer layer on a drift layer, forming a first layer on the preliminary buffer layer, selectively etching the first layer to form a first mesa that exposes a portion of the preliminary buffer layer, and selectively etching the exposed portion of the preliminary buffer layer to form a second mesa that covers a first portion of the drift layer, that exposes a second portion of the drift layer, and that includes a mesa step that protrudes from the first mesa. Dopants are selectively implanted into the drift layer adjacent the second mesa to form a junction termination region in the drift layer. Dopants are selectively implanted through a horizontal surface of the mesa step into a portion of the drift layer beneath the mesa step to form a buried junction extension in the drift layer.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: June 11, 2013
    Assignee: Cree, Inc.
    Inventors: Qingchun Zhang, Anant K. Agarwal
  • Patent number: 8455906
    Abstract: The present invention provides a semiconductor light-emitting device. The light-emitting device comprises a first conductive clad layer, an active layer, and a second conductive clad layer sequentially formed on a substrate. In the light-emitting device, the substrate has one or more side patterns formed on an upper surface thereof while being joined to one or more edges of the upper surface. The side patterns consist of protrusions or depressions so as to scatter or diffract light to an upper portion or a lower portion of the light-emitting device.
    Type: Grant
    Filed: November 1, 2011
    Date of Patent: June 4, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sun Woon Kim, Hyun Kyung Kim, Je Won Kim, In Seok Choi, Kyu Han Lee, Jeong Tak Oh
  • Patent number: 8455912
    Abstract: A light-emitting device which includes a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type; and a light emitting layer provided between the first and second semiconductor layers, the device comprises a first electrode formed on the first semiconductor layer; a second electrode formed on the second semiconductor layer; and a light-transmissive electrode covering the second semiconductor layer and the second electrode, wherein contact between the second electrode and the second semiconductor layer is non-ohmic, and the second electrode has a stacked structure including a lower layer and an upper layer whose contact resistance with the light-transmissive electrode is lower than that of the lower layer, part of the second electrode being exposed through an opening formed in the light-transmissive electrode.
    Type: Grant
    Filed: September 9, 2010
    Date of Patent: June 4, 2013
    Assignee: Stanley Electric Co., Ltd.
    Inventors: Satoshi Tanaka, Yusuke Yokobayashi
  • Patent number: 8450128
    Abstract: A method for producing a semiconductor optical device includes the steps of forming a semiconductor region including a ridge structure on a substrate; forming an insulating film on the semiconductor region; forming a non-photosensitive resin region on the insulating film, forming a first mask that defines a scribe area; forming the scribe area by etching using the first mask; after removing the first mask, forming an insulating layer by etching the insulating film, forming an electrode on the ridge structure and the non-photosensitive resin region to produce a substrate product; forming a scribe line on a surface of the semiconductor region in the scribe area of the substrate product; and cutting the product along the scribe line to form a semiconductor laser bar.
    Type: Grant
    Filed: October 7, 2011
    Date of Patent: May 28, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hideki Yagi, Hiroyuki Yoshinaga
  • Publication number: 20130126825
    Abstract: A method for producing optical signals with improved efficiency, including the following steps: providing a layered semiconductor structure that includes a substrate, a semiconductor collector region of a first conductivity type, a semiconductor base region of a second conductivity type disposed on the collector region, and a semiconductor emitter region of the first semiconductor type disposed as a mesa over a portion of a surface of the base region; providing, in the base region, at least one region exhibiting quantum size effects; providing collector, base, and emitter electrodes, respectively coupled with the collector, base and emitter regions; providing a tunnel barrier layer over at least the exposed portion of the surface of the base region; and applying signals with respect to the collector, base, and emitter electrodes to produce optical signals from the base region.
    Type: Application
    Filed: November 13, 2012
    Publication date: May 23, 2013
    Applicant: Quantum Electro Opto Systems Sdn. Bhd.
    Inventor: Quantum Electro Opto Systems Sdn. Bhd.
  • Patent number: 8435815
    Abstract: A manufacturing method of a surface-emitting semiconductor laser includes the steps of: forming a stacked structure having a lower-multilayer film reflector including a lower oxidizable layer having at least one layer, an active layer having a light emitting region, an upper-multilayer film reflector including an upper oxidizable layer and an upper layer on a substrate in this order; providing a first groove in the upper layer; and providing a second groove including a portion overlapping the first groove in a planar shape and a portion not overlapping the first groove in the stacked structure.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: May 7, 2013
    Assignee: Sony Corporation
    Inventors: Masaki Shiozaki, Osamu Maeda, Takahiro Arakida, Susumu Sato
  • Patent number: 8435809
    Abstract: A vertical total internal reflection (TIR) mirror and fabrication thereof is made by creating a re-entrant profile using crystallographic silicon etching. Starting with an SOI wafer, a deep silicon etch is used to expose the buried oxide layer, which is then wet-etched (in HF), opening the bottom surface of the Si device layer. This bottom silicon surface is then exposed so that in a crystallographic etch, the resulting shape is a re-entrant trapezoid with facets These facets can be used in conjunction with planar silicon waveguides to reflect the light upwards based on the TIR principle. Alternately, light can be coupled into the silicon waveguides from above the wafer for such purposes as wafer level testing.
    Type: Grant
    Filed: September 25, 2009
    Date of Patent: May 7, 2013
    Assignee: Intel Corporation
    Inventors: John Heck, Ansheng Liu, Michael T. Morse, Haisheng Rong
  • Patent number: 8420420
    Abstract: A method of manufacturing a thin film transistor array substrate and a structure of the same are disclosed. The manufacturing method merely requires two steps of mask fabrication to accomplish the manufacture of thin film transistor array, in which the manufacturing method utilizes a first mask fabrication step to define a pattern of a source electrode and a drain electrode of the thin film transistor, and a partially-exposed dielectric layer, and utilizes a second mask fabrication step to define an arrangement of a transparent conductive layer. The manufacturing method and structure can dramatically reduce the manufacturing cost of masks and simplify the whole manufacturing process.
    Type: Grant
    Filed: May 21, 2011
    Date of Patent: April 16, 2013
    Assignee: Chunghwa Picture Tubes, Ltd.
    Inventors: Wei-pang Yen, Hsien-kun Chiu, Chan-chang Liao, Chao-huan Hsu
  • Patent number: 8420424
    Abstract: According to one embodiment, in a method for manufacturing a semiconductor light emitting device, a transparent conductive film is formed on a semiconductor laminated body of a multilayer structure containing a light emitting unit. The transparent conductive film is a film transmissive to a light of a luminescence wavelength from the light emitting unit. A mask is formed on the portion of the transparent conductive film. The transparent conductive film is removed by wet etching through the mask so as to expose the semiconductor laminated body. The semiconductor laminated body is removed by anisotropically etching through the mask so as to remove the light emitting unit. The mask is removed. A first electrode is formed on the portion of the semiconductor laminated body exposed after removing the light emitting unit. A second electrode is formed on the portion of the transparent conductive film.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: April 16, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kyohei Shibata
  • Patent number: 8420422
    Abstract: According to the embodiments, a distribution of a recess portion shape is calculated based on a result obtained by measuring the recess portion shape of a first projection and recess pattern formed on a surface of a template. Next, a distribution of an application amount of a curing agent to a processing target layer is calculated based on the distribution of the recess portion shape, and the curing agent is applied to the processing target layer based on this distribution of the application amount of the curing agent. Next, a second projection and recess pattern is formed by transferring the first projection and recess pattern onto the curing agent by causing the curing agent to cure in a state where the first projection and recess pattern is in contact with the curing agent.
    Type: Grant
    Filed: March 7, 2011
    Date of Patent: April 16, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masafumi Asano, Ryoichi Inanami, Masayuki Hatano
  • Patent number: 8420423
    Abstract: An organic light-emitting display apparatus includes a planarization layer, a plurality of group electrode layers having different numbers of layers on the planarization layer and including a first group electrode layer having a metal layer, a reflective layer, a first transparent conductive layer, a second transparent conductive layer, and a third transparent conductive layer sequentially stacked, a second group electrode layer having the metal layer, the reflective layer, the first transparent conductive layer, and the third transparent conductive layer sequentially stacked, and a third group electrode layer having the metal layer, the reflective layer, and the first transparent conductive layer sequentially stacked, an intermediate layer on the first group electrode layer, the second group electrode layer, and the third group electrode layer, and including at least one organic light-emitting layer, and a second electrode layer on the intermediate layer.
    Type: Grant
    Filed: March 14, 2011
    Date of Patent: April 16, 2013
    Assignee: Samsung Display Co., Ltd
    Inventors: Jong-Hyun Choi, Dae-Hyun No
  • Patent number: 8415181
    Abstract: Provided is a light emitting element, a light emitting device including the same, and fabrication methods of the light emitting element and light emitting device. The light emitting device comprises a substrate, a light emitting structure including a first conductive layer of a first conductivity type, a light emitting layer, and a second conductive layer of a second conductivity type which are sequentially stacked, a first electrode which is electrically connected with the first conductive layer; and a second electrode which is electrically connected with the second conductive layer and separated apart from the first electrode, wherein at least a part of the second electrode is connected from a top of the light emitting structure, through a sidewall of the light emitting structure, and to a sidewall of the substrate.
    Type: Grant
    Filed: January 4, 2012
    Date of Patent: April 9, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yu-Sik Kim, Seong-Deok Hwang, Seung-Jae Lee, Sun-Pil Youn
  • Patent number: 8415767
    Abstract: A compliant bipolar micro device transfer head array and method of forming a compliant bipolar micro device transfer array from an SOI substrate are described. In an embodiment, a compliant bipolar micro device transfer head array includes a base substrate and a patterned silicon layer over the base substrate. The patterned silicon layer may include first and second silicon interconnects, and first and second arrays of silicon electrodes electrically connected with the first and second silicon interconnects and deflectable into one or more cavities between the base substrate and the silicon electrodes.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: April 9, 2013
    Assignee: LuxVue Technology Corporation
    Inventors: Dariusz Golda, Andreas Bibl
  • Patent number: 8415768
    Abstract: A compliant monopolar micro device transfer head array and method of forming a compliant monopolar micro device transfer array from an SOI substrate are described. In an embodiment, the micro device transfer head array including a base substrate and a patterned silicon layer over the base substrate. The patterned silicon layer may include a silicon interconnect and an array of silicon electrodes electrically connected with the silicon interconnect. Each silicon electrode includes a mesa structure protruding above the silicon interconnect, and each silicon electrode is deflectable into a cavity between the base substrate and the silicon electrode. A dielectric layer covers a top surface of each mesa structure.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: April 9, 2013
    Assignee: LuxVue Technology Corporation
    Inventors: Dariusz Golda, Andreas Bibl
  • Patent number: 8409893
    Abstract: A convex part formation method of forming a convex part in parallel with a <110> direction of a backing on the backing having a {100} face as the top surface thereof, includes: (a) forming a mask layer in parallel with the <110> direction on the backing; (b) etch the backing so as to form a convex-part upper layer whose sectional shape on a cutting plane corresponding to a {110} face is an isosceles trapezoid, the base of which is longer than the upper side thereof, and the side surface of which has an inclination of ?U; and (c) further etching the backing so as to form a convex-part lower layer whose sectional shape on the cutting plane corresponding to the {110} face is an isosceles trapezoid, the base of which is longer than the upper side thereof, and the side surface of which has an inclination of ?D (where ?D??U).
    Type: Grant
    Filed: January 23, 2012
    Date of Patent: April 2, 2013
    Assignee: Sony Corporation
    Inventors: Kiyotaka Yashima, Yoshinari Kiwaki, Kamada Michiru, Sachio Karino, Hironobu Narui, Nobukata Okano
  • Patent number: 8405065
    Abstract: An LED semiconductor body includes a semiconductor layer sequence which comprises a quantum structure which is intended to produce radiation and comprises at least one quantum layer and at least one barrier layer, wherein the quantum layer and the barrier layer are strained with mutually opposite mathematical signs.
    Type: Grant
    Filed: July 27, 2007
    Date of Patent: March 26, 2013
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Günther Grönninger, Christian Jung, Peter Heidborn, Alexander Behres
  • Publication number: 20130070798
    Abstract: A semiconductor laser includes a semiconductor laser portion including an active layer portion having a p-type cladding layer, an active layer, and an n-type cladding layer on a p-type InP semiconductor substrate; and current confining structures that fill spaces on both sides of the semiconductor laser portion. Each of the current confining structures includes a first p-type InP layer, a Ru-doped InP layer, and a second p-type InP layer. The Ru-doped InP layer is in contact only with the first and second p-type InP layers. To obtain the structure, timing of introduction of a halogen-containing gas is adjusted.
    Type: Application
    Filed: August 16, 2012
    Publication date: March 21, 2013
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Go Sakaino, Harunaka Yamaguchi, Takashi Nagira
  • Patent number: 8383438
    Abstract: One embodiment of the present invention provides a method for fabricating light-emitting diodes. The method includes etching grooves on a growth substrate, thereby creating mesas on the growth substrate. The method further includes fabricating on each of the mesas an indium gallium aluminum nitride (InGaAlN) multilayer structure which contains a p-type layer, a multi-quantum-well layer, and an n-type layer. In addition, the method includes depositing one or more metal substrate layers on top of the InGaAlN multilayer structure. Moreover, the method includes removing the growth substrate. Furthermore, the method includes creating electrodes on both sides of the InGaAlN multilayer structure, thereby resulting in a vertical-electrode configuration.
    Type: Grant
    Filed: August 19, 2008
    Date of Patent: February 26, 2013
    Assignee: Lattice Power (JIANGXI) Corporation
    Inventors: Chuanbing Xiong, Fengyi Jiang, Li Wang, Wenqing Fang, Guping Wang, Shaohua Zhang
  • Patent number: 8372670
    Abstract: A method for making a light-emitting element assembly including a support substrate having a first surface, a second surface facing the first surface, a recessed portion, and a conductive material layer formed over the first surface and the inner surface of the recessed portion, and a light-emitting element. The light-emitting element has a laminated structure including a first compound semiconductor layer, a light-emitting portion, and a second compound semiconductor layer, at least the second compound semiconductor layer and the light-emitting portion constituting a mesa structure. The light-emitting element further includes an insulating layer formed, a second electrode, and a first electrode. The mesa structure is placed in the recessed portion so that the conductive material layer and the second electrode are in at least partial contact with each other, and light emitted from the light-emitting portion is emitted from the second surface side of the first compound semiconductor layer.
    Type: Grant
    Filed: July 22, 2010
    Date of Patent: February 12, 2013
    Assignee: Sony Corporation
    Inventors: Rintaro Koda, Takahiro Arakida, Satoshi Taniguchi, Yuji Masui, Nobuhiro Suzuki, Tomoyuki Oki, Chiyomi Uchiyama, Kayoko Kikuchi
  • Publication number: 20130032776
    Abstract: A light emitting diode structure and a manufacturing method thereof are disclosed. The structure includes a substrate, an N type semiconductor layer, and active layer, a P type semiconductor layer, a current diffusion layer, and a metal electrode. The metal ions of the P type semiconductor layer may bond with hydrogen after process thermal annealing, and metal hydride may be generated. The metal hydride may be directly formed on the surface of the P type semiconductor layer and may be used as the current blocking layer. Since the metal hydride may be directly formed on the surface of the P type semiconductor layer, its structure is flat, which resolve the problem having the electrodes peeled off from the solder wire.
    Type: Application
    Filed: September 23, 2011
    Publication date: February 7, 2013
    Applicant: LEXTAR ELECTRONICS CORP.
    Inventor: CHENG-HUNG CHEN
  • Patent number: 8367450
    Abstract: A light emitting system is disclosed. The system comprises an active region having a stack of bilayer quantum well structures separated from each other by barrier layers. Each bilayer quantum well structure is formed of a first layer made of a first semiconductor alloy for electron confinement and a second layer made of a second semiconductor alloy for hole confinement, wherein a thickness and composition of each layer is such that a characteristic hole confinement energy of the bilayer quantum well structure is at least 200 meV.
    Type: Grant
    Filed: February 21, 2011
    Date of Patent: February 5, 2013
    Assignee: Technion Research & Development Foundation Ltd.
    Inventors: Gad Bahir, Dan Fekete, Asaf Albo
  • Patent number: 8368055
    Abstract: Provided are a display device, which has a longer life and can be fabricated simply relative to conventional display devices, and a method of fabricating the display device. The display device includes a substrate which includes first through third subpixel regions, first through third organic light-emitting transistors which are disposed in the first through third subpixel regions, respectively, and are operable to emit light of a first color, and a first fluorescent pattern which is formed on the first organic light-emitting transistor and is operable to cause light of a second color to be emitted.
    Type: Grant
    Filed: August 18, 2009
    Date of Patent: February 5, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jung-Han Shin, Jae-Byung Park, Don-Chan Cho, Jin-Seob Byun, Hyoung-Joo Kim
  • Patent number: 8367445
    Abstract: A method for producing a Group III nitride semiconductor light-emitting device includes forming a first stripe-pattern embossment on the top surface of a sapphire substrate, so that first grooves parallel to the x-axis direction (the c-axis direction of the sapphire substrate) are periodically arranged at specific intervals. Subsequently, an insulating film is formed over the entire surface of the first stripe-pattern embossment. Next, a second stripe-pattern embossment is formed so that second grooves, each having a flat bottom surface, are periodically arranged at specific intervals and parallel to the y-axis direction, which is orthogonal to the x-axis direction. A GaN crystal is grown through MOCVD on side surfaces of each second groove of the sapphire substrate, to thereby form, on the sapphire substrate, an m-plane GaN base layer. An LED device structure is formed on the base layer, to thereby produce a light-emitting device.
    Type: Grant
    Filed: November 23, 2011
    Date of Patent: February 5, 2013
    Assignee: Toyoda Gosei Co., Ltd.
    Inventor: Koji Okuno
  • Patent number: 8354286
    Abstract: A method of manufacturing a silicon optoelectronic device, a silicon optoelectronic device manufactured by the method, and an image input and/or output apparatus including the silicon optoelectronic device are provided. The method includes preparing an n- or p-type silicon-based substrate, forming a microdefect pattern along a surface of the substrate by etching, forming a control film with an opening on the microdefect pattern, and forming a doping region on the surface of the substrate having the microdefect pattern in such a way that a predetermined dopant of the opposite type to the substrate is injected onto the substrate through the opening of the control film to be doped to a depth so that a photoelectric conversion effect leading to light emission and/or reception by quantum confinement effect in the p-n junction occurs.
    Type: Grant
    Filed: January 16, 2004
    Date of Patent: January 15, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun-kyung Lee, Byoung-lyong Choi, Pil-soo Ahn, Jun-young Kim, Young-gu Jin
  • Patent number: 8343788
    Abstract: A method of fabricating a light emitting device comprising: providing a substrate; forming an epitaxial stack on the substrate wherein the epitaxial stack comprising a first conductivity semiconductor layer, an active layer and a second conductivity semiconductor layer; forming a mesa on the epitaxial stack to expose partial of the first conductivity semiconductor layer; and etching the surface of the first conductivity semiconductor layer and forming a least one rough structure on the surface of the first conductivity semiconductor layer wherein the first conductivity semiconductor layer is sandwiched by the substrate and the active layer.
    Type: Grant
    Filed: April 19, 2011
    Date of Patent: January 1, 2013
    Assignee: Epistar Corporation
    Inventors: De-Shan Kuo, Ting-Chia Ko, Chun-Hsiang Tu
  • Patent number: 8334151
    Abstract: An (Al, Ga, In)N and ZnO direct wafer bonded light emitting diode (LED), wherein light passes through electrically conductive ZnO. Flat and clean surfaces are prepared for both the (Al, Ga, In)N and ZnO wafers. A wafer bonding process is then performed between the (Al, Ga, In)N and ZnO wafers, wherein the (Al, Ga, In)N and ZnO wafers are joined together and then wafer bonded in a nitrogen ambient under uniaxial pressure at a set temperature for a set duration. After the wafer bonding process, ZnO is shaped for increasing light extraction from inside of LED.
    Type: Grant
    Filed: April 1, 2010
    Date of Patent: December 18, 2012
    Assignee: The Regents of the University of California
    Inventors: Akihiko Murai, Christina Ye Chen, Daniel B. Thompson, Lee S. McCarthy, Steven P. DenBaars, Shuji Nakamura, Umesh K. Mishra
  • Patent number: 8334542
    Abstract: A light emitting diode includes a thermal conductive substrate, an p-type GaN layer, an active layer and an n-type GaN layer sequentially stacked above the substrate and an electrode pad deposited on the n-type GaN layer. A surface of n-type GaN layer away from the active layer has a first diffusing section and a second diffusing section. The first diffusing section is adjacent to the electrode pad and the second diffusing section is located at the other side of the first diffusing section opposite to the electrode pad, wherein the doping concentration of the first diffusing section is less than that of the second diffusing section. The n-type GaN layer has an electrical resistance larger than that of the first diffusing section which in turn is larger than that of the second diffusing section.
    Type: Grant
    Filed: September 17, 2010
    Date of Patent: December 18, 2012
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventor: Chih-Chen Lai
  • Patent number: 8334154
    Abstract: A method for producing quantum dots embedded in a matrix on a substrate includes the steps of: depositing a precursor on the substrate, the precursor including at least one first metal or a metal compound; contacting the deposited precursor and uncovered areas of the substrate with a gas-phase reagent including at least one second metal and/or a chalcogen; and initiating a chemical reaction between the precursor and the reagent by raising a temperature thereof simultaneously with or subsequent to the contacting so that the matrix consists exclusively of elements of the reagent.
    Type: Grant
    Filed: December 11, 2007
    Date of Patent: December 18, 2012
    Assignee: Helmholtz-Zentrum Berlin Fuer Materialien und Energie GmbH
    Inventors: David Fuertes Marón, Sebastian Lehmann, Sascha Sadewasser, Martha Christina Lux-Steiner
  • Patent number: 8329481
    Abstract: A manufacturing method of nitride semiconductor light emitting elements, which can reliably form a mechanically stable wiring electrode leading from a light emitting element surface. A structure protective sacrifice layer is formed around a first electrode layer on a device structure layer beforehand, and after separation of the device structure layer into respective portions for the light emitting elements, the resultant is stuck to a support substrate. Subsequently, forward tapered grooves reaching the structure protective sacrifice layer are formed, and the inverse tapered portion formed outward of the forward tapered groove is lifted off in a lift-off step. Thus, an insulating layer is formed on the forward tapered side walls of the light emitting element, and a wiring electrode layer electrically connected to the second electrode layer on the principal surface of the light emitting element is formed on the insulating layer.
    Type: Grant
    Filed: February 9, 2012
    Date of Patent: December 11, 2012
    Assignee: Stanley Electric Co., Ltd.
    Inventor: Mamoru Miyachi
  • Publication number: 20120309123
    Abstract: A method for manufacturing a quantum cascade laser includes the steps of forming a semiconductor stacked structure including a first semiconductor region and a second semiconductor region; forming an etching mask having a striped pattern on the second semiconductor region; forming a semiconductor mesa structure having a mesa shape in cross section by etching the first and second semiconductor regions using the etching mask; forming an insulating layer over a top portion and side surfaces of the semiconductor mesa structure and the first semiconductor region; forming an opening in a portion of the insulating layer that is disposed on the top portion of the semiconductor mesa structure; and forming an electrode over the inside of the opening of the insulating layer, the top portion and side surfaces of the semiconductor mesa structure, and the first semiconductor region.
    Type: Application
    Filed: May 17, 2012
    Publication date: December 6, 2012
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Yukihiro TSUJI
  • Patent number: 8319231
    Abstract: A display device includes a first organic electroluminescent element and a second organic electroluminescent element. The first and second organic electroluminescent elements have different luminescent colors. The first and second organic electroluminescent elements each include, in series, a first electrode, a first charge transport layer, a second charge transport layer, a light-emitting layer, and a second electrode. The first charge transport layer is common to the first and second organic electroluminescent elements. The second charge transport layer of the first organic electroluminescent element is different in thickness from the second charge transport layer of the second organic electroluminescent element. The concentration of a dopant material contained in the first charge transport layer is less than that of the second charge transport layer.
    Type: Grant
    Filed: May 31, 2011
    Date of Patent: November 27, 2012
    Assignee: Canon Kabushiki Kaisha
    Inventor: Norifumi Kajimoto
  • Patent number: 8313966
    Abstract: Semiconductor micro- and nanotubes allow the incorporation of ordered structures such as quantum wells and quantum dots into them providing the potential for ultralow threshold micro- and nanoscale lasers for use in applications such as future ultrahigh-speed photonic systems as well as quantum information processing. According to the invention a means of manufacturing these with high reproducibility, low processing complexity, and at high densities is provided. Also provided is a means of releasing these micro- and nanotubes with low stress and a method of “pick-and-place” allowing micro- and nanotubes to be exploited in devices integrated on substrates that are either incompatible with the manufacturing technique or where the area of substrate required to manufacture them is detrimental to the cost or performance of the circuit.
    Type: Grant
    Filed: January 4, 2011
    Date of Patent: November 20, 2012
    Assignee: The Royal Institution for the Advancement of Learning/McGill University
    Inventor: Zetian Mi
  • Patent number: 8309972
    Abstract: Aspects include electrodes that provide specified reflectivity attributes for light generated from an active region of a Light Emitting Diode (LED). LEDs that incorporate such electrode aspects. Other aspects include methods for forming such electrodes, LEDs including such electrodes, and structures including such LEDs.
    Type: Grant
    Filed: January 25, 2012
    Date of Patent: November 13, 2012
    Assignee: Bridgelux, Inc.
    Inventors: Frank T. Shum, William W. So, Steven D. Lester
  • Patent number: 8298844
    Abstract: A method of manufacturing an organic thin film pattern, the method including: forming a dummy organic thin film on a substrate; radiating light on the dummy organic thin film pattern the dummy organic thin film; forming a main organic thin film, having a sublimation temperature is higher than that of the dummy organic thin film, on the substrate and the patterned dummy organic thin film; and heating patterned the dummy organic thin film and the main organic thin film, to sublimate the dummy organic thin film and thereby pattern the main organic thin film.
    Type: Grant
    Filed: December 9, 2010
    Date of Patent: October 30, 2012
    Assignee: Samsung Display Co., Ltd.
    Inventors: Kang-Il Lee, Yong-Sup Choi, Chool-Lae Roh
  • Patent number: 8288186
    Abstract: A substrate including a host and a seed layer bonded to the host is provided, then a semiconductor structure including a light emitting layer disposed between an n-type region and a p-type region is grown on the seed layer. In some embodiments, a bonding layer bonds the host to the seed layer. The seed layer may be thinner than a critical thickness for relaxation of strain in the semiconductor structure, such that strain in the semiconductor structure is relieved by dislocations formed in the seed layer, or by gliding between the seed layer and the bonding layer an interface between the two layers. In some embodiments, the host may be separated from the semiconductor structure and seed layer by etching away the bonding layer.
    Type: Grant
    Filed: September 22, 2010
    Date of Patent: October 16, 2012
    Assignee: Philips Lumileds Lighting Company LLC
    Inventors: Michael R. Krames, Nathan F. Gardner, John E. Epler
  • Publication number: 20120248403
    Abstract: The invention inter alia relates to a method of fabricating a layer assembly comprising the steps of: arranging a first layer on top of a carrier; arranging a second layer on top of the first layer; locally modifying the material of the buried first layer and providing at least one modified section in the first layer, wherein the modified material changes or induces mechanical strain in a portion of the second layer which is arranged above the at least one modified section; after locally modifying the material of the buried first layer, depositing a third material on top of the second layer, at least one characteristic of the third material being sensitive to the local mechanical strain in the second layer.
    Type: Application
    Filed: March 30, 2011
    Publication date: October 4, 2012
    Inventors: André STRITTMATTER, Andrei Schliwa, Tim David Germann, Udo W. Pohl, Vladimir Gaysler, Jan-Hindrik Schulze