Mesa Formation Patents (Class 438/39)
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Patent number: 7319076Abstract: A method and apparatus to provide a low resistance interconnect. A void is defined in the sacrificial layer that is proximate to an active layer. An overgrowth layer is formed in the void and over portions of the sacrificial layer adjacent to the void. A ridge section is defined in the overgrowth layer and portions of the sacrificial layer are removed to define a shank section in the overgrowth layer under the ridge section. The ridge section having a greater lateral dimension than the shank section to reduce electrical resistance between the active layer and electrical interconnects to be electrically coupled to the ridge section.Type: GrantFiled: September 26, 2003Date of Patent: January 15, 2008Assignee: Intel CorporationInventor: Peter J. Hanberg
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Publication number: 20080003707Abstract: The present invention provides a method to fabricate a diode whose heat stability is improved. The diode has a layer of high reflective ohmic contact and an alloy metal is used in the layer. With the alloy metal used in the layer, the heat stability of the diode is improved.Type: ApplicationFiled: August 9, 2006Publication date: January 3, 2008Applicant: National Central UniversityInventors: Cheng-Yi Liu, Chia-Hsien Chou, Ching-Liang Lin
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Patent number: 7314771Abstract: A method of manufacturing a display apparatus includes: forming a peripheral circuit, a first electrode and a bank on a substrate; forming a surface energy lowering pattern on the bank; forming an organic light emitting member on the first electrode; and forming a second electrode on the organic light emitting member. The first electrode receives a first driving signal. The first electrode has a first surface energy. The bank surrounds at least one side of the first electrode. The surface energy lowering pattern has a second surface energy which is lower than the first surface energy. The second electrode receives a second driving signal to display an image. Therefore, an image display quality of the display apparatus is improved.Type: GrantFiled: November 18, 2004Date of Patent: January 1, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-Won Lee, Joon-Hoo Choi, Jin-Koo Chung
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Patent number: 7303933Abstract: A process of manufacturing a semiconductor device includes the steps of forming a stacked structure of a first III-V compound semiconductor layer containing In and having a composition different from InP and a second III-V compound semiconductor layer containing In. The second III-V compound semiconductor layer is formed over the first III-V compound semiconductor layer and growing an InP layer at regions adjacent the stacked structure to form a stepped structure of InP. The process further includes the step of wet-etching the stepped structure and the second III-V compound semiconductor layer using an etchant containing hydrochloric acid and acetic acid to remove at least the second III-V compound semiconductor layer.Type: GrantFiled: June 20, 2005Date of Patent: December 4, 2007Assignee: Fujitsu Quantum Devices LimitedInventors: Takayuki Watanabe, Tsutomu Michitsuta, Taro Hasegawa, Takuya Fujii
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Optically pumped, surface-emitting semiconductor laser device and method for the manufacture thereof
Patent number: 7300808Abstract: The invention is directed to an optically pumped surface-emitting semiconductor laser device having at least one radiation-generating quantum well structure and at least one pump radiation source for optically pumping the quantum well structure, whereby the pump radiation source comprises an edge-emitting semiconductor structure. The radiation-generating quantum well structure and the edge-emitting semiconductor structure are epitaxially grown on a common substrate. A very efficient and uniform optical pumping of the radiation-generating quantum well structure is advantageously possible with this monolithically produced semiconductor laser device. Methods for manufacturing inventive semiconductor laser devices are also specified.Type: GrantFiled: July 29, 2004Date of Patent: November 27, 2007Assignee: Osram GmbHInventors: Tony Albrecht, Norbert Linder, Johann Luft -
Patent number: 7298136Abstract: An electrical test lead includes an insulated electrical cable having a proximal end and a distal end, an electrical connector disposed at the proximal end of the cable and connected to a test instrument, and an electrically conductive magnetic probe disposed at the distal end. The probe is adapted to magnetically attach to a test point in an electrical system and to provide an electrical connection from the test point through the probe, the cable and the connector to the test instrument. Together, the test lead and the test instrument may be used as an electrical test kit. The test lead may further include an additional electrical test lead component magnetically attached, and electrically connected, to the electrically conductive magnetic probe and extending therefrom. An additional electrically conductive magnetic probe or a non-magnetic electrical connector may be disposed at the distal end of the additional electrical test lead component.Type: GrantFiled: July 6, 2006Date of Patent: November 20, 2007Inventor: Kevin Mark Curtis
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Patent number: 7294519Abstract: Provided are a semiconductor light-emitting device having nano-needles and a method of manufacturing the same. The provided semiconductor light-emitting device improves the extraction efficiency of photons, and includes a gallium nitride (GaN) group multi-layer and nano-needles grown on the GaN group multi-layer. The nano-needles improve the extraction efficiency of photons.Type: GrantFiled: June 17, 2005Date of Patent: November 13, 2007Assignee: Luxpia Co., Ltd.Inventors: Jong Soo Lee, Min Sang Lee, Young Ki Lee
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Patent number: 7291529Abstract: Processing a semiconductor wafer can include forming a plurality of Light Emitting Devices (LED) on a semiconductor wafer having a first thickness. The plurality of LEDs on the wafer are brought into contact with a surface of a carrier to couple the wafer to the carrier. The first thickness of the wafer is reduced to a second thickness that is less than the first thickness by processing the backside of the wafer. The carrier is separated from the plurality of LEDs on the wafer and the wafer is cut to separate the plurality of LEDs from one another. Related devices are also disclosed.Type: GrantFiled: November 12, 2004Date of Patent: November 6, 2007Assignee: Cree, Inc.Inventors: David B. Slater, Jr., Matthew Donofrio
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Patent number: 7288446Abstract: Several methods and structures are disclosed for determining electrical properties of silicon-on-insulator (SOI) wafers and alternate versions of such wafers such as strained silicon:silicon/germanium:-on-insulator (SSGOI) wafers. The analyzed electrical properties include mobilities, interface state densities, and oxide charge by depositing electrodes on the wafer surface and measuring the current-voltage behavior using these electrodes, In a single gate structure, the source and drain electrodes reside on the wafer surface and the buried insulator acts as the gate oxide, with the substrate acting as the gate electrode. In a double gate structure, an oxide is used on the upper surface between the source and drain electrodes and an additional metal layer is used on top of this oxide to act as a second gate electrode.Type: GrantFiled: September 6, 2005Date of Patent: October 30, 2007Assignee: International Business Machines CorporationInventors: Harold J. Hovel, Thermon E. McKoy
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Patent number: 7288422Abstract: A photonic integrated device using a reverse-mesa structure and a method for fabricating the same are disclosed. The photonic integrated device includes a first conductive substrate on which a semiconductor laser, an optical modulator, a semiconductor optical amplifier, and a photo detector are integrated, a first conductive clad layer and an active layer sequentially formed on the first conductive substrate in the form of a mesa structure, a second conductive clad layer formed on the active layer in the form of a reverse-mesa structure, an ohmic contact layer formed on the second clad layer in such a manner that the ohmic contact layer has a width narrower than the width of an upper surface of the second conductive clad layer, a current shielding layer filled in a sidewall having a mesa and reverse-mesa structure, and at least one window area formed between the above elements.Type: GrantFiled: November 18, 2004Date of Patent: October 30, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Byeong-Hoon Park, Yu-Dong Bae, In Kim, Byung-Kwon Kang, Young-Hyun Kim, Sang-Moon Lee
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Patent number: 7279347Abstract: A method for manufacturing a light-emitting structure of a light-emitting device (LED) is disclosed. The white colored LED includes a resonant cavity structure, producing and mixing lights which may mix into a white colored light in the resonant cavity structure, so that the white colored LED may be more accurately controlled in its generated white colored light, which efficiently reduces deficiency, generates natural white colored light and aids in luminous efficiency promotion. In addition to the resonant cavity structure, the light-emitting structure also includes a contact layer, an n-type metal electrode, and a p-type metal electrode.Type: GrantFiled: November 25, 2003Date of Patent: October 9, 2007Assignee: Super Nova Optoelectronics Corp.Inventors: Schang-Jing Hon, Jenn-Bin Huang
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Patent number: 7279349Abstract: In a dry etching step for an organic material film, a fluorine-containing member is disposed to the periphery of a semiconductor substrate disposed on a lower electrode or a tray for wafer transportation to form fluorine (fluoro-radicals) from the member per se in addition to the fluoric gas added to the etching gas, with a purpose of removing reaction products, thereby removing reaction products deposited on the semiconductor substrate efficiently and stably.Type: GrantFiled: January 10, 2005Date of Patent: October 9, 2007Assignee: OpNext Japan, Inc.Inventors: Yasushi Sakuma, Katsuya Motoda, Kenji Uchida, Ryu Washino
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Patent number: 7276724Abstract: Series interconnection of optoelectronic device modules is disclosed. Each device module includes an active layer disposed between a bottom electrode and a transparent conducting layer. An insulating layer is disposed between the bottom electrode of a first device module and a backside top electrode of the first device module. One or more vias are formed through the active layer, transparent conducting layer and insulating layer of the first device module. Sidewalls of the vias are coated with an insulating material such that a channel is formed through the insulating material to the backside top electrode of the first device module. The channel is at least partially filled with an electrically conductive material to form a plug that makes electrical contact between the transparent conducting layer and the backside top electrode of the first device module.Type: GrantFiled: January 20, 2005Date of Patent: October 2, 2007Assignee: Nanosolar, Inc.Inventors: James R. Sheats, Sam Kao, Gregory A. Miller, Martin R. Roscheisen
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Patent number: 7271019Abstract: Disclosed are a semiconductor device and method of manufacturing the same comprising a substrate, a mesa region adjacent to the substrate, an electroplated metal layer, for reducing the thermal resistance of the device, surrounding the mesa region, an insulator layer separating a side portion of the mesa region from the electroplated metal layer, a heat sink, a bonding layer adjacent to the heat sink, and a second metal layer in between the substrate and the heat sink, wherein the substrate is adjacent to the bonding layer, and wherein the electroplated metal layer dimensioned and configured to have a thickness of at least half a thickness of the mesa region; and to laterally spread heat away from the mesa region. The mesa region comprises a first cladding layer adjacent to the substrate, an active region adjacent the first cladding layer, and a second cladding layer adjacent to the active region.Type: GrantFiled: June 9, 2006Date of Patent: September 18, 2007Assignee: United States of America as represented by the Secretary of the ArmyInventors: John T. Pham, John D. Bruno, Richard L. Tober
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Patent number: 7265389Abstract: A method for fabricating a light emitting diode (LED) is provided. Successively forming a first type doped semiconductor layer, a light emitting layer and a second type doped semiconductor layer on an epitaxy substrate; forming a bonding layer thereon; bonding a transferring substrate with the bonding layer; removing the epitaxy substrate; removing a part of the first type doped semiconductor layer, the light emitting layer and the second type doped semiconductor layer for exposing a part of the bonding layer; patterning the bonding layer to form a first and a second bonding portion isolated from each other, wherein the first type doped semiconductor layer, the light emitting layer and the second type doped semiconductor layer are disposed on the first bonding portion; forming a pad on the first type doped semiconductor layer; and forming a conducting wire for electrically connecting the pad and the second bonding portion.Type: GrantFiled: October 14, 2005Date of Patent: September 4, 2007Assignee: National Central UniversityInventors: Cheng-Yi Liu, Yuan-Tai Lai, Shen-Jie Wang
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Patent number: 7250319Abstract: A method of fabricating quantum features on a substrate from a layer of material selected from materials identified in the III-V periodic groups (e.g., silicon (Si), InP, Si—Ge, and the like) uses sequentially two patterned masks, each mask includes an elongated mask pattern disposed substantially orthogonal to the elongated pattern of the other mask. In one embodiment, the method forms on a semiconductor wafer a plurality of quantum dots having topographic dimensions of about 30 nm or less. In another embodiment, the invention may be halted after a first etch process to form quantum lines.Type: GrantFiled: April 16, 2004Date of Patent: July 31, 2007Assignee: Applied Materials, Inc.Inventors: Wei Liu, Lawrence West
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Patent number: 7244629Abstract: In a vertical cavity surface emitting laser diode manufactured on a non-off-angle substrate with a (100)-oriented plane or the like, anisotropic stress is applied to a central portion of an active layer by forming a asymmetrical oxidation structure in an Al high concentration portion in the mesa, so that polarization controllability of a device can be improved.Type: GrantFiled: November 2, 2004Date of Patent: July 17, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Mizunori Ezaki, Michihiko Nishigaki, Keiji Takaoka
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Patent number: 7195998Abstract: A compound semiconductor device including: an isolated mesa section on which an upper surface having two pairs of parallel sides is formed by mesa etching a compound semiconductor wafer, wherein the mesa section is formed from at least a forward mesa surface which is a mesa section side surface having an obtuse angle against a wafer surface and a backward mesa surface which is a mesa section side surface having an acute angle against the wafer surface, the two mesa surfaces being recognized when viewed from an X direction parallel to one pair of the two parallel sides of the upper surface of the mesa section.Type: GrantFiled: January 13, 2003Date of Patent: March 27, 2007Assignee: Sharp Kabushiki KaishaInventor: Masahiro Ikehara
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Patent number: 7176045Abstract: A laser diode includes an active layer of a group III-V compound semiconductor device containing N and As as the group V elements. The active layer has exposed lateral edges wherein the N atoms are substituted by the As atoms at the exposed lateral edges by an annealing process conducted in a AsH3 atmosphere.Type: GrantFiled: January 9, 2004Date of Patent: February 13, 2007Assignee: Ricoh Company, Ltd.Inventor: Shunichi Sato
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Patent number: 7172914Abstract: A method of forming a semiconductor structure includes forming an isolation region in a semiconductor substrate. A first oxide layer is on the substrate, a first sacrificial layer is on the first oxide layer, and a first nitride layer is on the first sacrificial layer. The first oxide layer may be a screen oxide layer, and the method provides consistency in the thickness of the screen oxide layer.Type: GrantFiled: January 2, 2001Date of Patent: February 6, 2007Assignee: Cypress Semiconductor CorporationInventor: Sundar Narayanan
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Patent number: 7166483Abstract: A light-emitting device comprises a multi-layer structure including one or more active layer configured to irradiate light in response to the application of an electric signal, a transparent passivation layer laid over an outmost surface of the multi-layer stack, a reflector layer laid over the passivation layer, and a plurality of electrode pads coupled with the multi-layer structure. In a manufacture process of the light-emitting device, the reflector layer and the passivation layer are patterned to form at least one opening exposing an area of the multi-layer structure. One electrode pad is formed through the opening of the reflector layer and the passivation layer to connect with the multi-layer structure.Type: GrantFiled: June 17, 2004Date of Patent: January 23, 2007Assignee: Tekcore Co., Ltd.Inventors: Yu-Chuan Liu, Chia-Ming Lee, I-Ling Chen, Jen-Inn Chyi
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Patent number: 7160747Abstract: Methods of forming a semiconductor device can include forming a semiconductor structure on a substrate, the semiconductor structure having mesa sidewalls and a mesa surface opposite the substrate. A contact layer can be formed on the mesa surface wherein the contact layer has sidewalls and a contact surface opposite the mesa surface and wherein the contact layer extends across substantially an entirety of the mesa surface. A passivation layer can be formed on the mesa sidewalls and on portions of the contact layer sidewalls adjacent the mesa surface, and the passivation layer can expose substantially an entirety of the contact surface of the contact layer.Type: GrantFiled: December 19, 2003Date of Patent: January 9, 2007Assignee: Cree, Inc.Inventors: Kevin Ward Haberern, Raymond Rosado, Michael John Bergman, David Todd Emerson
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Patent number: 7157298Abstract: A method of fabricating a surface emitting semiconductor laser includes the following steps. A first laminate of semiconductor layers and a second laminate of semiconductor layers are formed on a substrate. The first laminate includes a first reflection mirror layer of a first conduction type, an active region, a III-V semiconductor layer containing Al, and a second reflection mirror layer of a second conduction type, the second laminate being used for monitoring and having an oxidizable region. The first and second laminates are etched so as to form mesas on the substrate in which side surface of the III-V semiconductor layer contained in the first laminate is exposed. Oxidization of the III-V semiconductor layer from the side surface is started at an oxidization rate.Type: GrantFiled: March 11, 2003Date of Patent: January 2, 2007Assignee: Fuji Xerox Co., Ltd.Inventors: Hideo Nakayama, Akira Sakamoto
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Patent number: 7135411Abstract: Antimony-based semiconductor devices are formed over a substrate structure (10) that includes an antimony-based buffer layer (24) and an antimony-based buffer cap (26). Multiple epitaxial layers (30–42) formed over the substrate structure (10) are dry etched to form device mesas (12) and the buffer cap (26) provides a desirably smooth mesa floor and electrical isolation around the mesas.Type: GrantFiled: August 12, 2004Date of Patent: November 14, 2006Assignee: Northrop Grumman CorporationInventors: Peter S. Nam, Michael D. Lange, Roger S. Tsai
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Patent number: 7129104Abstract: Devices and techniques for coupling radiation to intraband quantum-well semiconductor sensors that are insensitive to the wavelength of the coupled radiation. At least one reflective surface is implemented in the quantum-well region to direct incident radiation towards the quantum-well layers.Type: GrantFiled: April 8, 2003Date of Patent: October 31, 2006Assignee: California Institute of TechnologyInventors: Sarath D. Gunapala, Sumith V. Bandara, John K. Liu
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Patent number: 7125733Abstract: A method for producing an emission module having at least two vertically emitting lasers in which an optically active laser layer is arranged on a substrate and at least one upper covering layer is arranged on said laser layer. In a first etching step, upper mesa regions are formed by etching the upper covering layer, wherein the etching depth of the first etching step is chosen such that the first etching step is ended above the optically active laser layer, and the first etching step is carried out such that the resulting distance between adjacent upper mesa regions is so small that the radiation generated by the finished lasers can be coupled directly into a single optical waveguide. In a second etching step, the optically active layer is severed to form lower mesa regions, the second etching step being a wet-chemical or dry-chemical etching step with a predominantly chemical etching component.Type: GrantFiled: May 6, 2004Date of Patent: October 24, 2006Assignee: Infineon Technologies AGInventor: Gunther Steinle
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Patent number: 7115913Abstract: A TFT array substrate used for a display device and a method of making the same are disclosed. A optically transparent thick resin insulation film 5 is formed on a base substrate and an upper contact hole 51 is perforated through the optically transparent thick resin insulation film 5. A lower contact hole 41 perforated through a gate insulation film 15 and patterning of an ITO film to make a transparent pixel electrode are then collectively carried out under a photoresist pattern 8. Where the photoresist pattern 8 is provided after making the ITO film, an aperture 81 is perforated closer to the center of the upper contact hole 51 at an end portion of a connecting line 14a for a pad and is smaller in diameter by a side etching size plus a margin than the upper contact hole.Type: GrantFiled: March 25, 2003Date of Patent: October 3, 2006Assignee: TFPD CorporationInventor: Hirotaka Shigeno
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Patent number: 7105369Abstract: In one aspect the invention relates to a high bandwidth shallow mesa semiconductor photodiode responsive to incident electromagnetic radiation. The photodiode includes an absorption narrow bandgap layer, a wide bandgap layer disposed substantially adjacent to the absorption layer, a first doped layer having a first conductivity type disposed substantially adjacent to the wide bandgap layer, and a passivation region disposed substantially adjacent to the wide bandgap layer and the first doped layer.Type: GrantFiled: May 28, 2004Date of Patent: September 12, 2006Assignee: Multiplex, Inc.Inventor: Ping Yuan
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Patent number: 7105448Abstract: A method for peeling off a thin film semiconductor element over an insulating surface by using a void, and a method for manufacturing a semiconductor device by transferring the peeled semiconductor element. According to the peeling method of the invention, a first base layer having a plurality of recessed portions is formed over a substrate, and a second base layer having a plurality of voids is formed on the recessed portions of the first base layer. On the second base layer, a third base layer is formed and a semiconductor element is formed thereon. Then, by separating the second base layer at an intersecting surface with the voids, the semiconductor element is peeled off from the substrate.Type: GrantFiled: February 27, 2004Date of Patent: September 12, 2006Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Toru Takayama, Yasuyuki Arai
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Patent number: 7098059Abstract: A surface emitting semiconductor laser includes a substrate, a first semiconductor multilayer reflector formed on the substrate, an active region formed on the first semiconductor multilayer reflector, a second semiconductor multilayer reflector formed on the active region, a current confinement layer interposed between the first and second semiconductor multilayer reflectors and partially including an oxide region, and an insulating layer formed on a coated surface provided by a semiconductor layer which is part of the first semiconductor multilayer reflector and is revealed after removal of a surface oxidation layer.Type: GrantFiled: April 20, 2005Date of Patent: August 29, 2006Assignee: Fuji Xerox Co., Ltd.Inventors: Hiromi Otoma, Jun Sakurai
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Patent number: 7087448Abstract: This invention relates to generally to semiconductor devices, for example lasers and more particularly to single frequency lasers and is directed at overcoming problems associated with the manufacture of these devices. In particular, a laser device is provided formed on a substrate having a plurality of layers (1,2,3,4,5), the laser device comprising at least one waveguide (for example a ridge) established by the selective removal of sections of at least one of the layers. The ridge (100;101) has at least one defect defining region (104), the at least one defect defining region of the ridge defining a defect in the ridge. The width of the ridge is greater in the at least one defect defining region of the ridge than in adjacent sections of the ridge.Type: GrantFiled: October 11, 2001Date of Patent: August 8, 2006Assignee: University of Ireland, CorkInventor: Brian Michael Corbett
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Patent number: 7087449Abstract: An active semiconductor device, such as, buried heterostructure semiconductor lasers, LEDs, modulators, photodiodes, heterojunction bipolar transistors, field effect transistors or other active devices, comprise a plurality of semiconductor layers formed on a substrate with one of the layers being an active region. A current channel is formed through this active region defined by current blocking layers formed on adjacent sides of a designated active region channel where the blocking layers substantially confine the current through the channel. The blocking layers are characterized by being an aluminum-containing Group III–V compound, i.e., an Al-III–V layer, intentionally doped with oxygen from an oxide source. Also, wet oxide process or a deposited oxide source may be used to laterally form a native oxide of the Al-III–V layer. An example of a material system for this invention useful at optical telecommunication wavelengths is InGaAsP/InP where the Al-III–V layer comprises InAlAs:O or InAlAs:O:Fe.Type: GrantFiled: June 24, 2004Date of Patent: August 8, 2006Assignee: Infinera CorporationInventors: Fred A. Kish, Jr., Sheila K. Mathis, Charles H. Joyner, Richard P. Schneider
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Patent number: 7084433Abstract: In this semiconductor laser device, an InGaP etching block layer 11 as an etching selection layer having etching selectivity for an n-type AlInP current block layer 10, which is a non-optical-absorption layer, is formed on the n-type current block layer 10. Since this etching block layer 11 prevents the current block layer 10 on both sides of a ridge 20 from being etched during manufacture, a contact layer 12 can be prevented from entering gaps between the sides of this ridge 20 and the current block layer 10. Therefore, light oscillating in an active layer 4 is taken out from a device end surface without being absorbed in the contact layer 12. According to this semiconductor laser device, an oscillation threshold current and an operation current can be maintained low, deterioration of differential quantum efficiency can be prevented and reliability can be improved.Type: GrantFiled: March 4, 2003Date of Patent: August 1, 2006Assignee: Sharp Kabushiki KaishaInventors: Hiroyuki Hosoba, Atsuo Tsunoda, Hiroshi Hayashi
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Patent number: 7083994Abstract: This invention generally relates to semiconductor devices, for example lasers and more particularly to single frequency lasers and is directed at overcoming problems associated with the manufacture of these devices. In particular, a laser device is provided formed on a substrate having a plurality of layers (1,2,3,4,5), the laser device comprising at least one waveguide (for example a ridge) established by the selective removal of sections of at least one of the layers. Wherein alignment features are provided on the device to facilitate subsequent placement.Type: GrantFiled: October 7, 2002Date of Patent: August 1, 2006Assignee: Eblana Photonics LimitedInventor: James O'Gorman
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Patent number: 7084044Abstract: The present invention provides an optoelectronic device and a method of manufacture thereof. In one embodiment, the method of manufacturing the optoelectronic device may include creating a multilayered optical substrate and then forming a self aligned dual mask over the multilayered optical substrate. The method may further include etching the multilayered optical substrate through the self aligned dual mask to form a mesa structure.Type: GrantFiled: June 7, 2004Date of Patent: August 1, 2006Assignee: TriQuint Technology Holding Co.Inventors: Charles W. Lentz, Bettina A. Nechay, Abdallah Ougazzaden, Padman Parayanthal, George J. Przybylek
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Patent number: 7083996Abstract: A nitride semiconductor device includes a GaN substrate having a single-crystal GaN layer at least on its surface and plurality of device-forming layers made of nitride semiconductor. The device-forming layer contacting the GaN substrate has a coefficient of thermal expansion smaller than that of GaN, so that a compressive strain is applied to the device-forming layer. This result in prevention of crack forming in the device-forming layers, and a lifetime characteristics of the nitride semiconductor device is improved.Type: GrantFiled: September 29, 2004Date of Patent: August 1, 2006Assignee: Nichia CorporationInventors: Shinichi Nagahama, Shuji Nakamura
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Patent number: 7078257Abstract: A method of fabricating a surface emitting semiconductor laser includes a first step of forming, on a substrate, multiple monitor-use semiconductor layers having stripes radiating from a center of the substrate, and a laser portion that includes semiconductor layers and is located on the periphery of the multiple monitor-use semiconductor layers, a second step of monitoring oxidized conditions on the multiple monitor-use semiconductor layers when a selectively oxidized region is formed in the laser portion, and a third step of controlling oxidization of the selectively oxidized region on the basis of the oxidized conditions thus monitored.Type: GrantFiled: March 11, 2003Date of Patent: July 18, 2006Assignee: Fuji Xerox Co., LtdInventors: Akira Sakamoto, Hideo Nakayama, Yasuaki Miyamoto, Jun Sakurai
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Patent number: 7078256Abstract: A nitride semiconductor LED improved in lighting efficiency and a fabrication method thereof, in which an n-doped semiconductor layer is formed on a substrate. An active layer is formed on the n-doped semiconductor layer to expose at least a partial area of the n-doped semiconductor layer. A p-doped semiconductor layer is formed on the active layer. A p+-doped semiconductor layer is formed on the p-doped semiconductor layer. An n+-doped semiconductor layer is formed in at least a partial upper region of the p+-doped semiconductor layer via n-dopant ion implantation. The n+-doped semiconductor layer cooperates with an underlying partial region of the p+-doped semiconductor layer to realize a reverse bias tunneling junction. Also, an upper n-doped semiconductor layer is formed on the n+-doped semiconductor layer to realize lateral current spreading. The invention can improve lighting efficiency by using the reverse bias tunneling junction and/or the lateral current spreading.Type: GrantFiled: June 25, 2004Date of Patent: July 18, 2006Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Yung Ho Ryu, Kee Jeong Yang, Bang Won Oh, Jin Sub Park, Young Hoon Kim
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Patent number: 7074633Abstract: Provided is a nitride semiconductor laser diode and a method for manufacturing the same. The method includes the steps of: a) forming a nitride semiconductor layer by orderly evaporating a substrate, an undoped GaN layer, an n-type layer, a multi-quantum well (MQW), an electron blocking layer (EBL) and a p-type layer; b) eliminating the substrate and the undoped GaN layer in the nitride semiconductor layer by lapping the substrate and the undoped GaN layer; and c) forming a ridge structure on the n-type layer. According to the present invention, a ridge structure is easily formed on an n-type layer, I-V characteristics are improved, heat generation is suppressed and an operational lifetime is extended.Type: GrantFiled: January 18, 2005Date of Patent: July 11, 2006Assignee: LG Electronics Inc.Inventor: Sungwon Khym
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Patent number: 7067339Abstract: At the time of selective growth of an active layer on a substrate, crystal is previously grown in an active layer non-growth region, and the active layer is grown in an active layer selective growth region. With this configuration, a source supplied to the non-growth region is incorporated in the deposited crystal from the initial stage of growth, so that the supplied amount of the source to the active layer selective growth region is kept nearly at a constant value over the entire period of growth of the active layer, to eliminate degradation of characteristics of the device due to a variation in growth rate of the active layer. In particular, the selective growth method is effective in fabrication of a semiconductor light emitting device including a cladding layer, a guide layer, and an active layer, each of which is formed by selective growth, wherein the active layer has multiple quantum wells.Type: GrantFiled: June 3, 2005Date of Patent: June 27, 2006Assignee: Sony CorporationInventors: Goshi Biwa, Hiroyuki Okuyama
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Patent number: 7063997Abstract: A process for producing a nitride semiconductor light-emitting device includes the steps of preparing a substrate, growing a p-type nitride semiconductor layer on the substrate by the MOCVD process using hydrazine-based gas as a nitrogen precursor and N2 gas as a carrier gas, forming an active layer on the p-type nitride semiconductor layer, forming an n-type conductive nitride semiconductor layer on the active layer, and forming p- and n-electrodes in electrical connection with the p- and n-type nitride semiconductors, respectively.Type: GrantFiled: July 20, 2004Date of Patent: June 20, 2006Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Dong Hyun Cho, Masayoshi Koike, Hun Joo Hahm
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Patent number: 7060542Abstract: Disclosed are a display system and a method of producing the same. In the present invention, a hexagonal pyramid shaped GaN semiconductor light-emitting device selectively crystal-grown is fixed on an upper surface of a substrate by embedding it in an insulation layer formed of an epoxy resin. Then the insulation layer is selectively dry etched in an oxygen plasma atmosphere to expose an upper end portion of the GaN semiconductor light-emitting device. A conductor film is formed on the entire surface, and a required portion of the conductor film is left as a lead-out electrode while the unrequired portion is removed by lithography.Type: GrantFiled: September 1, 2004Date of Patent: June 13, 2006Assignee: Sony CorporationInventors: Hideharu Nakajima, Masato Doi
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Patent number: 7049630Abstract: An OLED device having pillars with a cross section that is wider on the top. The pillars structure a conductive layer during deposition into distinct portions located between the pillars and on the top of the pillars. In one embodiment, the grooves between the pillars extend outside the electrode region to prevent shorting of adjacent electrodes.Type: GrantFiled: November 24, 2003Date of Patent: May 23, 2006Assignee: Osram Opto Semiconductors (Malaysia) Sdn. BhdInventors: Hooi Bin Lim, Hagen Klausmann, Bernd Fritz
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Patent number: 7037733Abstract: When the emissivity ? on the reverse face of a substrate 10 is measured during annealing processing for the substrate 10, films made from a material that varies the emissivity ?, such as a first DPS film 15 used for forming a plug 15A, a second DPS film 17 used for forming a capacitor lower electrode 17A and a third DPS film 20 used for forming a capacitor upper electrode 20A, are formed on the top face of the substrate 10. On the other hand, no film made from a material that varies the emissivity ?, such as a DPS film, is formed on the reverse face of the substrate 10.Type: GrantFiled: July 1, 2002Date of Patent: May 2, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Satoshi Shibata, Junji Hirase, Tatsuo Sugiyama, Emi Kanasaki, Fumitoshi Kawase, Yasushi Naito
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Patent number: 7037742Abstract: Light emitting diodes include a substrate, an epitaxial region on the substrate that includes therein a diode region and a multilayer conductive stack on the epitaxial region opposite the substrate. A passivation layer extends at least partially on the multilayer conductive stack opposite the epitaxial region, to define a bonding region on the multilayer conductive stack opposite the epitaxial region. The passivation layer also extends across the multilayer conductive stack, across the epitaxial region and onto the substrate. The multilayer conductive stack can include an ohmic layer on the epitaxial region opposite the substrate, a reflector layer on the ohmic layer opposite the epitaxial region and a tin barrier layer on the reflector layer opposite the ohmic layer. An adhesion layer also may be provided on the tin barrier layer opposite the reflector layer. A bonding layer also may be provided on the adhesion layer opposite the tin barrier layer.Type: GrantFiled: April 15, 2004Date of Patent: May 2, 2006Assignee: Cree, Inc.Inventors: David B. Slater, Jr., Bradley E. Williams, Peter S. Andrews
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Patent number: 7033853Abstract: The invention is directed to a vertically emitting laser and a method of manufacturing such a laser having a current aperture and a semiconductor relief. The semiconductor relief and the current aperture are defined in the same processing operation, thereby causing the semiconductor relief and the current aperture to be substantially self-aligned with respect to one another. In addition, such processing results in an area ratio of the semiconductor relief and the current aperture to be substantially self-scaling with respect to processing variations.Type: GrantFiled: March 26, 2004Date of Patent: April 25, 2006Assignee: Infineon Technologies AGInventor: Dipl.-Ing. Daniel Supper
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Patent number: 7008810Abstract: A method for fabricating at least one mesa or ridge structure in a layer or layer sequence, in which a sacrificial layer (4) is applied and patterned above the layer or layer sequence. A mask layer is applied and patterned above the sacrificial layer for definition of the mesa or ridge dimensions. The sacrificial layer (4) and of the layer or layer sequence are removed so that the mesa or ridge structure is formed in the layer or layer sequence. A part of the sacrificial layer (4) is selectively removed from the side areas thereof which have been uncovered in the previous step, so that a sacrificial layer remains which is narrower in comparison with a layer that has remained above the sacrificial layer as seen from the layer or layer sequence. A coating is applied at least to the sidewalls of the structure produced in the previous steps so that the side areas of the residual sacrificial layer are not completely overformed by the coating material.Type: GrantFiled: March 19, 2004Date of Patent: March 7, 2006Assignee: Osram Opto Semiconductors GmbHInventors: Christine Höss, Andreas Weimar, Andreas Leber, Alfred Lell, Helmut Fischer, Volker Harle
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Patent number: 6995030Abstract: An optoelectronic semiconductor chip has an active layer containing a photon-emitting zone. The active layer is attached to a carrier member at a bonding side of the active layer. The active layer has at least one recess therein with a cross-sectional area that decreases with increasing depth into said active layer proceeding from said bonding side.Type: GrantFiled: January 17, 2003Date of Patent: February 7, 2006Assignee: Osram GmbHInventors: Stefan Illek, Klaus Streubel, Walter Wegletter, Andreas Ploessl, Ralph Wirth
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Patent number: 6991950Abstract: There is provided a semiconductor laser element which can change band gap wavelengths without change of composition of a multiple quantum well active layer and a method for fabricating a semiconductor laser module. In the method for fabricating a semiconductor laser element wherein a multiple quantum well active layer is formed on a semiconductor substrate with a crystal growth method, an insulation film is formed at the upper part of the multiple quantum well active layer, an electrode film is moreover formed on the insulation film and at least a part of the electrode film is electrically connected to the multiple quantum well active layer, distortion of the multiple quantum well active layer is controlled in the semiconductor laser element fabrication process after the process of the crystal growth method.Type: GrantFiled: February 5, 2003Date of Patent: January 31, 2006Assignees: Hitachi, Ltd., OpNext Japan, IncInventors: Hiroshi Moriya, Kisho Ashida, Toshinori Hirataka, Mamoru Morita
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Patent number: 6989299Abstract: A method for fabricating on-chip spacers for a TFT panel exposes a photoresist layer on top of the TFT panel using two exposure processes, one through the bottom of the TFT and the other through a mask over the TFT panel. The exposure process through the bottom exposes all photoresist covering windows on the TFT panel and leaves all photoresist corresponding to an opaque grid corresponding a TFT driving circuit. A second exposure process through a mask above the photoresist leaves part of the photoresist in the opaque grid unexposed. The exposed photoresist is removed leaving on-chip spacers only on the opaque grid. Therefore, the on-chip spacers can not affect the display quality and can be easily formed on a high dpi TFT panel.Type: GrantFiled: February 25, 2003Date of Patent: January 24, 2006Assignee: Forhouse CorporationInventors: Yuan-Tung Dai, Tsung-Neng Liao, Chun-Chi Lee