Mesa Formation Patents (Class 438/39)
  • Publication number: 20100080256
    Abstract: Systems and methods for electrically pumped, surface-emitting and edge emitting ZnO ultraviolet diode lasers are disclosed. The ZnO diode laser may be fabricated using growth processes (e.g., MBE) to form Sb-doped ZnO as a p-type layer and doped ZnO as an n-type layer. ZnO-based quantum well structures may be further formed in between the n- and p-type ZnO layers. The ZnO layers and quantum wells may be grown in columnar structures which act as resonant cavities for generated light, significantly improving light amplification and providing high power output. For example, ultraviolet lasing at around 380 nm was demonstrated at about room temperature at a threshold current density of about 10 A/cm2. The output power was further measured to be about 11.3 ?W at about 130 mA driving current.
    Type: Application
    Filed: September 30, 2009
    Publication date: April 1, 2010
    Applicant: The Regents of the University of California
    Inventors: Jianlin Liu, Sheng Chu
  • Patent number: 7687290
    Abstract: A method for manufacturing a semiconductor optical device includes: forming a laminated semiconductor structure of GaN-based materials on a semiconductor wafer, the laminated semiconductor structure forming a laser diode of GaN-based materials, including an active layer having a quantum well structure; cleaving the semiconductor wafer including the laminated semiconductor structure to expose a cleaved end face of the laminated semiconductor structure; and forming an SiO2 film on the cleaved end face and performing a heat treatment to cause Ga vacancy diffusion in the active layer to disorder the quantum well structure of the active layer.
    Type: Grant
    Filed: March 17, 2008
    Date of Patent: March 30, 2010
    Assignee: Mitsubishi Electric Corporation
    Inventor: Shinji Abe
  • Patent number: 7682855
    Abstract: A substrate-free light emitting diode (LED) including an epitaxy layer, a conductive supporting layer, and a first contact pad is provided. The epitaxy layer includes a first type doped semiconductor layer, a light emitting layer, and a second type doped semiconductor layer. The light emitting layer is disposed on the first type doped semiconductor layer, and a portion of the first type doped semiconductor layer is exposed. The second type doped semiconductor layer and the conductive supporting layer are sequentially disposed on the second type doped semiconductor layer. The first contact pad is disposed on the exposed first type doped semiconductor layer and electrically connected thereto. The first contact pad and the conductive supporting layer serving as an electrode are disposed on the same side of the epitaxy layer to avoid the light shielding effects of the electrode to improve the front light emitting efficiency of the LED.
    Type: Grant
    Filed: July 31, 2006
    Date of Patent: March 23, 2010
    Assignee: Industrial Technology Research Institute
    Inventors: Chien-Cheng Yang, Zhi-Cheng Hsiao, Gen-Wen Hsieh
  • Patent number: 7678597
    Abstract: A method of manufacturing a semiconductor device provides a semiconductor device with a gallium-nitride-based semiconductor structure that allows long-term stable operation without degradation in device performance. After formation of an insulation film on a surface other than on a ridge surface, an oxygen-containing gas such as O2, O3, NO, N2O, or NO2 is supplied to oxidize a p-type GaN contact layer from the surface and to thereby form an oxide film on the surface of the p-type GaN contact layer. Then, a p-type electrode that establishes contact with the p-type GaN contact layer is formed by evaporation or sputtering on the oxide film and on the insulation film. Heat treatment is subsequently performed at temperatures between 400 and 700° C. in an atmosphere containing a nitrogen-containing gas such as N2 or NH3 or an inert gas such as Ar or He.
    Type: Grant
    Filed: November 26, 2008
    Date of Patent: March 16, 2010
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kenichi Ohtsuka, Yoichiro Tarui, Yosuke Suzuki, Katsuomi Shiozawa, Kyozo Kanamoto, Toshiyuki Oishi, Yasunori Tokuda, Tatsuo Omori
  • Patent number: 7678648
    Abstract: Novel etch techniques are provided for shaping silicon features below the photolithographic resolution limits. FinFET devices are defined by recessing oxide and exposing a silicon protrusion to an isotropic etch, at least in the channel region. In one implementation, the protrusion is contoured by a dry isotropic etch having excellent selectivity, using a downstream microwave plasma etch.
    Type: Grant
    Filed: July 14, 2006
    Date of Patent: March 16, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Kevin J. Torek, Mark Fischer, Robert J. Hanson
  • Patent number: 7678594
    Abstract: An integrated optical device comprising a first semiconductor optical element provided on a first region of the main face of a substrate and a second semiconductor optical element provided on a second region and optically coupled to the first semiconductor optical element is fabricated. A first III-V compound semiconductor layer containing Al element is formed on the main face. A second III-V compound semiconductor layer for forming the first semiconductor optical element is then formed on the first III-V compound semiconductor layer. An etching mask M is formed on the first region. The end point of the dry etching is detected by using the etching mask M to dry-etch the second III-V compound semiconductor layer while detecting Al element. The first semiconductor optical element is thus formed. The second semiconductor optical element is formed on the second region.
    Type: Grant
    Filed: May 29, 2007
    Date of Patent: March 16, 2010
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Tomokazu Katsuyama
  • Patent number: 7670874
    Abstract: A method involves plating pillars of electrically conductive material up from a seed layer located on a substrate, surrounding the pillars with a fill material so that the pillars and fill material collectively define a first package, and removing the substrate from the first package.
    Type: Grant
    Filed: February 16, 2007
    Date of Patent: March 2, 2010
    Inventor: John Trezza
  • Publication number: 20100046566
    Abstract: A semiconductor light emitting device includes at least a first cladding layer of a first conductive type, an active layer, a second cladding layer of a second conductivity type, and a contact layer of the second conductivity type stacked in this order on a substrate, and further includes a ridge portion including the second cladding layer and the contact layer. On the second cladding layer, are formed a dielectric film which covers the ridge portion and has an opening selectively exposing a top of the ridge portion, and an electrode in contact with a top surface and a side surface of the contact layer exposed from the dielectric film. The dielectric film includes a no-current injection region which covers an end of the ridge portion to block current injection to the active layer, and the no-current injection region of the dielectric film is in contact with the contact layer.
    Type: Application
    Filed: May 29, 2009
    Publication date: February 25, 2010
    Inventor: Akiyoshi KUDO
  • Patent number: 7666694
    Abstract: An improved throughput can be presented, since an influence of the deterioration in crystallinity created in the epitaxial layer can be eliminated by a simple and easy method, and a semiconductor laser device having stabilized properties such as threshold current, slope efficiency, device life time and the like can be presented. A method for manufacturing a semiconductor laser device according to the present invention comprises: forming partially a diffraction grating on a surface of a semiconductor substrate or on a film on the surface of the semiconductor substrate; and forming a multiple-layered film by forming an epitaxial layer on a surface of the diffraction grating. The operation of forming the diffraction grating includes an operation of forming the diffraction grating so that a width of the diffraction grating in a direction that is orthogonal to a cavity direction of the semiconductor laser device is presented as a width equal to or longer than a sum of a mesa width and 30 ?m.
    Type: Grant
    Filed: September 18, 2006
    Date of Patent: February 23, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Masahide Kobayashi, Shotaro Kitamura
  • Patent number: 7662672
    Abstract: A manufacturing process of a leadframe-based BGA package is disclosed. A leadless leadframe with an upper layer and a lower layer is provided for the package. The upper layer includes a plurality of ball pads, and the lower layer includes a plurality of sacrificial pads aligning and connecting with the ball pads. A plurality of leads are formed in either the upper layer or the lower layer to interconnect the ball pads or the sacrificial pads. An encapsulant is formed to embed the ball pads after chip attachment and electrical connections. During manufacturing process, a half-etching process is performed after encapsulation to remove the sacrificial pads to make the ball pads electrically isolated and exposed from the encapsulant for solder ball placement where the soldering areas of the ball pads are defined without the need of solder mask(s) to solve the problem of solder bleeding of the solder balls on the leads or the undesired spots during reflow. Moreover, mold flash can easily be detected and removed.
    Type: Grant
    Filed: May 19, 2008
    Date of Patent: February 16, 2010
    Assignees: ChipMos Technologies (Bermuda) Ltd., ChipMos Technologies Inc.
    Inventor: Hung-Tsun Lin
  • Publication number: 20100029030
    Abstract: Provided is a process for producing a surface emitting laser including a surface relief structure provided on laminated semiconductor layers, including the steps of transferring, to a first dielectric film, a first pattern for defining a mesa structure and a second pattern for defining the surface relief structure in the same process; and forming a second dielectric film on the first dielectric film and a surface of the laminated semiconductor layers to which the first pattern and the second pattern have been transferred. Accordingly, a center position of the surface relief structure can be aligned with a center position of a current confinement structure at high precision.
    Type: Application
    Filed: July 27, 2009
    Publication date: February 4, 2010
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Tatsuro Uchida, Mitsuhiro Ikuta, Tetsuya Takeuchi
  • Publication number: 20100009483
    Abstract: An exemplary method includes the following steps. First, a substrate is provided. Second, a nitride-based multi-layered structure is epitaxially grown on the substrate. The multi-layered structure includes a first-type layer, an active layer, and a second-type layer arranged one on the other in that order along a direction away from the substrate. A crystal growth orientation of the multi-layered structure intersects with a <0001> crystal orientation thereof. Thirdly, the multi-layered structure is patterned to form a mesa structure thereof, wherein the first-type layer is partially exposed to form an exposed portion. The mesa structure has a top surface facing away from the substrate, and side surfaces adjacent to the top surface. Fourthly, a first-type electrode and a second-type electrode are formed in ohmic contact with the first-type layer and the second-type layer, respectively. Finally, the top and side surfaces of the patterned multi-layered structure are wet etched.
    Type: Application
    Filed: September 16, 2009
    Publication date: January 14, 2010
    Applicant: FOXSEMICON INTEGRATED TECHNOLOGY, INC.
    Inventor: WEN-JANG JIANG
  • Publication number: 20100003778
    Abstract: A method of manufacturing a semiconductor laser includes sequentially forming a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer on top of one another on a semiconductor substrate; forming a ridge in the second conductivity type semiconductor layer; forming a first insulating film on the second conductivity type semiconductor layer at a first temperature; forming a second insulating film on the first insulating film at a second temperature, lower than the first temperature; and forming an electrode on the second insulating film.
    Type: Application
    Filed: November 20, 2008
    Publication date: January 7, 2010
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Hitoshi Tada, Tsutomu Yamaguchi, Zempei Kawazu, Yuji Okura
  • Patent number: 7642108
    Abstract: A photonic crystal light emitting diode (“PXLED”) is provided. The PXLED includes a periodic structure, such as a lattice of holes, formed in the semiconductor layers of an LED. The parameters of the periodic structure are such that the energy of the photons, emitted by the PXLED, lies close to a band edge of the band structure of the periodic structure. Metal electrode layers have a strong influence on the efficiency of the PXLEDs. Also, PXLEDs formed from GaN have a low surface recombination velocity and hence a high efficiency. The PXLEDs are formed with novel fabrication techniques, such as the epitaxial lateral overgrowth technique over a patterned masking layer, yielding semiconductor layers with low defect density. Inverting the PXLED to expose the pattern of the masking layer or using the Talbot effect to create an aligned second patterned masking layer allows the formation of PXLEDs with low defect density.
    Type: Grant
    Filed: October 8, 2007
    Date of Patent: January 5, 2010
    Assignee: Philips Lumileds Lighting Company, LLC
    Inventors: Michael R. Krames, Mihail M. Sigalas, Jonathan J. Wierer, Jr.
  • Publication number: 20090316744
    Abstract: A semiconductor laser including: a nitride III-V compound semiconductor substrate configured to have a first planar area, a second planar area, and a third planar area in a major surface, the first planar area being formed of a C-plane, the second planar area being continuous with the first planar area and being formed of a semipolar plane inclined to the first planar area, the third planar area being continuous with the second planar area and being formed of a C-plane parallel to the first planar area; a first cladding layer configured to be composed of a nitride III-V compound semiconductor on the major surface of the nitride III-V compound semiconductor substrate; an active layer configured to be composed of a nitride III-V compound semiconductor that exists on the first cladding layer and contains In; and a second cladding layer configured to be composed of a nitride III-V compound semiconductor on the active layer.
    Type: Application
    Filed: June 18, 2009
    Publication date: December 24, 2009
    Applicant: Sony Corporation
    Inventor: Toshiyuki OBATA
  • Publication number: 20090305447
    Abstract: A method of forming a gain guide implant for a vertical cavity surface emitting laser (VCSEL) comprises implanting ions into a wafer to simultaneously form a first non-conducting portion of the gain guide implant spaced apart from an active region and a second non-conducting portion of the gain guide implant occupying the active region, the first non-conducting portion laterally offset relative to the second non-conducting portion.
    Type: Application
    Filed: June 6, 2008
    Publication date: December 10, 2009
    Applicant: FINISAR CORPORATION
    Inventor: James K. GUENTER
  • Patent number: 7625778
    Abstract: A substrate-free LED device is provided. The LED device comprises a substrate, an epitaxial layer disposed on the substrate, a first electrode disposed on a portion of the epitaxial layer, a second electrode disposed on another portion of the epitaxial layer, and a protection layer, disposed over the epitaxial layer. It is noted that in the LED device, the substrate comprises, for example but not limited to, high heat-sink substrate, and the protection layer comprises, for example but not limited to, high heat-sink, high transparent material.
    Type: Grant
    Filed: June 8, 2005
    Date of Patent: December 1, 2009
    Assignee: Chunghwa Picture Tubes, Ltd.
    Inventor: Ching-Chung Chen
  • Publication number: 20090289541
    Abstract: A method of forming a display device is provided.
    Type: Application
    Filed: May 19, 2009
    Publication date: November 26, 2009
    Applicant: TPO DISPLAYS CORP.
    Inventors: Tsung-Yen LIN, Chih-Hung PENG, Chien-Peng WU, Shan-Hung TSAI, Yi Chun YEH
  • Publication number: 20090278140
    Abstract: A manufacturing method of a semiconductor device comprises the steps of: providing a substrate; forming a plurality of grooves on the substrate by photolithograph etching or laser engraving, wherein the plurality of grooves divides a surface of the substrate into a plurality of mesas and the substrate is a patterned substrate; and growing a semiconductor device (e.g. photo-electronic device or LED) on the patterned substrate. The semiconductor device comprises at least one layer, wherein the layer directly disposed on the patterned substrate is the first layer. The first layer comprises a plurality of separated regions divided by the grooves.
    Type: Application
    Filed: April 30, 2009
    Publication date: November 12, 2009
    Applicant: ADVANCED OPTOELECTRONIC TECHNOLOGY INC.
    Inventors: SHIH CHENG HUANG, PO MIN TU, SHIH HSIUNG CHAN
  • Publication number: 20090275160
    Abstract: After a p-type cladding layer, an etching rate reducing layer and a p-type contact layer are formed in order on an n-type substrate, an etching mask is formed. Then, by using the etching mask, the p-type contact layer, the etching rate reducing layer and the p-type cladding layer are partially etched in the region outside the etching mask with an etchant. At this time, the etching rate of the layers by the etchant is slower in the etching rate reducing layer than in the p-type cladding layer and the p-type contact layer. Then, a metal thin film is formed such that the film continuously coats an upper surface and side surfaces of a ridge consisting of the above layers left after the etching step. A normal vector at a surface coated with the thin film has an upward component.
    Type: Application
    Filed: July 9, 2009
    Publication date: November 5, 2009
    Inventors: Shuichi HIRUKAWA, Katsuhiko Kishimoto
  • Publication number: 20090267195
    Abstract: A semiconductor device of present invention comprises a layered structure including a cladding layer with a first conductivity, an active layer, and a cladding layer with a second conductivity which are successively grown on a semiconductor substrate of (001) orientation, and an embedding layer covering both side surfaces of the layered structure in a widthwise direction across a longitudinal direction of the layered structure in a plane parallel to a surface of the semiconductor substrate. A portion of side surfaces of the active layer in the widthwise direction lies parallel to at least (010) or (100) surface.
    Type: Application
    Filed: December 19, 2006
    Publication date: October 29, 2009
    Applicant: NEC CORPORATION
    Inventor: Tomoaki Kato
  • Publication number: 20090268773
    Abstract: A surface emitting laser element that includes a cylindrical mesa post in which a plurality of semiconductor layers including an active layer is grown and that emits a laser light in a direction perpendicular to a substrate surface, the surface emitting laser element including a dielectric multilayer film on a top surface of the mesa post in at least a portion over a current injection area of the active layer; and a dielectric portion that includes layers fewer than layers of the dielectric multilayer film and that is arranged on a portion excluding the portion over the current injection area on the top surface of the mesa post and on at least part of a side surface of the mesa post.
    Type: Application
    Filed: April 24, 2008
    Publication date: October 29, 2009
    Applicant: THE FURUKAWA ELECTRIC CO.,LTD.,
    Inventors: Norihiro IWAI, Takeo Kageyama, Kinuka Tanabe
  • Patent number: 7602830
    Abstract: A monolithic semiconductor laser having plural semiconductor lasers having different emission wavelengths from each other, including: a semiconductor substrate; a first double hetero-structure formed within a first area on the semiconductor substrate and having first clad layers disposed above and below a first active layer; and a second double hetero-structure formed within a second area on the semiconductor substrate and having second clad layers disposed above and below a second active layer. The first and second active layers are made of different semiconductor materials from each other. The first clad layers above and below the first active layer are of approximately the same semiconductor materials and the second clad layers above and below the second active layer are of approximately the same semiconductor materials.
    Type: Grant
    Filed: July 20, 2007
    Date of Patent: October 13, 2009
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takehiro Nishida, Motoharu Miyashita, Tsutomu Yamaguchi
  • Publication number: 20090252190
    Abstract: In a method of fabricating a semiconductor optical device, a semiconductor region is formed by growing an InP lower film, a active region, an InP upper film and a capping film on a substrate sequentially. Material of the capping film is different from that of InP. Next, a mask is formed on the capping film, and the semiconductor region is etched using the mask to form a semiconductor stripe mesa, which includes an InP lower cladding layer, a active layer, an InP upper cladding layer and a capping layer. The active layer comprises aluminum-based III-V compound. A width of the top surface of the capping layer is greater than that of a width of the bottom surface of the capping layer. A width of the top surface of the InP upper cladding layer is smaller than that of the bottom surface of the InP upper cladding layer. The minimum width of the semiconductor mesa is in the InP upper cladding layer.
    Type: Application
    Filed: March 30, 2009
    Publication date: October 8, 2009
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Manabu YOSHIMURA, Nobuyuki Ikoma, Kenji Hiratsuka
  • Patent number: 7585688
    Abstract: A method for manufacturing a semiconductor optical device includes: forming a first resist pattern on a top surface of a laminated semiconductor structure; forming channels and a waveguide ridge by dry etching using the first resist pattern as a mask; forming an SiO2 film on the waveguide ridge and the channels, leaving the first resist pattern on a top surface of the waveguide ridge; forming a second resist pattern covering the SiO2 film on the channels, and exposing the top surface of the SiO2 film on top of the waveguide ridge; removing the SiO2 film by dry etching using the second resist pattern as a mask; removing the first and second resist patterns by a wet method; and forming a p-side electrode.
    Type: Grant
    Filed: February 28, 2008
    Date of Patent: September 8, 2009
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takafumi Oka, Shinji Abe
  • Publication number: 20090219966
    Abstract: A laser diode structure that includes two different insulator layers, one to maintain good optical confinement, typically located at the sides of the laser ridge, and another to improve the heat dissipation properties, typically located on the etched surfaces away from the ridge.
    Type: Application
    Filed: March 3, 2008
    Publication date: September 3, 2009
    Inventors: Wei-Sin TAN, Jennifer Mary Barnes
  • Publication number: 20090209055
    Abstract: A process for the semiconductor laser diode is disclosed, which prevents the abnormal growth occurred at the second growth for the burying region of the buried hetero structure. The ICP (Induction-Coupled Plasma) CVD apparatus forms a silicon oxide file with a thickness of above 2 ?m as adjusting the bias power PBIAS. Patterning the silicon oxide mask and dry-etching the semiconductor layers, a mesa structure including the active layer may be formed. As leaving the patterned silicon oxide film, the second growth for the burying region buries the mesa structure. The residual stress of the silicon oxide film is ?250 to ?150 MPa at a room temperature, while, it is ?200 to 100 MPa at temperatures from 500 to 700° C.
    Type: Application
    Filed: January 6, 2009
    Publication date: August 20, 2009
    Inventors: Takeshi Kishi, Tetsuya Hattori, Kazunori Fujimoto
  • Publication number: 20090203161
    Abstract: The present invention provides a laser diode with a current blocking layer without a pn-junction. The laser diode includes a lower cladding layer, an active region and an upper cladding layer on the GaAs substrate in this order. The active region includes first and second regions. The upper cladding layer, which includes a ridge structure, locates on the first region, while, the current blocking region is on the second region of the active region so as to sandwich the ridge structure. The current blocking layer of the invention is made of one of un-doped GaInP and un-doped AlGaInP grown at a relatively low temperature and shows high resistance greater than 105 ?·cm.
    Type: Application
    Filed: March 16, 2009
    Publication date: August 13, 2009
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventor: Jun-ichi HASHIMOTO
  • Patent number: 7573060
    Abstract: An active layer having a p-type quantum dot structure is disposed over a lower cladding layer made of semiconductor material of a first conductivity type. An upper cladding layer is disposed over the active layer. The upper cladding layer is made of semiconductor material, and includes a ridge portion and a cover portion. The ridge portion extends in one direction, and the cover portion covers the surface on both sides of the ridge portion. A capacitance reducing region is disposed on both sides of the ridge portion and reaching at least the lower surface of the cover portion. The capacitance reducing region has the first conductivity type or a higher resistivity than that of the ridge portion, and the ridge portion has a second conductivity type. If the lower cladding layer is an n-type, the capacitance reducing region reaches at least the upper surface of the lower cladding layer.
    Type: Grant
    Filed: October 22, 2007
    Date of Patent: August 11, 2009
    Assignees: Fujitsu Limited, The University of Tokyo
    Inventors: Nobuaki Hatori, Tsuyoshi Yamamoto, Hisao Sudo, Yasuhiko Arakawa
  • Publication number: 20090197363
    Abstract: A method for manufacturing a semiconductor optical device comprises forming a groove on a first semiconductor layer; forming a second semiconductor layer containing aluminum in the groove; forming a third semiconductor layer on the first semiconductor layer and the second semiconductor layer; forming an insulating layer on the third semiconductor layer covering the region opposite the second semiconductor layer; forming a stripe-shaped structure by etching the first semiconductor layer and the third semiconductor layer without exposing the second semiconductor layers using the insulating layer as a mask; and burying the stripe-shaped structure with burying layers.
    Type: Application
    Filed: May 1, 2008
    Publication date: August 6, 2009
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Go Sakaino
  • Publication number: 20090196318
    Abstract: A method of manufacturing a vertical cavity surface emitting laser of a mesa structure, the method comprises: sequentially laminating on a substrate a plurality of semiconductor layers including a bottom reflecting mirror, an active layer, a selective oxidation layer and a top reflecting mirror, followed by forming a dielectric film on the laminated semiconductor layers; forming on the dielectric film a first resist pattern comprised of large and small annular opening patterns and large and small annular resist patterns around the same central axis; forming the large and small annular opening patterns in the dielectric film; forming a second resist pattern in the dielectric film so that only the small annular opening pattern is exposed, followed by forming an annular electrode in the exposed small annular opening pattern; and forming a third resist pattern over the annular electrode.
    Type: Application
    Filed: February 3, 2009
    Publication date: August 6, 2009
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: Tatsuro Uchida
  • Patent number: 7569461
    Abstract: In a method for fabricating a nitride-based compound layer, first, a GaN substrate is prepared. A mask layer with a predetermined pattern is formed on the GaN substrate to expose a partial area of the GaN substrate. Then a buffer layer is formed on the partially exposed GaN substrate. The buffer layer is made of a material having a 10% or less lattice mismatch with GaN. Thereafter, the nitride-based compound is grown laterally from a top surface of the buffer layer toward a top surface of the mask layer and the nitride-based compound layer is vertically grown to a predetermined thickness. Also, the mask layer and the buffer layer are removed via wet-etching to separate the nitride-based compound layer from the GaN substrate.
    Type: Grant
    Filed: June 21, 2006
    Date of Patent: August 4, 2009
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Soo Min Lee, Cheol Kyu Kim, Jaeun Yoo, Sung Hwan Jang, Masayoshi Koike
  • Patent number: 7566578
    Abstract: A GaN based III-V nitride semiconductor light-emitting device and a method for fabricating the same are provided. In the GaN based III-V nitride semiconductor light-emitting device including first and second electrodes arranged facing opposite directions or the same direction with a high-resistant substrate therebetween and material layers for light emission or lasing, the second electrode directly contacts a region of the outmost material layer exposed through an etched region of the high-resistant substrate. A thermal conductive layer may be formed on the bottom of the high-resistant substrate to cover the exposed region of the outmost material layer.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: July 28, 2009
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Joon-seop Kwak, Kyo-yeol Lee, Jae-hee Cho, Su-hee Chae
  • Publication number: 20090179210
    Abstract: A method of patterning a substrate that includes locating a single mask film over the substrate and forming first opening portions in first locations in the mask film. First electrical materials are deposited over the substrate and mask film to form patterned areas in the first locations. Second opening portions are formed in second locations different from the first locations in the mask film. Subsequently, second electrical materials are deposited over the substrate and mask film to form patterned areas in the first and second locations.
    Type: Application
    Filed: January 10, 2008
    Publication date: July 16, 2009
    Inventor: Ronald S. Cok
  • Publication number: 20090168825
    Abstract: A light-emitting element assembly includes a support substrate having a first surface, a second surface facing the first surface, a recessed portion, and a conductive material layer formed over the first surface and the inner surface of the recessed portion, and a light-emitting element. The light-emitting element has a laminated structure including a first compound semiconductor layer, a light-emitting portion, and a second compound semiconductor layer, at least the second compound semiconductor layer and the light-emitting portion constituting a mesa structure. The light-emitting element further includes an insulating layer formed, a second electrode, and a first electrode. The mesa structure is placed in the recessed portion so that the conductive material layer and the second electrode are in at least partial contact with each other, and light emitted from the light-emitting portion is emitted from the second surface side of the first compound semiconductor layer.
    Type: Application
    Filed: December 12, 2008
    Publication date: July 2, 2009
    Applicant: Sony Corporation
    Inventors: Rintaro Koda, Takahiro Arakida, Satoshi Taniguchi, Yuji Masui, Nobuhiro Suzuki, Tomoyuki Oki, Chiyomi Uchiyama, Kayoko Kikuchi
  • Publication number: 20090147814
    Abstract: A ridge stripe type semiconductor laser device is provided, on a semiconductor substrate (102), with a first conduction type cladding layer (103), an active layer (104), a second conduction type first cladding layer (105), a second conduction type second cladding layer (108) of a ridge type stripe shape for confining direction, and a current block layer (107) formed by removing at least an upper portion of the ridge. In a section normal to the stripe direction of the ridge, each of the two side faces of the ridge is provided with a first face (118) substantially normal to the semiconductor substrate surface and extending downward from the upper end of the ridge, and a second face (119) formed to have a substantially straight skirt slope face inclined at the ridge skirt portion obliquely downward to the ridge outside. The first face and the second face are made to merge either directly or through a third intermediate face into each other.
    Type: Application
    Filed: January 12, 2006
    Publication date: June 11, 2009
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Hiroyuki HOSOI, Kouji MAKITA, Michinari YAMANAKA
  • Publication number: 20090141764
    Abstract: In the method of making a semiconductor laser, a semiconductor region is grown on an active layer, and a part of the semiconductor region is etched to form a ridge structure. An insulating film is formed over the ridge structure, and a resin layer of photosensitive material is formed to bury the ridge structure. A cured resin portion and an uncured resin portion are formed in the resin layer by performing lithographic exposure of the resin layer, and the uncured resin portion is on the top of the ridge structure. The uncured resin portion is removed to form a dent which is provided on the top of the ridge structure. An overall surface of the cured resin portion and dent is etched to form an etched resin layer. An opening is formed in the etched resin layer by thinning the cured resin portion, and a part of the insulating film is exposed in the opening of the etched resin layer. The part of the insulating film is etched using the etched resin layer as a mask to form an opening in the insulating film.
    Type: Application
    Filed: October 31, 2008
    Publication date: June 4, 2009
    Inventors: Hideki Yagi, Toshio Nomaguchi, Kenji Hiratsuka
  • Patent number: 7541206
    Abstract: A nitride-based semiconductor light-emitting device having an improved structure to enhance light extraction efficiency, and a method of manufacturing the same are provided. The method includes the operations of sequentially forming an n-clad layer, an active layer, and a p-clad layer on a substrate; forming a plurality of masking dots on an upper surface of the p-clad layer; forming a p-contact layer having a rough surface on portions of the p-clad layer between the masking dots; forming a rough n-contact surface of the n-clad layer having the same rough shape as the rough shape of the p-contact layer by dry-etching from a portion of the upper surface of the p-contact layer to a desired depth of the n-clad layer; forming an n-electrode on the rough n-contact surface; and forming a p-electrode on the p-contact layer.
    Type: Grant
    Filed: January 4, 2007
    Date of Patent: June 2, 2009
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Suk-ho Yoon, Cheol-soo Sone, Jeong-wook Lee, Joo-sung Kim
  • Patent number: 7537945
    Abstract: Provided are a semiconductor laser device capable of stable operation at the time of high power output without damage to a resonator end surface and a method of manufacturing the same, as well as an optical transmission module and an optical disk apparatus using the semiconductor laser device. A method of manufacturing a semiconductor laser device includes a laser wafer formation step of forming a laser wafer at least having a semiconductor layer to form a resonator end surface, a cleavage step of cleaving the laser wafer in the atmosphere and forming a semiconductor laser element having the resonator end surface, a contact step of brining the resonator end surface in contact with a nitrogen containing gas containing 90-100 volume % nitrogen for one hour or longer, and a reflectance control film formation step of forming a reflectance control film in contact with the resonator end surface.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: May 26, 2009
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Shuichi Hirukawa, Katsuhiko Kishimoto
  • Publication number: 20090130790
    Abstract: A method for manufacturing a nitride semiconductor light-emitting element comprises: forming a semiconductor laminated structure wherein an n-type nitride semiconductor epitaxial layer, an active layer, and a p-type nitride semiconductor epitaxial layer are laminated on a substrate; forming a p-type electrode having a first electrode layer containing Pd and a second electrode layer containing Ta on the p-type nitride semiconductor epitaxial layer; heat treating at a temperature between 400° C. and 600° C. in an ambient containing oxygen after forming the p-type electrode; and forming a pad electrode containing Au on the p-type electrode after the heat treating.
    Type: Application
    Filed: November 5, 2008
    Publication date: May 21, 2009
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Kyozo Kanamoto, Katsuomi Shiozawa, Kazushige Kawasaki, Shinji Abe, Hitoshi Sakuma
  • Publication number: 20090129419
    Abstract: Provided is a VCSEL array device that includes at least a first multilayer reflective film, an active layer, and a second multilayer reflective film, formed on a substrate that extends in a longitudinal direction. Plural mesa portions are formed on the substrate by selectively removing at least a portion of the first multilayer reflective film, active layer, and second multilayer reflective film. A selectively oxidized region is formed in at least one of the first multilayer reflective film and the second multilayer reflective film. The VCSEL array device further includes an interlayer insulating film that covers at least a side portion and a bottom portion of the mesa portions, and a surface protecting film that covers the interlayer insulating film. The surface protecting film has plural grooves formed along a longitudinal direction of the substrate in which at least a portion of the surface protecting film is removed.
    Type: Application
    Filed: August 11, 2008
    Publication date: May 21, 2009
    Applicant: FUJI XEROX CO., LTD.
    Inventors: Kazuyuki Matsushita, Nobuaki Ueki
  • Patent number: 7529448
    Abstract: The present invention provides a system, method and apparatus for improved electrical-to-optical transmitters (100) disposed within printed circuit boards (104). The heat sink (110, 200) is a thermal conductive material disposed within a cavity (102) of the printed circuit board (104) and is thermally coupled to a bottom surface (112) of the electrical-to-optical transmitter (100). A portion of the thermal conductive material extends approximately to an outer surface (120, 122 or 124) of a layer (114, 116 or 118) of the printed circuit board (104). The printed circuit board may comprise a planarized signal communications system or an optoelectronic signal communications system. In addition, the present invention provides a method for fabricating the heat sink wherein the electrical-to-optical transmitter disposed within a cavity of the printed circuit board is fabricated. New methods for flexible waveguides and micro-mirror couplers are also provided.
    Type: Grant
    Filed: September 21, 2006
    Date of Patent: May 5, 2009
    Assignee: Board of Regents, The University of Texas System
    Inventors: Ray T. Chen, Chulchae Choi
  • Patent number: 7524687
    Abstract: A method for producing an integrated semiconductor component comprising a first semiconductor layer construction for emitting radiation and a second semiconductor layer construction for receiving radiation, wherein a substrate is first provided and a first semiconductor layer sequence containing a radiation-generating region is deposited epitaxially on the substrate. A second semiconductor layer sequence containing a radiation-absorbing region is subsequently deposited epitaxially on the first semiconductor layer sequence. The second semiconductor layer sequence is then patterned in order to uncover a first location and a second location. A first semiconductor layer construction is electrically insulated from a second semiconductor layer construction. Finally, a first contact layer is applied to a free surface of the substrate and a second contact layer is applied at least to the first and second locations for contact-connection.
    Type: Grant
    Filed: February 26, 2008
    Date of Patent: April 28, 2009
    Assignee: Osram Opto Semiconductors GmbH
    Inventors: Glenn-Yves Plaine, Tony Albrecht, Peter Brick, Marc Philippens
  • Publication number: 20090103583
    Abstract: On an n-type GaN buffer layer serving as a common semiconductor layer, mesa regions are formed. The mesa region is formed of a semiconductor stack formed of an n-type GaN layer, an active layer and a p-type GaN layer. A current blocking region is not formed in the mesa region, and the mesa diameter of the mesa region is formed to be not more than 15 ?m. The mesa region is formed by selective growth. The mesa region without a surface damage allows sufficient constriction of current and an induced radiation of laser with low current.
    Type: Application
    Filed: August 28, 2008
    Publication date: April 23, 2009
    Applicant: ROHM CO., LTD.
    Inventors: Yoshinori Tanaka, Jun Ichihara
  • Patent number: 7521721
    Abstract: A surface-emitting type device includes a substrate including a first face and a second face that is tilted with respect to the first face and has a plane index different from a plane index of the first face, an emission section formed above the first face, and a rectification section formed above the second face, wherein the emission section includes a first semiconductor layer of a first conductivity type, an active layer formed above the first semiconductor layer, and a second semiconductor layer of a second conductivity type formed above the active layer, the rectification section includes a first semiconductor layer of the second conductivity type, and a second semiconductor layer of the first conductivity type formed above the first semiconductor layer, the first semiconductor layer of the emission section and the first semiconductor layer of the rectification section are formed by a common process and include the same impurity, the emission section and the rectification section are electrically connect
    Type: Grant
    Filed: February 1, 2006
    Date of Patent: April 21, 2009
    Assignee: Seiko Epson Corporation
    Inventors: Hajime Onishi, Tetsuo Nishida
  • Publication number: 20090097521
    Abstract: A side surface light emitting semiconductor element includes: an AlGaN layer doped with Mg at a concentration equal to or less than 5×1019 cm?3; a ridge having a striped shape and formed in an upper portion of a laminated structure which includes the AlGaN layer and an active layer; and a Schottky barrier formed on a top surface of the laminated structure in an area where the ridge is not formed and the AlGaN layer is exposed.
    Type: Application
    Filed: March 15, 2007
    Publication date: April 16, 2009
    Applicant: ROHM CO., LTD.
    Inventor: Ken Nakahara
  • Publication number: 20090098675
    Abstract: A method of manufacturing a semiconductor light-emitting device includes steps of forming a vertical cavity structure including a layer to be oxidized on a semiconductor substrate, and then forming a circular groove having a depth which penetrates at least the layer to be oxidized from an upper surface of the vertical cavity structure, thereby forming a columnar mesa whose side face is surrounded by the groove, oxidizing the layer to be oxidized from the side face of the mesa, thereby forming a current confinement layer, and forming a mask layer covering at least a central region of the upper surface of the mesa and exposing at least an edge of the upper surface and the side face of the mesa to an external, and then etching at least the edge of the upper surface and the side face of the mesa by using the mask layer as a mask.
    Type: Application
    Filed: October 1, 2008
    Publication date: April 16, 2009
    Applicant: Sony Corporation
    Inventors: Yuji Masui, Takahiro Arakida, Yoshinori Yamauchi, Rintaro Koda, Tomoyuki Oki
  • Publication number: 20090097518
    Abstract: A vertical cavity surface emitting laser diode (VCSEL) with a new structure is disclosed. The VCSEL of the invention provides the active layer, the first spacer layer, the tunnel junction, the second spacer layer burying the tunnel junction. Only the first spacer layer is ion-implanted to form a high-resistive region around the tunnel junction. The current injected into the second spacer layer is confined by the tunnel junction to reach the active layer, which reduces the increase of the parasitic resistance of the device. The high-resistive region around the tunnel junction reduces the parasitic capacitance of the device.
    Type: Application
    Filed: September 22, 2008
    Publication date: April 16, 2009
    Inventor: Yutaka Onishi
  • Publication number: 20090092164
    Abstract: The reliability of a buried hetero-structure semiconductor laser is improved by preventing an increase in oscillation threshold current and a decrease in external differential quantum efficiency in cases where the semiconductor laser is energized continuously under conditions of high temperature and high optical output. An optical semiconductor laser has an optical waveguide structure comprising an n-type cladding layer, an active layer and p-type cladding layers, and a current narrowing/blocking structure comprising a p-type blocking layer and an n-type blocking layer, wherein concentration of hydrogen contained in the p-type cladding layers is higher than concentration of hydrogen contained in the p-type blocking layer.
    Type: Application
    Filed: October 6, 2008
    Publication date: April 9, 2009
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Yasutaka SAKATA
  • Publication number: 20090086779
    Abstract: The LD of the invention provides a semiconductor stack including the current confinement region with the active mesa and the semi-insulating burying regions putting the active mesa therebeteen and the conductive region in contiguity with the current confinement region. The current confinement region and the conductive region are provided on epitaxially grown cladding layer. Two semiconductor regions, which are physically isolated to each other and each includes the semiconductor substrate, are provided on the semiconductor stack. One of regions comes in contact with one of burying regions and the active mesa, while, the other semiconductor regions comes in contact with the other of burying regions and the conductive region.
    Type: Application
    Filed: September 25, 2008
    Publication date: April 2, 2009
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Atsushi Matsumura