Mesa Formation Patents (Class 438/39)
  • Patent number: 7871841
    Abstract: A method of manufacturing a semiconductor light-emitting device includes steps of forming a vertical cavity structure including a layer to be oxidized on a semiconductor substrate, and then forming a circular groove having a depth which penetrates at least the layer to be oxidized from an upper surface of the vertical cavity structure, thereby forming a columnar mesa whose side face is surrounded by the groove, oxidizing the layer to be oxidized from the side face of the mesa, thereby forming a current confinement layer, and forming a mask layer covering at least a central region of the upper surface of the mesa and exposing at least an edge of the upper surface and the side face of the mesa to an external, and then etching at least the edge of the upper surface and the side face of the mesa by using the mask layer as a mask.
    Type: Grant
    Filed: October 1, 2008
    Date of Patent: January 18, 2011
    Assignee: Sony Corporation
    Inventors: Yuji Masui, Takahiro Arakida, Yoshinori Yamauchi, Rintaro Koda, Tomoyuki Oki
  • Patent number: 7871840
    Abstract: The present invention provides a semiconductor laser diode prevents not only the adhesion of the upper electrode but the heat dissipation of the mesa from degrading. The laser diode includes a substrate, portion of which forms a mesa including an active layer, an insulating layer formed so as to bury the mesa, and an electrode formed on the mesa and the insulating layer. This insulating layer may be selected from SiO2, SiON, SiN, Al2O3 or ZrO2 and formed by the inductive coupling plasma-enhanced chemical vapor deposition (ICP-CVD) technique.
    Type: Grant
    Filed: July 18, 2006
    Date of Patent: January 18, 2011
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Toshio Nomaguchi, Tetsuya Hattori
  • Publication number: 20100327312
    Abstract: A group III nitride semiconductor light-emitting device includes: a conductive support; a p-electrode positioned on the support, a p-type layer containing a group III nitride semiconductor, an active layer and an n-type layer having a first surface, which are positioned in turn on the p-electrode; and an n-electrode positioned on the first surface of the n-type layer. A groove is formed in the first surface of the n-type layer in a pattern such that the first surface of the n-type layer is continuous. A light-transmitting insulating film is formed on side surface and bottom surface of the groove. The groove has a depth at least reaching the p-type layer. The n-electrode is formed in wiring form.
    Type: Application
    Filed: June 9, 2010
    Publication date: December 30, 2010
    Applicant: TOYODA GOSEI CO., LTD.
    Inventors: Toshiya Uemura, Naoki Arazoe
  • Publication number: 20100328753
    Abstract: An integrated semiconductor optical device and an optical module capable of the high-speed and large-capacity optical transmission are provided. In an integrated semiconductor optical device in which a plurality of optical devices buried with semi-insulating semiconductor materials are integrated on the same semiconductor substrate and an optical module using the integrated semiconductor optical device, configurations (material and electrical characteristics) of the buried layers are made different for each of the optical devices.
    Type: Application
    Filed: June 24, 2010
    Publication date: December 30, 2010
    Inventors: Hiroaki Hayashi, Shigeki Makino, Takeshi Kitatani, Shigehisa Tanaka
  • Patent number: 7858418
    Abstract: Herein disclosed a method of manufacturing a light emitting device, including the steps of: (A) sequentially forming a first compound semiconductor layer of a first conduction type, an active layer, and a second compound semiconductor layer of a second conduction type different from said first conduction type, over a substrate; and (B) exposing a part of said first compound semiconductor layer, forming a first electrode over said exposed part of said first compound semiconductor layer and forming a second electrode over said second compound semiconductor layer, wherein said method further includes, subsequent to said step (B), the step of: (C) covering at least said exposed part of said first compound semiconductor layer, an exposed part of said active layer, an exposed part of said second compound semiconductor layer, and a part of said second electrode with an SOG layer.
    Type: Grant
    Filed: October 17, 2007
    Date of Patent: December 28, 2010
    Assignee: Sony Corporation
    Inventors: Yoshiaki Watanabe, Tomonori Hino, Nobukata Okano, Hisayoshi Kuramochi, Yuichiro Kikuchi, Tatsuo Ohashi
  • Publication number: 20100316078
    Abstract: A surface plasmon-generating apparatus includes an active layer including an n-type region formed on one side and a p-type region formed on the other side, the n-type region and the p-type region being in contact with each other to form a pn junction therebetween; a first barrier layer in contact with a first surface of the active layer; a second barrier layer in contact with a second surface of the active layer, the second surface being opposite the first surface; and a metal body disposed above the pn junction of the active layer with the second barrier layer and an insulating layer therebetween.
    Type: Application
    Filed: May 21, 2010
    Publication date: December 16, 2010
    Applicant: SONY CORPORATION
    Inventor: Tomoki Ono
  • Publication number: 20100316075
    Abstract: An optical device includes a gallium nitride substrate member having an m-plane nonpolar crystalline surface region characterized by an orientation of about ?2 degrees to about 2 degrees towards (000-1) and less than about 0.5 degrees towards (11-20). The device also has a laser stripe region formed overlying a portion of the m-plane nonpolar crystalline orientation surface region. A first cleaved c-face facet is provided on one end of the laser stripe region, and a second cleaved c-face facet is provided on the other end of the laser stripe region.
    Type: Application
    Filed: April 13, 2010
    Publication date: December 16, 2010
    Applicant: Kaai, Inc.
    Inventors: James W. Raring, Daniel F. Feezell, Nicholas J. Pfister, Rajat Sharma
  • Patent number: 7846820
    Abstract: A process for producing a nitride semiconductor according to the present invention includes: step (A) of provided an n-GaN substrate 101; step (B) of forming on the substrate 101 a plurality of stripe ridges having upper faces which are parallel to a principal face of the substrate 101; step (C) of selectively growing AlxGayInzN crystals (0?x, y, z?1: x+y+z=1) 104 on the upper faces of the plurality of stripe ridges, the AlxGayInzN crystals containing an n-type impurity at a first concentration; and step (D) of growing an Alx?Gay?Inz?N crystal (0?x?, y?, z??1:x?+y?+z?=1) 106 on the AlxGayInzN crystals 104, the Alx?Gay?Inz?N crystal 106 containing an n-type impurity at a second concentration which is lower than the first concentration, and linking every two adjoining AlxGayInzN crystals 104 with the Alx?Gay?Inz?N crystal 106 to form one nitride semiconductor layer 120.
    Type: Grant
    Filed: April 20, 2005
    Date of Patent: December 7, 2010
    Assignee: Panasonic Corporation
    Inventors: Akihiko Ishibashi, Toshiya Yokogawa, Toshitaka Shimamoto, Yoshiaki Hasegawa, Yasutoshi Kawaguchi, Isao Kidoguchi
  • Patent number: 7846756
    Abstract: A method of making a device is disclosed including: forming a first hard mask layer over an underlying layer; forming a first imprint resist layer over the underlying layer; forming first features over the first hard mask layer by bringing a first imprint template in contact with the first imprint resist layer; forming a first spacer layer over the first features; etching the first spacer layer to form a first spacer pattern and to expose top of the first features; removing the first features; patterning the first hard mask, using the first spacer pattern as a mask, to form first hard mask features; and etching at least part of the underlying layer using the first hard mask features as a mask.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: December 7, 2010
    Assignee: SanDisk 3D LLC
    Inventors: Bing K. Yen, Chun-Ming Wang, Yung-Tin Chen, Steven Maxwell
  • Patent number: 7842530
    Abstract: A method of manufacturing a vertical cavity surface emitting laser of a mesa structure, the method comprises: sequentially laminating on a substrate a plurality of semiconductor layers including a bottom reflecting mirror, an active layer, a selective oxidation layer and a top reflecting mirror, followed by forming a dielectric film on the laminated semiconductor layers; forming on the dielectric film a first resist pattern comprised of large and small annular opening patterns and large and small annular resist patterns around the same central axis; forming the large and small annular opening patterns in the dielectric film; forming a second resist pattern in the dielectric film so that only the small annular opening pattern is exposed, followed by forming an annular electrode in the exposed small annular opening pattern; and forming a third resist pattern over the annular electrode.
    Type: Grant
    Filed: February 3, 2009
    Date of Patent: November 30, 2010
    Assignee: Canon Kabushiki Kaisha
    Inventor: Tatsuro Uchida
  • Patent number: 7838377
    Abstract: A bipolar junction transistor includes a collector having a first conductivity type, a drift layer having the first conductivity type on the collector, a base layer on the drift layer and having a second conductivity type opposite the first conductivity type, a lightly doped buffer layer having the first conductivity type on the base layer and forming a p-n junction with the base layer, and an emitter mesa having the first conductivity type on the buffer layer and having a sidewall. The buffer layer includes a mesa step adjacent to and spaced laterally apart from the sidewall of the emitter mesa, and a first thickness of the buffer layer beneath the emitter mesa is greater than a second thickness of the buffer layer outside the mesa step.
    Type: Grant
    Filed: September 9, 2008
    Date of Patent: November 23, 2010
    Assignee: Cree, Inc.
    Inventors: Qingchun Zhang, Anant K. Agarwal
  • Publication number: 20100285625
    Abstract: A method for making a light-emitting element assembly including a support substrate having a first surface, a second surface facing the first surface, a recessed portion, and a conductive material layer formed over the first surface and the inner surface of the recessed portion, and a light-emitting element. The light-emitting element has a laminated structure including a first compound semiconductor layer, a light-emitting portion, and a second compound semiconductor layer, at least the second compound semiconductor layer and the light-emitting portion constituting a mesa structure. The light-emitting element further includes an insulating layer formed, a second electrode, and a first electrode. The mesa structure is placed in the recessed portion so that the conductive material layer and the second electrode are in at least partial contact with each other, and light emitted from the light-emitting portion is emitted from the second surface side of the first compound semiconductor layer.
    Type: Application
    Filed: July 22, 2010
    Publication date: November 11, 2010
    Applicant: SONY CORPORATION
    Inventors: Rintaro Koda, Takahiro Arakida, Satoshi Taniguchi, Yuji Masui, Nobuhiro Suzuki, Tomoyuki Oki, Chiyomi Uchiyama, Kayoko Kikuchi
  • Publication number: 20100284432
    Abstract: A surface emitting laser array having a plurality of surface emitting lasers arranged in an array, each of the surface emitting lasers being provided with a two-dimensional photonic crystal having a resonance mode in an in-plane direction and with an active layer. The surface emitting laser has a mesa-shaped inclined side wall surface. When a maximum light-receiving angle with respect to the mesa-shaped inclined side wall surface at which an incident light is coupled with a waveguide containing the two-dimensional photonic crystal is denoted as ?max°, an angle formed by a plane of the two-dimensional photonic crystal and the mesa-shaped inclined side wall surface is controlled so as to exceed (90+?max)° or be smaller than (90??max)°.
    Type: Application
    Filed: May 4, 2010
    Publication date: November 11, 2010
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Katsuyuki Hoshino, Shoichi Kawashima
  • Patent number: 7816162
    Abstract: After a p-type cladding layer, an etching rate reducing layer and a p-type contact layer are formed in order on an n-type substrate, an etching mask is formed. Then, by using the etching mask, the p-type contact layer, the etching rate reducing layer and the p-type cladding layer are partially etched in the region outside the etching mask with an etchant. At this time, the etching rate of the layers by the etchant is slower in the etching rate reducing layer than in the p-type cladding layer and the p-type contact layer. Then, a metal thin film is formed such that the film continuously coats an upper surface and side surfaces of a ridge consisting of the above layers left after the etching step. A normal vector at a surface coated with the thin film has an upward component.
    Type: Grant
    Filed: July 9, 2009
    Date of Patent: October 19, 2010
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Shuichi Hirukawa, Katsuhiko Kishimoto
  • Patent number: 7807490
    Abstract: Provided is a manufacturing method of a nitride semiconductor device having a nitride semiconductor substrate (e.g. GaN substrate) in which dislocation concentrated regions align in stripe formation, the dislocation concentrated regions extending from a front surface to a back surface of the substrate, the manufacturing method being for stacking each of a plurality of nitride semiconductor layers on the front surface of the substrate in a constant film thickness. Grooves are formed on the nitride semiconductor substrate in the immediate areas of dislocation concentrated regions. Each of the nitride semiconductor layers is formed as a crystal growth layer on the main surface of the nitride semiconductor substrate to which the grooves have been formed.
    Type: Grant
    Filed: July 14, 2008
    Date of Patent: October 5, 2010
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Takashi Kano, Tsutomu Yamaguchi, Hiroaki Izu, Masayuki Hata, Yasuhiko Nomura
  • Patent number: 7807489
    Abstract: A light-emitting device with a protection layer for Zn inter-diffusion and a process to form the device are described. The device of the invention provides an active layer containing aluminum (Al) as a group III element, typically AlGaInAs, and protection layers containing silicon (Si) to prevent the inter-diffusion of zing (Zn) atoms contained in p-type layers surrounding the active layer. One of protection layers is put between the active layer and the p-type cladding layer, while, the other of protection layers is disposed between the active layer and the p-type burying layer.
    Type: Grant
    Filed: June 18, 2008
    Date of Patent: October 5, 2010
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Mitsuo Takahashi, Kenji Hiratsuka, Akiko Kumagai
  • Publication number: 20100248406
    Abstract: A method is for manufacturing a nitride semiconductor laser element including a substrate, a nitride semiconductor layer that is laminated on the substrate and that has a ridge on its surface, an insulating protective film, and an electrode that is electrically connected with the nitride semiconductor layer. The method includes forming the ridge; forming a monocrystalline first film from the side faces of the ridge to the nitride semiconductor layer on both sides of the ridge; and forming a second film containing polycrystalline or an amorphous substance over the first film thereby forming the insulating protective film.
    Type: Application
    Filed: June 11, 2010
    Publication date: September 30, 2010
    Applicant: NICHIA CORPORATION
    Inventors: Shingo MASUI, Tomonori MORIZUMI
  • Publication number: 20100237382
    Abstract: The present invention provides a semiconductor light emitting element capable of improving light extraction efficiency and a semiconductor light emitting device using the semiconductor light emitting element without adding any manufacturing step A semiconductor light emitting element 1 includes a compound semiconductor layer 3 stacked on a single crystal substrate, and is formed by separating the single crystal substrate into individual rectangular pieces. An individual piece 2, which is the separated single crystal substrate, is oriented at a predetermined angle with respect to a cleavage plane of a crystal structure of the single crystal substrate so that long side surfaces 21 and 23 are different from the cleavage planes.
    Type: Application
    Filed: September 17, 2008
    Publication date: September 23, 2010
    Inventor: Hidenori Kamei
  • Patent number: 7791061
    Abstract: A light emitting diode is disclosed that includes a support structure and a Group III nitride light emitting active structure mesa on the support structure. The mesa has its sidewalls along an indexed crystal plane of the Group III nitride. A method of forming the diode is also disclosed that includes the steps of removing a substrate from a Group III nitride light emitting structure that includes a sub-mount structure on the Group III nitride light emitting structure opposite the substrate, and thereafter etching the surface of the Group III nitride from which the substrate has been removed with an anisotropic etch to develop crystal facets on the surface in which the facets are along an index plane of the Group III nitride. The method can also include etching the light emitting structure with an anisotropic etch to form a mesa with edges along an index plane of the Group III nitride.
    Type: Grant
    Filed: January 30, 2006
    Date of Patent: September 7, 2010
    Assignee: Cree, Inc.
    Inventors: John A. Edmond, David B. Slater, Jr., Hua Shuang Kong, Matthew Donofrio
  • Patent number: 7786020
    Abstract: A method for fabricating a nonvolatile memory device includes repeatedly stacking a stacked structure over a substrate to form a multi-stacked structure, wherein the stacked structure includes a conductive layer and an insulation layer, forming a photoresist pattern over the multi-stacked structure, first-etching an uppermost stacked structure of the multi-stacked structure using the photoresist pattern as an etch barrier, second-etching a resultant structure formed by the first-etching through the use of a breakthrough etching, slimming the photoresist pattern to form a slimmed photoresist pattern, and third-etching the uppermost stacked structure using the slimmed photoresist pattern as an etch barrier and, at the same time, etching a stacked structure disposed under the uppermost stacked structure and exposed by the first-etching.
    Type: Grant
    Filed: December 24, 2009
    Date of Patent: August 31, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Hye-Ran Kang, Sung-Yoon Cho
  • Patent number: 7785911
    Abstract: Provided are a semiconductor laser diode having a current confining layer and a method of fabricating the same. The semiconductor laser diode includes a substrate, a first material layer deposited on the substrate, an active layer which is deposited on the first material layer and emits a laser beam, and a second material layer which is deposited on the active layer and includes a ridge portion protruding from the active layer and a current confining layer formed by injection of ions into peripheral portions of the ridge portion so as to confine a current injected into the active layer. Therefore, it is possible to fabricate an improved semiconductor laser diode having a low-resonance critical current value that can remove a loss in an optical profile and reduce the profile width of a current injected into the active layer while maintaining the width of the ridge portion.
    Type: Grant
    Filed: October 13, 2006
    Date of Patent: August 31, 2010
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Joon-seop Kwak, Kyoung-ho Ha, Yoon-joon Sung
  • Publication number: 20100216268
    Abstract: A method of manufacturing a semiconductor element of good characteristics at a reduced manufacturing cost is provided. The manufacturing method of the semiconductor element includes a GaN-containing semiconductor layer forming step, an electrode layer forming step, a step of forming an Al film on the GaN-containing semiconductor layer, a step of forming a mask layer made of a material of which etching rate is smaller than that of a material of the Al film, a step of forming a ridge portion using the mask layer as a mask, a step of retreating a position of a side wall of the Al film with respect to a position of a side wall of the mask layer, a step of forming, on the side surface of the ridge portion and the top surface of the mask layer, a protective film made of a material of which etching rate is smaller than that of the material forming the Al film, and a step of removing the Al film and thereby removing the mask layer and a portion of the protective film formed on the top surface of the mask layer.
    Type: Application
    Filed: August 11, 2009
    Publication date: August 26, 2010
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Koji Katayama, Hiroyuki Kitabayashi, Satoshi Arakawa
  • Patent number: 7781796
    Abstract: A nitride semiconductor laser element includes a substrate and a nitride semiconductor layer in which a first semiconductor layer, an active layer, and a second semiconductor layer are laminated in this order on the substrate. At least one of the first semiconductor layer and the second semiconductor layer includes a first section forming recessed and raised portions and a second section embedding the recessed and raised portions of the first section. A region with a higher aluminum mixed crystal ratio than the second section that embeds the recessed and raised portions is disposed on top faces of the raised portions. The nitride semiconductor layer defines resonant planes, and the recessed and raised portions are formed in a shape of stripes that extend substantially parallel to the resonant planes.
    Type: Grant
    Filed: June 14, 2007
    Date of Patent: August 24, 2010
    Assignee: Nichia Corporation
    Inventors: Shingo Masui, Kazutaka Tsukayama
  • Patent number: 7781269
    Abstract: A method of making a semiconductor device includes forming at least one device layer over a substrate, forming a plurality of spaced apart first features over the device layer, where each three adjacent first features form an equilateral triangle, forming sidewall spacers on the first features, filling a space between the sidewall spacers with a plurality of filler features, selectively removing the sidewall spacers, and etching the at least one device layer using at least the plurality of filler features as a mask. A device contains a plurality of bottom electrodes located over a substrate, a plurality of spaced apart pillars over the plurality of bottom electrodes, and a plurality of upper electrodes contacting the plurality of pillars. Each three adjacent pillars form an equilateral triangle, and each pillar comprises a semiconductor device.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: August 24, 2010
    Assignee: Sandisk 3D LLC
    Inventors: Chun-Ming Wang, Yung-Tin Chen, Roy E. Scheuerlein
  • Patent number: 7781275
    Abstract: A method of manufacturing a flash memory device is disclosed. The method includes the steps of providing a semiconductor substrate in which a cell region and a select transistor region are defined, etching the semiconductor substrate in the select transistor region so that there is a first step between the cell region and the select transistor region, forming a cell gate in the cell region, and forming a transistor in the select transistor region.
    Type: Grant
    Filed: June 5, 2007
    Date of Patent: August 24, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventor: Young Ho Yang
  • Patent number: 7772023
    Abstract: Si atoms obtained by thermal decomposition of SiH4 are adsorbed in advance on one surface of a semiconductor substrate and side surfaces of a semiconductor mesa part. Thereby, prior to the growth of a buried layer, a diffusion protection layer composed of Si-doped InP with high impurity concentration is formed. As a result, when the buried layer is grown, Zn diffusing from an upper cladding layer is trapped by the diffusion protection layer, and interdiffusion between Zn and Fe is inhibited. Since the diffusion protection layer is formed uniformly at a small thickness of several monolayers, the diffusion protection layer is also inhibited from becoming a current leakage path. Consequently, the reliability of the semiconductor optical device can be improved.
    Type: Grant
    Filed: November 20, 2008
    Date of Patent: August 10, 2010
    Assignee: Sumitomo Electric Industries Ltd.
    Inventor: Kenji Hiratsuka
  • Patent number: 7772020
    Abstract: A vertical topology device includes a conductive adhesion structure having a first surface and a second surface, a conductive thick film support formed on the first surface, and a semiconductive device having an upper electrical contact and located over the conductive adhesion layer. Electrical current can flow between the conductive thick film and the upper electrical contact.
    Type: Grant
    Filed: August 2, 2007
    Date of Patent: August 10, 2010
    Assignee: LG Electronics Inc.
    Inventor: Myung Cheol Yoo
  • Publication number: 20100190283
    Abstract: A method to form a an LD with the buried mesa type is disclosed, in which the n-type current blocking layer is stably kept with a distance to the active layer in the buried mesa. The method of the invention includes a step to form the mesa by iterating the RIE and the ashing to obtain in a mesa side a steep edge with the (110) surface. A wet-etching process subsequent to the iterative etching and ashing removes residuals left on the mesa side. Then, the growth of the current blocking layer shows two modes of the horizontal growth of the (110) surface and the vertical growth of the (001) surface comparably.
    Type: Application
    Filed: January 22, 2010
    Publication date: July 29, 2010
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventor: Tomokazu KATSUYAMA
  • Patent number: 7759142
    Abstract: Embodiments described include straining transistor quantum well (QW) channel regions with metal source/drains, and conformal regrowth source/drains to impart a uni-axial strain in a MOS channel region. Removed portions of a channel layer may be filled with a junction material having a lattice spacing different than that of the channel material to causes a uni-axial strain in the channel, in addition to a bi-axial strain caused in the channel layer by a top barrier layer and a bottom buffer layer of the quantum well.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: July 20, 2010
    Assignee: Intel Corporation
    Inventors: Prashant Majhi, Mantu K. Hudait, Jack T. Kavalieros, Ravi Pillarisetty, Marko Radosavljevic, Gilbert Dewey, Titash Rakshit, Willman Tsai
  • Patent number: 7754508
    Abstract: A method of manufacturing a silicon optoelectronic device, a silicon optoelectronic device manufactured by the method, and an image input and/or output apparatus including the silicon optoelectronic device are provided. The method includes preparing an n- or p-type silicon-based substrate, forming a microdefect pattern along a surface of the substrate by etching, forming a control film with an opening on the microdefect pattern, and forming a doping region on the surface of the substrate having the microdefect pattern in such a way that a predetermined dopant of the opposite type to the substrate is injected onto the substrate through the opening of the control film to be doped to a depth so that a photoelectric conversion effect leading to light emission and/or reception by quantum confinement effect in the p-n junction occurs.
    Type: Grant
    Filed: January 20, 2006
    Date of Patent: July 13, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun-kyung Lee, Byoung-iyong Choi, Pil-soo Ahn, Jun-young Kim, Young-gu Jin
  • Patent number: 7751456
    Abstract: A method for manufacturing an laser diode includes: providing a wafer having thereon a semiconductor structure; depositing an SiO2 film; forming channels and a waveguide ridge between the channels in the wafer; forming an SiO2 film over the wafer; forming a resist pattern covering the SiO2 film in the channels such that the top surfaces of the resist pattern are lower than the top surface of the deposited SiO2 film on the top of the waveguide ridge, the resist pattern exposing the SiO2 film on the top of the waveguide ridge; removing the SiO2 film and the deposited SiO2 film by wet etching, using the resist pattern as a mask, to expose a p-GaN layer in the waveguide ridge; and forming an electrode layer on the top surface of the p-GaN layer.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: July 6, 2010
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kazushige Kawasaki, Toshiaki Kitano, Takafumi Oka
  • Patent number: 7745245
    Abstract: At least one recess and/or protruding portion is created on the surface portion of a substrate for scattering or diffracting light generated in a light emitting region. The recess and/or protruding portion has a shape that prevents crystal defects from occurring in semiconductor layers.
    Type: Grant
    Filed: January 30, 2008
    Date of Patent: June 29, 2010
    Assignee: Nichia Corporation
    Inventors: Isamu Niki, Motokazu Yamada, Masahiko Sano, Shuji Shioji
  • Patent number: 7742677
    Abstract: A method for producing an optoelectronic component is disclosed. The method includes the steps of providing a substrate, applying a semiconductor layer sequence to the substrate, applying at least two current expansion layers to the semiconductor layer sequence, applying and patterning a mask layer, patterning the second current expansion layer by means of an etching process during which sidewalls of the mask layer are undercut, patterning the first current expansion layer by means of an etching process during which the sidewalls of the mask layer are undercut at least to a lesser extent than during the patterning of the second current expansion layer, and removing the mask layer.
    Type: Grant
    Filed: June 4, 2007
    Date of Patent: June 22, 2010
    Assignee: Osram Opto Semiconductors GmbH
    Inventors: Franz Eberhard, Uwe Strauss, Ulrich Zehnder, Andreas Weimar, Raimund Oberschmid
  • Publication number: 20100151611
    Abstract: A method for manufacturing a semiconductor laser includes the steps of forming a mask layer having a stripe-shaped mask portion corresponding to a ridge stripe to be formed on a nitride-based group III-V compound semiconductor layer, etching the nitride-based group III-V compound semiconductor layer to a predetermined depth using the mask layer to form the ridge stripe, forming a resist to cover the mask layer and the nitride-based group III-V compound semiconductor layer, etching-back the resist until the stripe-shaped mask portion of the mask layer is exposed, removing the exposed mask portion of the mask layer by etching to expose the upper surface of the ridge stripe, forming a metal film on the resist and the exposed ridge stripe to form an electrode on the ridge stripe, removing the resist together with the metal film formed thereon, and removing the mask layer by etching.
    Type: Application
    Filed: November 16, 2009
    Publication date: June 17, 2010
    Applicant: Sony Corporation
    Inventors: Tsuyoshi Fujimoto, Nozomi Ohashi, Masaru Kuramoto, Eiji Nakayama
  • Patent number: 7736923
    Abstract: An optical semiconductor device includes: a first conductivity type first semiconductor region; a first conductivity type second semiconductor region formed on the first semiconductor region; a second conductivity type third semiconductor region formed on the second semiconductor region; a photodetector section formed of the second semiconductor region and the third semiconductor region; a micro mirror formed of a trench formed selectively in a region of the first semiconductor region and the second semiconductor region except the photodetector section; and a semiconductor laser element held on the bottom face of the trench. A first conductivity type buried layer of which impurity concentration is higher than those of the first semiconductor region and the second semiconductor region is selectively formed between the first semiconductor region and the second semiconductor region in the photodetector section.
    Type: Grant
    Filed: April 7, 2008
    Date of Patent: June 15, 2010
    Assignee: Panasonic Corporation
    Inventor: Takaki Iwai
  • Patent number: 7736925
    Abstract: A method of manufacturing a nitride-based semiconductor laser diode that can minimize optical absorption on a cavity mirror plane and improve the surface roughness of the cavity mirror plane is provided. The method includes the steps of: forming on a (0001) GaN (gallium nitride) substrate having at least two masks spaced apart by a distance equal to a laser cavity length in stripes that extend along the <11-20> direction; growing an n-GaN layer on the GaN substrate between the masks so that two (1-100) edges of the n-GaN layer are thicker than the remaining regions thereof; sequentially stacking an n-clad layer, an active layer, and a p-clad layer on the n-GaN layer to form an edge-emitting laser cavity structure in which laser light generated in the active layer passes through a region of the n-clad layer aligned laterally with the active layer and is output; and etching a (1-100) plane of the laser cavity structure to form a cavity mirror plane.
    Type: Grant
    Filed: June 8, 2006
    Date of Patent: June 15, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tan Sakong, Youn-joon Sung, Ho-sun Paek
  • Patent number: 7736939
    Abstract: A method for forming microlenses of different curvatures is described, wherein a substrate having at least a first and a second areas different in height is provided. A transparent photosensitive layer having a planar surface is formed on the substrate and then patterned into at least two islands of different thicknesses respectively over the first area and the second area. The at least two islands are heated and softened to form at least two microlenses of different curvatures respectively over the first area and the second area, wherein the higher an area is, the smaller the curvature of the corresponding microlens is.
    Type: Grant
    Filed: July 7, 2005
    Date of Patent: June 15, 2010
    Assignee: United Microelectronics Corp.
    Inventors: Hsin-Ping Wu, Chia-Huei Lin
  • Patent number: 7732817
    Abstract: A partition-wall structure having a concave portion corresponding to a pattern formed by a functional liquid, including: a first concave portion provided corresponding to a first pattern; a second concave portion provided corresponding to a second pattern that is coupled to the first pattern and whose width is smaller than a width of the first pattern; and a convex portion provided in the first pattern.
    Type: Grant
    Filed: August 30, 2005
    Date of Patent: June 8, 2010
    Assignee: Seiko Epson Corporation
    Inventors: Toshimitsu Hirai, Toshihiro Ushiyama
  • Patent number: 7732235
    Abstract: A method of making a semiconductor device includes forming a first photoresist layer over an underlying layer, patterning the first photoresist layer into a first photoresist pattern, wherein the first photoresist pattern comprises a plurality of spaced apart first photoresist features located over the underlying layer, and etching the underlying layer using the first photoresist pattern as a mask to form a plurality of first spaced apart features. The method further includes removing the first photoresist pattern, forming a second photoresist layer over the plurality of first spaced apart features, and patterning the second photoresist layer into a second photoresist pattern, wherein the second photoresist pattern comprises a plurality of second photoresist features covering edge portions of the plurality of first spaced apart features.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: June 8, 2010
    Assignee: Sandisk 3D LLC
    Inventors: Roy E. Scheuerlein, Steven Radigan
  • Patent number: 7732229
    Abstract: Methods and devices are provided for absorber layers formed on foil substrate. In one embodiment, a method of manufacturing photovoltaic devices may be comprised of providing a substrate comprising of at least one electrically conductive aluminum foil substrate, at least one electrically conductive diffusion barrier layer, and at least one electrically conductive electrode layer above the diffusion barrier layer. The diffusion barrier layer may prevent chemical interaction between the aluminum foil substrate and the electrode layer. An absorber layer may be formed on the substrate. In one embodiment, the absorber layer may be a non-silicon absorber layer. In another embodiment, the absorber layer may be an amorphous silicon (doped or undoped) absorber layer. Optionally, the absorber layer may be based on organic and/or inorganic materials.
    Type: Grant
    Filed: June 28, 2006
    Date of Patent: June 8, 2010
    Assignee: Nanosolar, Inc.
    Inventors: Craig Leidholm, Brent Bollman, James R. Sheats, Sam Kao, Martin R. Roscheisen
  • Patent number: 7732232
    Abstract: Series interconnection of optoelectronic device modules is disclosed. Each device module includes an active layer disposed between a bottom electrode and a transparent conducting layer. An insulating layer is disposed between the bottom electrode of a first device module and a backside top electrode of the first device module. One or more vias are formed through the active layer, transparent conducting layer and insulating layer of the first device module. Sidewalls of the vias are coated with an insulating material such that a channel is formed through the insulating material to the backside top electrode of the first device module. The channel is at least partially filled with an electrically conductive material to form a plug that makes electrical contact between the transparent conducting layer and the backside top electrode of the first device module.
    Type: Grant
    Filed: October 1, 2007
    Date of Patent: June 8, 2010
    Assignee: Nanosolar, Inc.
    Inventors: James R. Sheats, Sam Kao, Gregory A. Miller, Martin R. Roscheisen
  • Patent number: 7723732
    Abstract: A semiconductor light-emitting device includes a substrate having two main surfaces; and an active layer forming part, which is made of a compound semiconductor material, formed on one of the main surfaces, and includes an active layer. A plurality of holes, which pass through the active layer, are formed from the upper surface of the active layer forming part; a plurality of hollow parts, each of which corresponds to each hole, are provided between the active layer and the substrate; and the area of each hollow part is larger than that of the corresponding hole in plan view, and spreads on the lower surface of the active layer forming part, so as to expose a part of the lower surface of the active layer forming part, which overlaps the hollow part in plan view.
    Type: Grant
    Filed: November 7, 2007
    Date of Patent: May 25, 2010
    Assignee: Sanken Electric Co., Ltd.
    Inventors: Mikio Tazima, Yoshiki Tada
  • Patent number: 7713769
    Abstract: The present invention discloses a light emitting diode structure and a method for fabricating the same. In the present invention, a substrate is placed in a solution to form a chemical reaction layer on carved regions; the carved region is selectively etched to form a plurality of concave zones and form a plurality of convex zones; a semiconductor layer structure is epitaxially grown on the element regions and carved regions of the substrate; the semiconductor layer structure on the element regions is fabricated into a LED element with a photolithographic process.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: May 11, 2010
    Assignee: Tekcore Co., Ltd.
    Inventors: Hung-Cheng Lin, Chia-Ming Lee, Jen-Inn Chyi
  • Publication number: 20100111125
    Abstract: Provided is a VCSEL that includes a lower DBR of a first conductivity type, an active region, and an upper DBR of a second conductivity type, on a substrate. The lower DBR has a first to-be-oxidized Al-containing layer located farther from the active region than a second to-be-oxidized layer that is formed in the upper DBR. Both layers have an oxidized region and a first or a second non-oxidized region surrounded by the oxidized region. The first non-oxidized region is larger than the maximum size of the second non-oxidized region for a single mode oscillation, and smaller than the maximum size of the first non-oxidized region for a single mode oscillation. The second non-oxidized region is larger than the maximum size of the second non-oxidized region for a single mode oscillation. The first non-oxidized region has a size equal to or larger than that of the second non-oxidized region.
    Type: Application
    Filed: May 26, 2009
    Publication date: May 6, 2010
    Applicant: FUJI XEROX CO., LTD.
    Inventor: Takashi Kondo
  • Publication number: 20100111129
    Abstract: A laser diode capable of independently driving each ridge section, and inhibiting rotation of a polarization angle resulting from a stress applied to the ridge section without lowering reliability and a method of manufacturing the same are provided. A laser diode includes: three or more strip-like ridge sections in parallel with each other with a strip-like trench in between, including at least a lower cladding layer, an active layer, and an upper cladding layer in this order; an upper electrode on a top face of each ridge section, being electrically connected to the upper cladding layer; a wiring layer electrically connected to the upper electrode, in the air at least over the trench; and a pad electrode in a region different from regions of both the ridge section and the trench, being electrically connected to the upper electrode through the wiring layer.
    Type: Application
    Filed: October 23, 2009
    Publication date: May 6, 2010
    Applicant: SONY CORPORATION
    Inventors: Makoto Nakashima, Takahiro Yokoyama, Sachio Karino
  • Patent number: 7704759
    Abstract: In a semiconductor laser device, a plurality of light-emitting elements emitting light with different wavelengths are integrated on a substrate. Each of the light-emitting elements includes, on the substrate, an active layer and cladding layers respectively provided on top and bottom of the active layer. One of the cladding layers provided on top of the active layer is an upper cladding layer having a mesa ridge portion. An etching stopper layer for forming the ridge portion is interposed between the ridge portion and the other portion of the upper cladding layer. The thickness of the etching stopper layer varies among the light-emitting elements.
    Type: Grant
    Filed: September 11, 2008
    Date of Patent: April 27, 2010
    Assignee: Panasonic Corporation
    Inventors: Toru Takayama, Satoshi Murasawa, Yasuhiro Fujimoto, Hisashi Nakayama, Isao Kidoguchi
  • Patent number: 7700960
    Abstract: The present invention relates to a light emitting diode with enhanced luminance and light emitting performance due to increase in efficiency of current diffusion into an ITO layer, and a method of fabricating the light emitting diode. According to the present invention, there is manufactured at least one light emitting cell including an N-type semiconductor layer, an active layer and a P-type semiconductor layer on a substrate. The method of the present invention comprises the steps of (a) forming at least one light emitting cell with an ITO layer formed on a top surface of the P-type semiconductor layer; (b) forming a contact groove for wiring connection in the ITO layer through dry etching; and (c) filling the contact groove with a contact connection portion made of a conductive material for the wiring connection.
    Type: Grant
    Filed: October 23, 2009
    Date of Patent: April 20, 2010
    Assignee: Seoul Opto Device Co., Ltd.
    Inventors: Dae Won Kim, Yeo Jin Yoon, Duck Hwan Oh, Jong Hwan Kim
  • Patent number: 7701993
    Abstract: In order to provide excellent device characteristics and enhance fabrication yield and run-to-run reproducibility in a buried device structure using a low mesa on a p-type substrate, a cross sectional configuration before growth of a contact layer of a device, i.e., after growth of an over-cladding layer is flattened so as not to cause a problem in crystal quality of the contact layer. A mesa-stripe stacked body including at least a p-type cladding layer (2), an active layer (4) and an n-type cladding layer (6) is formed on a p-type semiconductor substrate (1), a current-blocking layer (8) is buried in both sides of the stacked body, and an n-type over-cladding layer (9) and an n-type contact layer (10) are disposed on the current-blocking layer (8) and the stacked body. The n-type over-cladding layer (9) is made of a semiconductor crystal having a property for flattening a concavo-convex shape of upper surfaces of the current-blocking layer (8) and the stacked body.
    Type: Grant
    Filed: May 26, 2005
    Date of Patent: April 20, 2010
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Ryuzo Iga, Yasuhiro Kondo
  • Patent number: 7700941
    Abstract: A surface-emitting semiconductor laser includes an active zone, the active zone having a p-n-junction and surrounded by a first n-doped semiconductor layer and at least one p-doped semiconductor layer; a tunnel contact layer on the p-side of the active zone; an n-doped current-carrying layer that covers the tunnel contact layer, the n-doped current-carrying layer comprising a raised portion; and a structured layer having an optical thickness at least equal to the optical thickness of the current-carrying layer in the region of the raised portion, wherein the structured layer is disposed on the current-carrying layer within a maximum distance of 2 ?m from the raised portion.
    Type: Grant
    Filed: April 11, 2006
    Date of Patent: April 20, 2010
    Assignee: Vertilas GmbH
    Inventor: Markus Ortsiefer
  • Publication number: 20100085997
    Abstract: A nitride-based semiconductor laser device includes a nitride-based semiconductor layer formed on an active layer made of a nitride-based semiconductor, and an electrode layer including a first metal layer, made of Pt, formed on a far side of a surface of the nitride-based semiconductor layer from the active layer, a second metal layer, made of Pd, formed on a surface of the first metal layer, and a third metal layer, made of Pt, formed on a surface of the second metal layer, and having a shape necessary for the device in plan view. A thickness of the third metal layer is at least 10 times and not more than 30 times a thickness of the first metal layer.
    Type: Application
    Filed: October 7, 2009
    Publication date: April 8, 2010
    Applicant: Sanyo Electric Co., Ltd.
    Inventors: Gaku Nishikawa, Kiyoshi Oota, Yoshinari Ichihashi