Mesa Formation Patents (Class 438/39)
  • Patent number: 7511311
    Abstract: A nitride semiconductor light-emitting device includes a layered portion emitting light on a substrate. The layered portion includes an n-type semiconductor layer, an active layer, and a p-type semiconductor layer. The periphery of the layered portion is inclined, and the surface of the n-type semiconductor layer is exposed at the periphery. An n electrode is disposed on the exposed surface of the n-type semiconductor layer. This device structure can enhance the emission efficiency and the light extraction efficiency.
    Type: Grant
    Filed: August 1, 2003
    Date of Patent: March 31, 2009
    Assignee: Nichia Corporation
    Inventors: Takeshi Kususe, Takahiko Sakamoto
  • Patent number: 7510891
    Abstract: A method of manufacturing an organic light emitting display device and the organic light emitting display device which reduces generation of dark spots by particles are disclosed.
    Type: Grant
    Filed: October 24, 2006
    Date of Patent: March 31, 2009
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Pil-Geun Chun, Eun-Ah Kim
  • Patent number: 7491983
    Abstract: A high electron mobility transistor is disclosed which has a double-layered main semiconductor region formed on a silicon substrate via a multilayered buffer region. The multilayered buffer region is in the form of alternations of an aluminum nitride layer and a gallium nitride layer. The main semiconductor region, buffer region, and part of the substrate taper as they extend away from the rest of the substrate, providing slanting side surfaces. An electroconductive antileakage overlay covers these side surfaces via an electrically insulating overlay. Electrically coupled to the silicon substrate via a contact electrode, the antileakage overlay serves for reduction of current leakage along the side surfaces.
    Type: Grant
    Filed: February 17, 2006
    Date of Patent: February 17, 2009
    Assignee: Sanken Electric Co., Ltd.
    Inventors: Koji Otsuka, Nobuo Kaneko
  • Publication number: 20090041075
    Abstract: A surface-emitting type semiconductor optical device includes: a first DBR portion of a first conductivity type provided on a GaAs substrate of the first conductivity type; an active layer provided on the first DBR portion; a second DBR portion provided on the active layer; a mesa-shaped conductive layer, which is provided between the first DBR portion and the second DBR portion, and which has, embedded therein, a current confinement portion for supplying current to the active layer; and a burying layer comprising single undoped GaInP and provided between the first DBR portion and the second DBR portion, on the side faces of the conductive layer. The resistivity of the undoped GaInP in the surface-emitting type semiconductor optical device is not lower than 105 ?cm. Improved productivity, as well as favorable device characteristics and high reliability can be achieved as a result.
    Type: Application
    Filed: July 31, 2008
    Publication date: February 12, 2009
    Inventor: Jun-ichi Hashimoto
  • Patent number: 7482183
    Abstract: An electronic device includes a conductive n-type substrate, a Group III nitride active region, an n-type Group III-nitride layer in vertical relationship to the substrate and the active layer, at least one p-type layer, and means for providing a non-rectifying conductive path between the p-type layer and the n-type layer or the substrate. The non-rectifying conduction means may include a degenerate junction structure or a patterned metal layer.
    Type: Grant
    Filed: January 22, 2007
    Date of Patent: January 27, 2009
    Assignee: Cree, Inc.
    Inventors: John A. Edmond, Kathleen M. Doverspike, Michael J. Bergmann, Hua-Shuang Kong
  • Patent number: 7482617
    Abstract: In order to prevent As/P replacement at the boundary face of a re-grown semiconductor layer and avoid a crystalline defect caused by the replacement, there is provided an optical semiconductor device comprising: a semiconductor substrate; a striped stacking body including a first semiconductor layer, an active layer, and a second semiconductor layer; and a burying layer burying the striped stacking body striped stacking body, wherein surfaces in contact with a side face and a bottom face of the burying layer are made of a compound semiconductor that contains arsenic (As) alone as a group V element, and a portion other than the surface includes a group V element other than arsenic.
    Type: Grant
    Filed: October 6, 2005
    Date of Patent: January 27, 2009
    Assignee: Fujitsu Limited
    Inventors: Tsuyoshi Yamamoto, Mitsuru Ekawa
  • Patent number: 7479400
    Abstract: A method of manufacturing a semiconductor laser element having an enhanced yield ratio is provided. The semiconductor laser element having a cladding layer, an intermediate layer, and a capping layer is manufactured as follows. At the laminating step, a plurality of lamination layers are laminated in a laminating direction. Subsequently, at protruding step, a cladding layer, a capping layer and a precursor of an intermediate layer are formed so that widthwise lengths of the cladding layer and the capping layer become shorter or uniform in the laminating direction, and so that the precursor of an intermediate layer protrudes widthwise from the cladding layer and the capping layer. At removing step, an protrusion of the precursor of the intermediate layer is removed.
    Type: Grant
    Filed: July 14, 2005
    Date of Patent: January 20, 2009
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Shinichi Kawato
  • Patent number: 7476558
    Abstract: This invention relates to a method for manufacturing selective area grown stacked-layer electro-absorption modulated laser structure, comprising: step 1: forming a selective growth pattern of a modulator section on a substrate; step 2: simultaneously growing a 2-stacked-layer active region structure of a modulator MQW layer and a laser MQW layer by the first epitaxy step; step 3: etching gratings, and removing the laser MQW layer in the modulator section by selective etching; and step 4: completing the growth of the entire electro-absorption modulated laser structure by a second epitaxy step.
    Type: Grant
    Filed: August 30, 2005
    Date of Patent: January 13, 2009
    Assignee: Institute of Semiconductors, Chinese Academy of Sciences
    Inventors: Hongliang Zhu, Wei Wang
  • Publication number: 20090010293
    Abstract: A nitride semiconductor light emitting device includes an n-type GaN substrate (101) that is a nitride semiconductor substrate, a nitride semiconductor layer including a p-type nitride semiconductor layer formed on the n-type GaN substrate (101). The p-type nitride semiconductor layer includes a p-type AlGaInN contact layer (108), a p-type AlGaInN cladding layer (107) under the p-type AlGaInN contact layer (108), and a p-type AlGaInN layer (106). A protection film (113) made of a silicon nitride film is formed above a current injection region formed in the p-type nitride semiconductor layer.
    Type: Application
    Filed: July 2, 2008
    Publication date: January 8, 2009
    Inventor: Takeshi Kamikawa
  • Publication number: 20090010291
    Abstract: A light-emitting device with a protection layer for Zn inter-diffusion and a process to form the device are described. The device of the invention provides an active layer containing aluminum (Al) as a group III element, typically AlGaInAs, and protection layers containing silicon (Si) to prevent the inter-diffusion of zing (Zn) atoms contained in p-type layers surrounding the active layer. One of protection layers is put between the active layer and the p-type cladding layer, while, the other of protection layers is disposed between the active layer and the p-type burying layer.
    Type: Application
    Filed: June 18, 2008
    Publication date: January 8, 2009
    Inventors: Mitsuo Takahashi, Kenji Hiratsuka, Akiko Kumagai
  • Publication number: 20090001387
    Abstract: To provide a method for manufacturing a large semiconductor device which easily operates normally and has excellent current characteristics. A first single-crystal semiconductor layer is provided over an insulating substrate. Then, the first single-crystal semiconductor layer is processed into an island shape. After that, a second single-crystal semiconductor layer is provided over the insulating substrate so as to overlap with part of a region where the first single-crystal semiconductor layer is provided. After that, the second single-crystal semiconductor layer is processed into an island shape. Thus, defects at joint portions in the case of providing the single-crystal semiconductor layers can be reduced.
    Type: Application
    Filed: June 19, 2008
    Publication date: January 1, 2009
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Hajime KIMURA
  • Publication number: 20090001408
    Abstract: A semiconductor light-emitting device with a new layer structure is disclosed, where the current leaking path is not caused to enhance the current injection efficiency within the active layer. The device provides a mesa structure containing active layer and a p-type lower cladding layer on a p-type substrate and a burying layer doped with iron (Fe) to bury the mesa structure, where the burying layer shows a semi-insulating characteristic. The device also provides an n-type blocking layer arranged so as to cover at least a portion of the p-type buffer lower within the mesa structure. The n-type blocking layer prevents the current leaking from the burying layer to the p-type buffer layer, and the semi-insulating burying layer that covers the rest portion of the mesa structure not covered by the n-type blocking layer prevents the current leaking from the n-type blocking layer to the n-type cladding layer within the mesa structure.
    Type: Application
    Filed: May 16, 2008
    Publication date: January 1, 2009
    Inventors: Atsushi Matsumura, Tomokazu Katsuyama
  • Publication number: 20090003401
    Abstract: Provided is a surface emitting laser which can maintain a fundamental transverse mode to obtain higher power while higher-order transverse mode oscillations are suppressed, and a method of manufacturing the surface emitting laser. The surface emitting laser includes: an aperture portion to be a path for injecting a current to an active layer; a current confinement region provided in the vicinity of the aperture portion; and a current injection region which is provided on an opposite side to a light output side with respect to the active layer therebetween, in which a current injection path in the current injection region has a smaller diameter than the aperture portion.
    Type: Application
    Filed: June 20, 2008
    Publication date: January 1, 2009
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: Yoshinobu Sekiguchi
  • Patent number: 7465977
    Abstract: There is described a method for producing a packaged integrated circuit. The method comprises a first step of building an integrated circuit having a micro-structure suspended above a micro-cavity, and having a heating element on the micro-structure capable of heating itself and its immediate surroundings. A layer of protective material is then deposited on said micro-structure such that at least a top surface of the micro-structure and an opening of the micro-cavity is covered, wherein the protective material is in a solid state at room temperature and can protect the micro-structure during silicon wafer dicing procedures and subsequent packaging. The integrated circuit is packaged and an electric current is passed through the heating element such that a portion of the protective material is removed and an unobstructed volume is provided above and below the micro-structure.
    Type: Grant
    Filed: October 27, 2003
    Date of Patent: December 16, 2008
    Assignee: Microbridge Technologies Inc.
    Inventors: Leslie M. Landsberger, Oleg Grudin
  • Patent number: 7462504
    Abstract: A surface-emitting type light-emitting diode includes a substrate, a p-n junction layer elevated on a portion of the substrate to emit light, and a first isolator layer formed on a sidewall of the p-n junction layer as well as a periphery portion of a top surface of the p-n junction layer except for a central region of the top surface.
    Type: Grant
    Filed: July 18, 2006
    Date of Patent: December 9, 2008
    Assignee: LG Electronics Inc.
    Inventors: Kie Young Lee, Shi Jong Leem
  • Publication number: 20080298412
    Abstract: A semiconductor laser device having a MQW structure composed of an active layer, a p-type second clad layer, and a p-type first clad layer sequentially stacked on an n-type clad layer provided on an n-type GaAs substrate is provided. In the semiconductor laser device, the n-type clad layer and the p-type first clad layer are lattice-matched to the GaAs substrate. A negative strain layer is provided in an intermediate layer of the first clad layer, in which a positive strain layer is provided on both surfaces or one surface of the negative strain layer.
    Type: Application
    Filed: November 28, 2007
    Publication date: December 4, 2008
    Inventor: ATSUSHI NAKAMURA
  • Patent number: 7459354
    Abstract: The crystallization method by laser light irradiation forms a multiplicity of convexes (ridges) in the surface of an obtained crystalline semiconductor film, deteriorating film quality. Therefore, it is a problem to provide a method for forming a ridge-reduced semiconductor film and a semiconductor device using such a semiconductor film. The present invention is characterized by heating a semiconductor film due to a heat processing method (RTA method: Rapid Thermal Anneal method) to irradiate light emitted from a lamp light source after crystallizing the semiconductor film by laser light, thereby reducing the ridge.
    Type: Grant
    Filed: July 23, 2004
    Date of Patent: December 2, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideto Ohnuma, Tamae Takano, Toru Mitsuki
  • Publication number: 20080293177
    Abstract: Provided is a method of manufacturing a nitride-based semiconductor LED including sequentially forming an n-type nitride semiconductor layer, an active layer, and a p-type nitride semiconductor layer on a substrate; forming a Pd/Zn alloy layer on the p-type nitride semiconductor layer; heat-treating the p-type nitride semiconductor layer on which the Pd/Zn alloy layer is formed; removing the Pd/Zn alloy layer formed on the p-type nitride semiconductor layer; mesa-etching portions of the p-type nitride semiconductor layer, the active layer, and the n-type nitride semiconductor layer such that a portion of the upper surface of the n-type nitride semiconductor layer is exposed; and forming an n-electrode and a p-electrode on the exposed n-type nitride semiconductor layer and the p-type nitride semiconductor layer, respectively.
    Type: Application
    Filed: August 13, 2007
    Publication date: November 27, 2008
    Inventors: Sun Woon Kim, Seong Ju Park, Ja Yeon Kim, Min Ki Kwon, Dong Ju Lee, Jae Ho Han
  • Patent number: 7455563
    Abstract: An electroluminescence display device including a substrate, a corrugated structure formed on the substrate, wherein the corrugated structure disperses light through diffraction and reflection; and a first electrode layer, a first insulation layer, a fluorescent layer, a second insulation layer, and a second electrode layer sequentially formed on the substrate to follow the shape of the corrugated structure.
    Type: Grant
    Filed: December 19, 2006
    Date of Patent: November 25, 2008
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Young-Rag Do, Yoon-Chang Kim, Ji-Hoon Ahn, Sang-Hwan Cho, Joon-Gu Lee
  • Publication number: 20080283852
    Abstract: A light-emitting device and a method to from the device are is described. The device described herein may realize the transversely single mode operation by the buried mesa configuration even when the active layer contains aluminum. The method provides a step to form the mesa on a semiconductor substrate with an average dislocation density of 500 to 5000 cm?2, a step to form a protection layer, which prevents the active layer from oxidizing, at least on a side of the active layer, and a step to from a blocking layer so as to cover the protection layer and to bury the mesa.
    Type: Application
    Filed: May 13, 2008
    Publication date: November 20, 2008
    Inventors: Yukihiro TSUJI, Kenji Hiratsuka, Mitsuo Takahashi
  • Publication number: 20080280386
    Abstract: A method for manufacturing an laser diode includes: providing a wafer having thereon a semiconductor structure; depositing an SiO2 film; forming channels and a waveguide ridge between the channels in the wafer; forming an SiO2 film over the wafer; forming a resist pattern covering the SiO2 film in the channels such that the top surfaces of the resist pattern are lower than the top surface of the deposited SiO2 film on the top of the waveguide ridge, the resist pattern exposing the SiO2 film on the top of the waveguide ridge; removing the SiO2 film and the deposited SiO2 film by wet etching, using the resist pattern as a mask, to expose a p-GaN layer in the waveguide ridge; and forming an electrode layer on the top surface of the p-GaN layer.
    Type: Application
    Filed: October 31, 2007
    Publication date: November 13, 2008
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Kazushige Kawasaki, Toshiaki Kitano, Takafumi Oka
  • Publication number: 20080279241
    Abstract: A light-emitting element includes a mesa structure in which a first compound semiconductor layer of a first conductivity type, an active layer, and a second compound semiconductor layer of a second conductivity type are disposed in that order, wherein at least one of the first compound semiconductor layer and the second compound semiconductor layer has a current constriction region surrounded by an insulation region extending inward from a sidewall portion of the mesa structure; a wall structure disposed so as to surround the mesa structure; at least one bridge structure connecting the mesa structure and the wall structure, the wall structure and the bridge structure each having the same layer structure as the portion of the mesa structure in which the insulation region is provided; a first electrode; and a second electrode disposed on a top face of the wall structure.
    Type: Application
    Filed: April 3, 2008
    Publication date: November 13, 2008
    Applicant: Sony Corporation
    Inventors: Tomoyuki Oki, Yuji Masui, Yoshinori Yamauchi, Rintaro Koda, Takahiro Arakida
  • Patent number: 7449354
    Abstract: A trench-gated field effect transistor (FET) is formed as follows. Using one mask, a plurality of active gate trenches and at least one gate runner trench are defined and simultaneously formed in a silicon region such that (i) the at least one gate runner trench has a width greater than a width of each of the plurality of active gate trenches, and (ii) the plurality of active gate trenches are contiguous with the at least one gate runner trench.
    Type: Grant
    Filed: January 5, 2006
    Date of Patent: November 11, 2008
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Bruce Douglas Marchant, Thomas E. Grebs, Rodney S. Ridley, Nathan Lawrence Kraft
  • Patent number: 7445949
    Abstract: A method of manufacturing a semiconductor laser device is provided. First, a first mask layer is formed on an epitaxial structure to define a protrudent area in a ridge structure. Thereafter, a conformal second mask layer is formed over the epitaxial structure to cover the first mask layer. A third mask layer is formed over the second mask layer. The exposed second mask layer is removed. Using the first and the third mask layers as etching masks, a portion of the epitaxial structure is removed. The third mask layer and the remaining second mask layer are removed to form the ridge structure. An insulation layer is formed on the epitaxial structure and then the first mask layer is removed to expose the top surface of the protrudent area. A conductive layer is formed on the epitaxial structure such that it contacts with the top surface of the protrudent area.
    Type: Grant
    Filed: August 6, 2004
    Date of Patent: November 4, 2008
    Assignee: National Central University
    Inventors: Hung-Cheng Lin, Jen-Inn Chyi, Guan-Ting Chen
  • Patent number: 7439091
    Abstract: A light-emitting diode (LED) and a method for manufacturing the same are described. The method for manufacturing the LED comprises the following steps. An illuminant epitaxial structure is provided, in which the illuminant epitaxial structure has a first surface and a second surface on opposite sides, and a substrate is deposed on the first surface of the illuminant epitaxial structure. A metal layer is formed on the second surface of the illuminant epitaxial structure. An anodic oxidization step is performed to oxidize the metal layer, so as to form a metal oxide layer. An etching step is performed to remove a portion of the metal oxide layer, so as to form a plurality of holes in the metal oxide layer.
    Type: Grant
    Filed: February 22, 2007
    Date of Patent: October 21, 2008
    Assignee: Epistar Corporation
    Inventors: Shi-Ming Chen, Mau-Phon Houng, Chang-Hsing Chu, Te-Chi Yen
  • Publication number: 20080247439
    Abstract: In a semiconductor laser device (LD1), a semiconductor laser layer is formed on one face of a semiconductor substrate (1), and a p-type electrode (8) and an n-type electrode (11) are provided on the semiconductor laser layer side and the semiconductor substrate (1) side, respectively, so as to sandwich the semiconductor laser layer and the semiconductor substrate (1) therebetween. The p-type electrode (8) includes a first electrode (9) and a second electrode (10) that covers the first electrode (9).
    Type: Application
    Filed: March 2, 2005
    Publication date: October 9, 2008
    Inventors: Yozo Uchida, Kenji Nakashima, Seiji Kawamoto
  • Publication number: 20080240191
    Abstract: In a p-type clad layer, not only a p-type dopant Zn but also Fe is doped. Its Zn concentration is 1.5×1018 cm?3 and the Fe concentration is 1.8×1017 cm?3. In a semi-insulating burying layer, Fe is doped as an impurity generating a deep acceptor level and the concentration thereof is 6.0×1016 cm?3. The Fe concentration in the p-type clad layer is thus three times higher than the Fe concentration in the burying layer.
    Type: Application
    Filed: March 21, 2008
    Publication date: October 2, 2008
    Applicants: FUJITSU LIMITED, EUDYNA DEVICES INC.
    Inventors: Kan TAKADA, Mitsuru EKAWA, Tsuyoshi YAMAMOTO, Tatsuya TAKEUCHI
  • Publication number: 20080233670
    Abstract: A method of fabricating a p-i-n type light emitting diode using p-type ZnO, and particularly, a technique for fabricating a p-type ZnO thin film doped with copper, a light emitting diode manufactured using the same, and its application to electrical and magnetic devices. The method of fabricating a p-i-n type light emitting diode using p-type ZnO includes depositing a low-temperature ZnO buffer layer on a sapphire single-crystal substrate, depositing an n-type gallium doped ZnO layer on the deposited low-temperature ZnO buffer layer, depositing an intrinsic ZnO thin film on the deposited n-type gallium doped ZnO layer, forming a p-type ZnO thin film layer on the deposited intrinsic ZnO thin film, forming a MESA structure on the p-type ZnO thin film layer through wet etching to obtain a diode structure, and subjecting the diode structure to post-heat treatment.
    Type: Application
    Filed: December 9, 2005
    Publication date: September 25, 2008
    Applicant: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Won-kook Choi, Yeon-sik Jung
  • Publication number: 20080230793
    Abstract: Disclosed herein are a patterned substrate for a light emitting diode and a light emitting diode employing the patterned substrate. The substrate has top and bottom surfaces. Protrusion patterns are arranged on the top surface of the substrate. Furthermore, recessed regions surround the protrusion patterns. The recessed regions have irregular bottoms. Thus, the protrusion patterns and the recessed regions can prevent light emitted from a light emitting diode from being lost due to the total reflection to thereby improve light extraction efficiency.
    Type: Application
    Filed: November 28, 2006
    Publication date: September 25, 2008
    Applicant: SEOUL OPTO DEVICE CO., LTD.
    Inventors: Yeo Jin Yoon, Won Cheol Seo
  • Publication number: 20080203394
    Abstract: The present invention provides a method of an active-matrix thin film transistor array, comprising of two levels of metallic interconnections formed from one layer of metallic conductor; and thin-film transistors with source, drain and gate electrodes either fully or partially replaced with metal, and wherein the pixel electrodes are polycrystalline silicon.
    Type: Application
    Filed: November 24, 2006
    Publication date: August 28, 2008
    Inventors: Hoi-Sing Kwok, Man Wong, Zhiguo Meng, Dongli Zhang, Jiaxin Sun, Xiuling Zhu
  • Publication number: 20080197377
    Abstract: A photonic semiconductor device which includes a semiconductor layer having a ridge-form protruding part formed on a semiconductor substrate. A resin layer is formed on surface parts on both sides of the protruding part so that the protruding part is embedded, and a first insulating film includes an opening that is formed on the resin layer which exposes an upper surface of the protruding part and a portion of a upper surface of the resin layer on both sides of the protruding part. A first electrode is formed in the opening so as to cover the upper surface of the protruding part, and electrically couple to an upper part of the protruding part; and a second electrode, which electrically couples to the first electrode, is formed on the first electrode and the first insulation film.
    Type: Application
    Filed: February 15, 2008
    Publication date: August 21, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Hisao SUDO, Tsuyoshi YAMAMOTO
  • Publication number: 20080192781
    Abstract: The present invention relates in general to semiconductor light emitting devices and in particular to methods of altering the spatial emission patterns of such devices. A known problem with these prior art light emitting devices (and laser diodes in general) is that their far-field emission patterns are elliptical and astigmatic in nature. The present invention addresses this problem by refractive index perurbations in the semiconductor device aligned in a direction substantially transverse to the light emission direction to achieve a desired spatial distribution of the emission.
    Type: Application
    Filed: September 5, 2005
    Publication date: August 14, 2008
    Applicant: EBLANA PHOTONICS LIMITED
    Inventors: James C. O'Gorman, Brian J. Kelly, John A. Patchell
  • Patent number: 7411220
    Abstract: A semiconductor light emitting device can have stable electric characteristics and can emit light with high intensity from a substrate surface. The device can include a transparent substrate and a semiconductor layer on the substrate. The semiconductor layer can include a first conductive type semiconductor layer, a luminescent layer, a second conductive type semiconductor layer, and first and second electrodes disposed to make contact with the first and second conductive type semiconductor layers, respectively. The first conductive type semiconductor layer, the luminescent layer, and the second conductive type semiconductor layer can be laminated in order from the side adjacent the substrate. An end face of the semiconductor layer can include a first terrace provided in an end face of the first conductive type semiconductor layer in parallel with the substrate surface, and an inclined end face region provided nearer to the substrate than the first terrace.
    Type: Grant
    Filed: June 17, 2005
    Date of Patent: August 12, 2008
    Assignee: Stanley Electric Co. Ltd.
    Inventors: Naochika Horio, Munehiro Kato, Masahiko Tsuchiya, Satoshi Tanaka
  • Publication number: 20080181276
    Abstract: A semiconductor laser diode device with small driving current and no distortion in the projected image.
    Type: Application
    Filed: January 31, 2008
    Publication date: July 31, 2008
    Inventors: Satoshi Kawanaka, Atsushi Nakamura, Masato Hagimoto, Hideki Hara, Masakatsu Yamamoto
  • Patent number: 7399657
    Abstract: Ball grid array packages for semiconductor die include a thermally conductive container and a substrate that substantially enclose a semiconductor die. The die is positioned with respect to the container by thermally conductive supports formed in the container or attached to the container. The die contacts the supports so that the die and the container form a cavity that is at least partially filled with a thermally conductive material such as a conductive epoxy to promote thermal conduction between the die and the container. The die electrically connects to the substrate with bond wires that extend through an aperture in the substrate and attach to bond pads provided on the substrate. The aperture is typically filled with a protective layer of resin, epoxy, or other material that also encapsulates the bond wires.
    Type: Grant
    Filed: July 31, 2002
    Date of Patent: July 15, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Todd O. Bolken, Chad A. Cobbley
  • Patent number: 7396476
    Abstract: Methods of fabricating comb drive devices utilizing one or more sacrificial etch-buffers are disclosed. An illustrative fabrication method may include the steps of etching a pattern onto a wafer substrate defining one or more comb drive elements and sacrificial etch-buffers, liberating and removing one or more sacrificial etch-buffers prior to wafer bonding, bonding the etched wafer substrate to an underlying support substrate, and etching away the wafer substrate. In some embodiments, the sacrificial etch-buffers are removed after bonding the wafer to the support substrate. The sacrificial etch-buffers can be provided at one or more selective regions to provide greater uniformity in etch rate during etching. A comb drive device in accordance with an illustrative embodiment can include a number of interdigitated comb fingers each having a more uniform profile along their length and/or at their ends, producing less harmonic distortion during operation.
    Type: Grant
    Filed: January 17, 2006
    Date of Patent: July 8, 2008
    Assignee: Honeywell International Inc.
    Inventors: Jeffrey A. Ridley, James A. Neus
  • Publication number: 20080157059
    Abstract: An active layer having a p-type quantum dot structure is disposed over a lower cladding layer made of semiconductor material of a first conductivity type. An upper cladding layer is disposed over the active layer. The upper cladding layer is made of semiconductor material, and includes a ridge portion and a cover portion. The ridge portion extends in one direction, and the cover portion covers the surface on both sides of the ridge portion. A capacitance reducing region is disposed on both sides of the ridge portion and reaching at least the lower surface of the cover portion. The capacitance reducing region has the first conductivity type or a higher resistivity than that of the ridge portion, and the ridge portion has a second conductivity type. If the lower cladding layer is an n-type, the capacitance reducing region reaches at least the upper surface of the lower cladding layer.
    Type: Application
    Filed: October 22, 2007
    Publication date: July 3, 2008
    Applicants: FUJITSU LIMITED, THE UNIVERSITY OF TOKYO
    Inventors: Nobuaki Hatori, Tsuyoshi Yamamoto, Hisao Sudo, Yasuhiko Arakawa
  • Publication number: 20080157106
    Abstract: A nitride semiconductor laser element comprises a substrate, a nitride semiconductor layer that is laminated on the substrate and that has a ridge on its surface, and an electrode that is electrically connected with the nitride semiconductor layer, wherein there is provided an insulating protective film produced by forming a monocrystalline first film or a first film containing hexagonal crystals, and extending from the side faces of the ridge to the nitride semiconductor layer on both sides of the ridge, and a second film containing a polycrystalline or amorphous substance, from the nitride semiconductor layer side, in this order.
    Type: Application
    Filed: December 22, 2007
    Publication date: July 3, 2008
    Applicant: NICHIA CORPORATION
    Inventors: Shingo Masui, Tomonori Morizumi
  • Publication number: 20080137703
    Abstract: In order to provide excellent device characteristics and enhance fabrication yield and run-to-run reproducibility in a buried device structure using a low mesa on a p-type substrate, a cross sectional configuration before growth of a contact layer of a device, i.e., after growth of an over-cladding layer is flattened so as not to cause a problem in crystal quality of the contact layer. A mesa-stripe stacked body including at least a p-type cladding layer (2), an active layer (4) and an n-type cladding layer (6) is formed on a p-type semiconductor substrate (1), a current-blocking layer (8) is buried in both sides of the stacked body, and an n-type over-cladding layer (9) and an n-type contact layer (10) are disposed on the current-blocking layer (8) and the stacked body. The n-type over-cladding layer (9) is made of a semiconductor crystal having a property for flattening a concavo-convex shape of upper surfaces of the current-blocking layer (8) and the stacked body.
    Type: Application
    Filed: May 26, 2005
    Publication date: June 12, 2008
    Inventors: Ryuzo Iga, Yasuhiro Kondo
  • Publication number: 20080137702
    Abstract: A buried semiconductor laser exhibiting a reduced dislocation of a contact layer is achieved. A buried semiconductor laser, comprising: an n-type indium phosphide (InP) substrate; an active layer disposed on the n-type InP substrate; block layers provided so as to bilaterally disposed on both sides of the active layer; a clad layer provided so as to cover the active layer and the block layers; and a p-type gallium indium arsenide (InGaAs) contact layer provided on the clad layer, wherein the p-type InGaAs contact layer has a compressive strain.
    Type: Application
    Filed: December 7, 2007
    Publication date: June 12, 2008
    Applicant: NEC Electronics Corporation
    Inventor: Satoshi Ae
  • Publication number: 20080135868
    Abstract: In an element structure of a nitride semiconductor light emitting element, the laminate including a light emitting part having a laminate structure of a first n-type layer 13, a p-type clad layer 15 and an active layer 14 sandwiched between them, and a second n-type layer 16 present at the outer side of the light emitting part and at the p-type clad layer side. When the laminate is to be grown on a substrate 11, the light emitting part has the p-type clad layer 15 placed on the upper side of the second n-type layer 16 is placed on the further upper side of the light emitting part. The second n-type layer 16 is dry-etched to form an exposed surface. An electrode P12 is formed on the surface exposed by dry etching, whereby the electrode P12 becomes a p-side electrode having a low contact resistance, which is used for injecting a hole in the p-type clad layer 15 of the aforementioned light emitting part, even if the electrode P12 is formed in the n-type layer 16.
    Type: Application
    Filed: September 29, 2005
    Publication date: June 12, 2008
    Applicant: MITSUBISHI CABLE INDUSTRIES, LTD.
    Inventors: Hiroaki Okagawa, Shin Hiraoka
  • Patent number: 7374959
    Abstract: A two-wavelength semiconductor laser device includes a first conductive material substrate having thereon first and second regions separated from each other. A first semiconductor laser diode is formed on the first region. A non-active layer is formed on the second region and has the same layers as those of the first semiconductor laser diode. A second semiconductor laser diode is formed on the non-active layer. A lateral conductive region is formed at least between the first and second semiconductor laser diodes.
    Type: Grant
    Filed: May 24, 2006
    Date of Patent: May 20, 2008
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Chong Mann Koh
  • Publication number: 20080111139
    Abstract: Provided is a vertical light emitting device having improved light extraction efficiency and a method of manufacturing the same. The vertical light emitting device may include a p type electrode, a p type semiconductor layer, an active layer, and an n type semiconductor layer which may be sequentially formed on the p type electrode, and an n type electrode on a portion of a surface of the n type semiconductor layer, wherein the portion of the surface of the n type semiconductor layer may be at an inclined plane inclined from an area near a circumference of the n type electrode towards the active layer. The p type electrode may include a current blocking layer which is made of an insulating material and on the p type electrode directly under the n type electrode. Accordingly, a voltage increase may be minimized or reduced, and light extraction efficiency may be improved.
    Type: Application
    Filed: July 24, 2007
    Publication date: May 15, 2008
    Inventors: Jung-hye Chae, Myoung-gyun Suh
  • Patent number: 7371595
    Abstract: A method for manufacturing a semiconductor laser device is provided in which deformation of a cap layer and a third cladding layer is inhibited and a protruding portion of an intermediate layer is removed. By coating outer peripheral portions facing an intermediate layer of a third cladding layer and an etching stop layer with a resist, inevitably removing at least the third cladding layer, and etching the intermediate layer and a cap layer in a second etching step, a protruding portion of the intermediate layer is removed, and the cap layer is prevented from being etched undesirably, whereby a ridge portion without irregularities with respect to a direction substantially perpendicular to a lamination direction is produced, and increase of an operation voltage and decrease of external differential quantum efficiency are prevented.
    Type: Grant
    Filed: October 28, 2005
    Date of Patent: May 13, 2008
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Atsuo Tsunoda, Akiyoshi Sugahara
  • Patent number: 7344904
    Abstract: Provided is a method of fabricating a laser diode.
    Type: Grant
    Filed: June 15, 2005
    Date of Patent: March 18, 2008
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Yeon-hee Kim, Kwang-ki Choi, Youn-joon Sung
  • Patent number: 7338827
    Abstract: A method for fabricating nitride semiconductor devices according to the present invention includes the steps of: (A) providing a nitride semiconductor substrate, which will be split into chip substrates, which includes device portions that will function as the respective chip substrates when the substrate is split and interdevice portions that connect the device portions together, and in which the average thickness of the interdevice portions is smaller than the thickness of the device portions; (B) defining a masking layer, which has striped openings over the device portions, on the upper surface of the nitride semiconductor substrate; (C) selectively growing nitride semiconductor layers on portions of the upper surface of the nitride semiconductor substrate, which are exposed through the openings of the masking layer; and (D) cleaving the nitride semiconductor substrate along the interdevice portions of the nitride semiconductor substrate, thereby forming nitride semiconductor devices on the respectively sp
    Type: Grant
    Filed: March 9, 2004
    Date of Patent: March 4, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Gaku Sugahara, Yasutoshi Kawaguchi, Akihiko Ishibashi, Isao Kidoguchi, Toshiya Yokogawa
  • Publication number: 20080049804
    Abstract: The present invention provides a semiconductor laser diode that has the buried mesa stripe and a current blocking layer without involving any pn-junction. The laser diode includes a lower cladding layer, an active region and an upper cladding layer on the GaAs substrate in this order. The mesa stripe, buried with the current blocking layer, includes the first portion of the upper cladding layer in addition to the active region. The current blocking layer of the invention is made of one of un-doped GaInP and un-doped AlGaInP grown at a relatively low temperature below 600° C. and shows high resistivity greater than 105 ?·cm for the bias voltage below 5 V.
    Type: Application
    Filed: August 15, 2007
    Publication date: February 28, 2008
    Inventor: Jun-ichi Hashimoto
  • Patent number: 7335519
    Abstract: A method for manufacturing a light-emitting diode (LED) is disclosed. In the method, a substrate is firstly provided, in which a first conductivity type cladding layer, an active layer, a second conductivity type cladding layer, a superlattice contact layer and a transparent conductive oxide layer are stacked on the substrate in sequence. Next, an etching mask layer is formed on a portion of the transparent conductive oxide layer, in which the etching mask layer is an insulator. Then, a definition step is performed by using the etching mask layer to remove an exposed portion of the transparent conductive oxide layer, and the superlattice contact layer, the second conductivity type cladding layer and the active layer under the exposed portion of the transparent conductive oxide layer until the first conductivity type cladding layer is exposed. The etching mask layer is then removed.
    Type: Grant
    Filed: April 14, 2005
    Date of Patent: February 26, 2008
    Assignee: Epitech Technology Corporation
    Inventors: Shih-Chang Shei, Ming-Lum Lee
  • Patent number: 7329569
    Abstract: A method of forming a semiconductor device may include forming a semiconductor structure on a substrate wherein the semiconductor structure defines a mesa having a mesa surface opposite the substrate and mesa sidewalls between the mesa surface and the substrate. A first passivation layer can be formed on at least portions of the mesa sidewalls and on the substrate adjacent the mesa sidewalls wherein at least a portion of the mesa surface is free of the first passivation layer and wherein the first passivation layer comprises a first material. A second passivation layer can be formed on the first passivation layer wherein at least a portion of the mesa surface is free of the second passivation layer, and wherein the second passivation layer comprises a second material different than the first material. Related devices are also discussed.
    Type: Grant
    Filed: December 19, 2003
    Date of Patent: February 12, 2008
    Assignee: Cree, Inc.
    Inventors: Kevin Ward Haberern, Raymond Rosado, Michael John Bergman, David Todd Emerson
  • Publication number: 20080032435
    Abstract: The method for manufacturing a semiconductor laser element according to the present invention has the steps of: forming a semiconductor laminated structure having an active layer composed of a semiconductor material containing Al; etching the semiconductor laminated structure to form a mesa; forming a first burying layer at a first growing temperature so as to coat the side of the mesa; and forming a second burying layer at a second growing temperature higher than the first growing temperature on the first burying layer to bury the circumference of the mesa.
    Type: Application
    Filed: January 22, 2007
    Publication date: February 7, 2008
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Chikara Watatani, Toru Ota, Takashi Nagira