Abstract: A semiconductor device has both a logic section and a non-volatile memory (NVM) section. Transistors in both sections are separated by trench isolation. The logic isolation has narrower trenches than NVM trenches and both types of trenches have corners at the tops thereof. The trenches are lined by growing an oxide that is necessarily to take care of the plasma damage of the substrate, which is preferably silicon, that occurs during the formation of the trenches. These oxide liners are grown to a greater thickness in the NVM trenches than in the logic trenches to obtain a greater degree of corner rounding in the NVM trenches. This growth differential is achieved by selectively implanting the NVM trenches with a species that speeds oxide growth or selectively implanting the logic trenches with a species that retards oxide growth. As a further alternative, the NVM trenches can be implanted with a growth enhancing species and the logic trenches with a retarding species.

Abstract: A method comprising forming a first trench in a substrate, and forming a second trench in the substrate, the second trench intersecting the first trench and having a retrograde sidewall profile relative to a direction from a top of the trench to a bottom of the trench. An apparatus comprising a matrix of cells in a substrate formed by a plurality of first trenches and a plurality of second trenches, the plurality of second trenches intersecting the plurality of first trenches and having a retrograde sidewall profile relative to a direction from a top to a bottom of the respective trench; and an electrically accessible storage device coupled to respective ones of the matrix of cells.

Abstract: The invention utilizes introductions of oxygen and hydroxyl to perform an in situ steam generated process to reoxidize a conventional sidewall oxide layer and density the oxide in a shallow trench isolation. The ISSG process renders the conventional sidewall oxide layer much less stress and encroachment. The electrical property of the active regions and the isolation quality between the active regions can be assured. The ISSG process can densify the oxide in a shallow trench isolation to prevent the oxide from being lost in the following clean process.

Abstract: To form substrate isolation for a nonvolatile memory, floating gate polysilicon (410) is formed over a semiconductor substrate (110), then silicon nitride (130) is deposited, and then the nitride, the floating gate polysilicon and the substrate are etched to form isolation trenches (140). Dielectric (150) is formed in the trenches and over the silicon nitride. The dielectric thickness is relatively small so that the top surface (150T) of the dielectric over the trenches lies at all times below the top surface of silicon nitride. The dielectric deposition and polishing times are therefore reduced. Other embodiments are also provided.

Abstract: A high-voltage transistor and fabrication process in which the fabrication of the high-voltage transistor can be readily integrated into a conventional CMOS fabrication process. The high-voltage transistor of the invention includes a channel region formed beneath a portion of the gate electrode after the gate electrode has been formed on the surface of a semiconductor substrate. In a preferred embodiment, the channel region is formed by the angled ion implantation of dopant atoms using an edge of the gate electrode as a doping mask. The high-voltage transistor of the invention further includes a drain region that is spaced apart from the channel region by a portion of a well region and by an isolation region residing in the semiconductor substrate. By utilizing the process of the invention to fabricate the high-voltage transistor, the transistor can be integrated into an existing CMOS device with minimal allocation of additional substrate surface area.

Abstract: To provide a method for producing a non-volatile semiconductor memory device that can form trenches having different depths in a reduced number of processes.

Abstract: A process for producing a semiconductor device including plural element forming regions having different element region widths W and element isolating regions between said element forming regions. The process includes forming trenches on a semiconductor substrate having previously accumulated thereon a first dielectric film for forming isolating regions; accumulating a second dielectric film having a thickness t on the semiconductor substrate to fill in trenches; removing part of the second dielectric film on element forming regions that have an element regions width W satisfying the following equation: W≧2t/tan &thgr;, wherein &thgr; represents a accumulation angle of said second dielectric film on said element forming region; and polishing the second dielectric film.

Abstract: In a combined isolation oxide film (BT1), a part closer to a gate electrode (GT13) reaches a buried oxide film (2) through an SOI layer (3) while a part closer to another gate electrode (GT12) has a sectional shape provided with a well region on its lower portion. The shape of an edge portion of the combined isolation oxide film (BT1) is in the form of a bird's beak in a LOCOS isolation oxide film. Consequently, the thicknesses of portions defining edge portions of the gate oxide films (GO12, GO13) are locally increased. Thus provided are a semiconductor device including a MOS transistor having a gate oxide film prevented from dielectric breakdown without increasing its thickness and a method of manufacturing the same.

Abstract: A method of chemical-mechanical polishing for forming a shallow trench isolation is disclosed. A substrate having a number of active regions, including a number of relative large active regions and a number of relative small active regions, is provided. The method comprises the following steps. A silicon nitride layer on the substrate is first formed. A number of shallow trenches are formed between the active regions. An oxide layer is formed over the substrate, so that the shallow trenches are filled with the oxide layer. A partial reverse active mask is formed on the oxide layer. The partial rever active mask has an opening at a central part of each relative large active region. The opening exposes a portion of the oxide layer. The opening has at least a dummy pattern. The oxide layer on the central part of each large active region is removed to expose the silicon nitride layer. The partial reverse active mask is removed. The oxide layer is planarized to expose the silicon nitride layer.

Abstract: A method of fabricating a trench isolation structure in a high-density semiconductor device that provides an isolation characteristic that is independent of the properties of adjacent MOS transistor devices, wherein a first trench in a first isolation area and a second trench implanted are formed on a semiconductor substrate, a nitrogen (N)-rich silicon layer is formed on the sidewall in a second isolation area, a subsequent oxidation process may be employed to fabricate oxide layers, each having a different thickness, on the sidewall surfaces of the first and second trenches. When the first and second oxide-layered trenches are filled with a stress relief liner and a dielectric material, the different thicknesses of the oxides prevent leakage currents from flowing to an adjacent semiconductor device, regardless of the doping properties of each device.

Abstract: A method for forming uniform-depth recesses across areas of different trench density, in accordance with the present invention, includes providing a substrate having trenches formed therein. The substrate includes regions of different trench density. The trenches are filled with a first filler material, and the first filler material is removed from a surface of the substrate. A second filler material is formed over the surface of the substrate such that the depth of the second filler material is substantially uniform across the regions of different trench density.

Abstract: A method of manufacturing a semiconductor device is provided which, even if device dimensions decrease, prevents degradation in the operating characteristics of semiconductor elements which are isolated from each other by an element isolation region in a trench isolation structure. Implantation of ions (15) in a polycrystalline silicon layer (3) from above through a silicon nitride film (2) produces an ion-implanted polycrystalline silicon layer (16). Since the ions (15) are an ionic species of element which acts to enhance oxidation, the implantation of the ions (15) changes the polycrystalline silicon layer (3) into the ion-implanted polycrystalline silicon layer (16) having a higher oxidation rate. In subsequent formation of a thermal oxide film (21) on the inner wall of a trench (5), exposed part of the ion-implanted polycrystalline silicon layer (16) is also oxidized, forming relatively wide polycrystalline silicon oxide areas (21a).

Abstract: A method of forming a shallow trench isolation layer in a semiconductor device is provided, wherein a first trench and a second trench are formed in an area selected from a semiconductor substrate and a sidewall oxide layer, an anti-oxidation liner, and a mask layer are formed on the semiconductor substrate including the inner surfaces of the first and second trenches, in the same order. Using photoresist lithography, the mask layer and the anti-oxidation layer are etched in the second trench. An isolation layer is formed in the first and second trenches by depositing and then chemically and mechanically polishing the dielectric material and the layers underneath until the semiconductor substrate surface is exposed. The first trench provides isolation between N-FETs, an N-FET and a P-FET, an N-FET and other circuit devices, a P-FET and other circuit devices, and other circuit devices and the second trench provides isolation between P-FETs.

Abstract: A method for fabricating a semiconductor device by one masking process using selective epitaxial growth, comprising the steps of providing a first conductive silicon substrate having an active region and field regions thereon and having a formed pad oxide layer on the surface, forming a trench having a width including the active region and field regions at both sides of the active region by etching the pad oxide layer and silicon substrate, forming a spacer having a width similar to that of the field region at both sidewalls of the trench and exposing active region of the silicon substrate, forming a second conductive well on the exposed active region of the silicon substrate by growing an in-situ doped silicon epi layer to a height similar to a surface of the silicon substrate, depositing an oxide layer on the resultant structure to fill a gap between the spacer and the well and performing planarization of the oxide layer to expose a surface of the silicon substrate and to form isolation layers at both sides

Abstract: When a top surface area for a plurality of dummy patterns 13 and a width for a plurality of trenches 12 are set on the basis of a ratio (an occupation density of the film for polishing in an adjacent region 10) of a total top surface area for raised sections of the film for polishing to a horizontally projected area of the adjacent region 10, it is possible to suppress dishing and erosion and thereby attain a high planarity when a film for polishing is formed on a semiconductor substrate, wherein dummy patterns 13 partitioned by a plurality of trenches 12 are disposed in an element isolation region 11, and planarization by the CMP is applied thereto.

Abstract: A method for fabricating shallow trench isolation structures. A substrate is provided on which are sequentially stacked a buffer oxide layer and a mask layer. A plurality of trenches with different densities is formed in the stack of substrate/buffer oxide/mask layers. An insulating layer is formed over the substrate to fill the trenches. A planarized sacrificial layer is formed by spin coating polymer on the insulating layer. The sacrificial layer is completely removed by dry etching. A predetermined thickness of the insulating layer is removed such that a preliminary planarization of the insulating layer is obtained. By adjusting the etching parameters, the insulating layer is continuously removed by dry etching until the mask layer is exposed. The mask layer and buffer oxide layer are sequentially removed to expose a plurality of isolation structures with rounded surfaces.

Abstract: A process for forming insulator filled, shallow trench isolation (STI), regions in a semiconductor substrate, featuring a disposable polysilicon stop layer used to allow uniform insulator fill to be obtained, independent of shallow trench width, has been developed. The process features filling shallow trench shapes with a first high density plasma (HDP), deposited silicon oxide layer, followed by the deposition of the thin polysilicon stop layer, and a second HDP silicon oxide layer. After a planarizing chemical mechanical polishing procedure residual regions of the second HDP silicon oxide, still remaining in regions overlying the insulator filled shallow trench shapes, are selectively removed using the thin polysilicon layer as a stop layer. The polysilicon layer is then thermally oxidized. The thickness of the polysilicon layer can be varied such that the resultant polysilicon oxide layer serves to alleviate the possible oxide loss in the STI regions during subsequent clean processes.

Abstract: A method of manufacturing a semiconductor device including a plurality of active regions of different area and device isolation regions formed between the active regions, the method including the steps of: forming a first insulating film and a second insulating film in sequence on a semiconductor substrate; forming a plurality of openings through the first and second insulating films at desired positions; forming trenches in the semiconductor substrate in the openings to define active regions of different area and device isolation regions between the active regions; depositing a third insulating film on the semiconductor substrate so that the trenches are filled with the third insulating film; flattening the third insulating film by CMP until the second insulating film is exposed in the active regions; and removing the third insulating film remaining in the active regions because of a difference in polishing rate derived from variation in deposit density in the third insulating film and simultaneously reducin

Abstract: Trench isolation regions of different depths are formed through a simple manufacturing process, and reliability of a semiconductor device is increased. Trenches (103a, 103b) of different widths are formed on a semiconductor substrate (101) on which an underlying film (104) such as a silicon oxide film and a mask material (105) such as a silicon nitride film are formed. Then, an insulating film such as a silicon oxide film is deposited over the entire surface to such a degree that the narrower trench (103a) is filled up. At this time, the wider trench (103b) has an unfilled space in its central portion. a The surface of the substrate (101) is then vertically etched back until it is exposed in the trench 103b. With insulating films (106a, 106b) in the trenches (103a, 103b) as a mask, the surface of the substrate (101) is anisotropically etched vertically to form a deeper bottom (103c) in the trench (103b).

Abstract: A trenched-isolated semiconductor structure is created by a process that entails forming a patterned trench (54) along an upper surface of a semiconductor body (40). A dielectric layer (56) is provided over the upper semiconductor surface. The dielectric layer is covered with a smoothening layer (60) whose upper surface is smoother than the upper surface of the dielectric layer. The smoothening layer is removed starting from its upper surface. During the removal of the smoothening layer, upward-protruding material of the dielectric layer progressively becomes exposed and is also removed. As a result, the remainder of dielectric layer has a smoother upper surface than the initial upper surface of the dielectric layer.

Abstract: A method for forming shallow trench isolation in an integrated circuit is introduced. Firstly, the first silicon oxide layer and a silicon nitride layer are formed subsequently on the silicon substrate. Then lithography and etching are used to open a shallow trench. Then thermal oxidation is performed. The following step is to form the shallow trench isolation by forming the second silicon oxide with high density plasma enhanced chemical vapor deposition. Then an organic spin-on-glass is coated and low temperature baking is performed. After that, partial etching back is performed to remove spin-on-glass outside the shallow trench. This etching recipe has high selectivity between the second silicon oxide layer to spin-on-glass. Then curing at temperature above 800° C. and etching back are performed with silicon nitride as end point.

Abstract: A process for device fabrication, including coating a wafer with a layer including SiO2, SiNx, and a first resist, defining shallow trench isolation and alignment patterns in the first resist, transferring the first resist pattern into the SiO2 and SiNx, removing the first resist, etching trenches to a depth suitable for shallow trench isolation, coating the wafer with a second photoresist, defining open areas around alignment-marks, etching alignment mark trenches to a depth greater than the trench depth, suitable for alignment mark detection, removing the second resist and the SiNx, depositing SiO2 to fill the trenches for shallow trench isolation and partially fill the alignment mark trenches for alignment mark detection; and performing chemical mechanical polishing, leaving shallow trench isolation features and topographical alignment marks.

Abstract: A local oxidation of silicon (LOCOS) process directed to forming differential field oxide thickness on a single wafer with minimized process steps and optimized planarity. When patterning the masking layer, at least two window widths are formed in the masking layer, exposing the underlying substrate and pad oxide. When one of the window widths is sufficiently small, oxidation of the substrate will be inhibited causing reduced growth and thus a reduced field oxide thickness in that window as compared to other larger windows formed in the same masking layer, creating differential field oxide thicknesses in one growth step. To optimize planarity, prior to oxidation variable depth trenches are formed in alignment with the windows so that the resulting field oxide regions are substantially planar with the substantial surface.

Abstract: A plurality of trenches are formed in a semiconductor substrate, and an insulating film is formed over the plurality of trenches and the semiconductor substrate. A resist layer is then formed over the insulating film. The resist layer is then patterned such that remaining portions of the resist layer extend over first trenches of at least a given width and such that removed portions of the resist layer extend over second trenches of less then the given width. The insulating film is then etched using the remaining portions of the resist layer as a mask to expose the second trenches. The remaining portions of the resist layer are then removed to expose portions of the insulating film protruding above the first trenches. The exposed portions of the insulating film protruding above the first trenches is then chemical mechanical polished.

Abstract: A method of forming an trench isolation region uses discrete chemical mechanical polishing processes. Polishing stop patterns are formed on a semiconductor substrate and trenches are formed in the semiconductor substrate adjacent the polishing stop patterns. Then the polishing stop patterns are covered by and the trenches are filled with insulating material. A first chemical mechanical polishing process uses a non-ceria series slurry to partially planarize the insulating layer. Next, a second chemical mechanical polishing process uses a ceria-based slurry to planarize the insulating layer until the polishing stop patterns are exposed. The second chemical mechanical polishing process has a high polishing selectivity with respect to the material of the polishing stop patterns and the insulating material.

Abstract: There is provided a method for forming a Shallow Trench Isolation (STI) easy to suppress an occurrence of the debot even when the micro-scratch is present. A silicon oxide film made of an organic Spin-On-Glass (SOG) film is formed on a surface of a silicon oxide film in which a micro-scratch is generated by Chemical Mechanical Polishing (CMP). Such anisotropic etching is conducted that an etching rate for a silicon oxide film may be equal to that for the silicon nitride film, to remove the silicon nitride film and then remove by wet etching a pad oxide film, to nevertheless prevent a debot from occurring.

Abstract: In the fabrication of an integrated circuit, particularly an integrated circuit for radio frequency applications, a method for forming shallow and deep trenches for isolation of semiconductor devices comprised in said circuit, comprising providing a semiconductor substrate; optionally forming a first dielectric layer on said substrate; forming at least one shallow trench by using a first mask, said shallow trench extending into said substrate; forming a second dielectric layer of a predetermined thickness on the structure obtained subsequent to the step of forming at least one shallow trench; forming at least one opening in said second dielectric layer by using a second mask with an edge of said second mask aligned to an edge of said shallow trench with a maximum misalignment of half the predetermined thickness, said opening extending within the shallow trench to the bottom thereof, whereby a spacer of a width equal to the predetermined thickness is formed in said shallow trench and along said edge thereof; a

Abstract: A method of making an isolation trench structure in a semiconductor substrate is disclosed. A first layer is formed on a semiconductor substrate. The first layer is subsequently patterned to form islands to protect active areas in the semiconductor substrate. A second layer is conformally formed over the islands and the remaining portions of the substrate. The second layer is then anisotropically etched to form spacers on sidewalls of the islands. The substrate is subjected to a thermal oxidation process, thereby forming thermal oxide masks at positions which are not covered with the islands and the spacers. Thereafter, the sidewall spacers are selectively removed to expose the substrate between the islands and the oxide masks. Then, isolation trenches are etched through the exposed substrate using the islands and the oxide masks as etch masks. The isolation regions made according to the present invention have the widths beyond lithography limit.

Abstract: A semiconductor device and a method for constructing a semiconductor device is disclosed. A deep trench isolation structure (108) is formed proximate a surface of a semiconductor substrate (106). A deep trench plug (122) layer is deposited within the deep trench isolation structure (108). A shallow trench isolation structure (130) is formed where the deep trench isolation structure (108) meets the surface of the semiconductor substrate (106). A shallow trench plug layer (133) is deposited within the shallow trench isolation structure (130).

Abstract: Disclosed is a method of providing variant fills in a semiconductor substrate having a plurality of trenches by providing a semiconductor substrate with a first set of trenches and a second set of trenches, filling all the trenches with a first fill material, masking the second set of trenches in a manner effective in resisting an etching of said first fill material, etching the first fill material in the first set of trenches to a depth effective in permitting the first set of trenches to be plugged, plugging the first set of trenches with a material resistant to an etching of the first fill material, etching the first fill material from the second set of trenches; and then filling the second set of trenches with a second fill material. The process may be generalized to more than two fill materials.

Abstract: A method of forming a shallow trench isolation layer in a semiconductor device is provided, wherein a first trench and a second trench are formed in an area selected from a semiconductor substrate and a sidewall oxide layer, an anti-oxidation liner, and a mask layer are formed on the semiconductor substrate including the inner surfaces of the first and second trenches, in the same order. Using photoresist lithography, the mask layer and the anti-oxidation layer are etched in the second trench. An isolation layer is formed in the first and second trenches by depositing and then chemically and mechanically polishing the dielectric material and the layers underneath until the semiconductor substrate surface is exposed. The first trench provides isolation between N-FETs, an N-FET and a P-FET, an N-FET and other circuit devices, a P-FET and other circuit devices, and other circuit devices and the second trench provides isolation between P-FETs.

Abstract: A transistor structure is provided for ESD protection in an integrated circuit device. A semiconductor substrate has source and drain diffusion regions and respective source and drain wells under the source and drain diffusion regions. A shallow trench isolation formed over the semiconductor substrate and into the semiconductor substrate separates the source and drain diffusion regions and a portion of the source and drain wells. Source and drain contact structures respectively formed on the shallow trench isolation over the source and drain diffusion regions and extend through the shallow trench isolation to contact the source and drain diffusion regions. An ion implantation is performed through the contact openings into the bottoms of the source and drain wells to control the device trigger voltage and position the discharge current far away from the surface, which increases the device ESD performance significantly.

Abstract: A dummy active region is formed in which abrading processes are averaged. A semiconductor device is characterized in that an active region for forming an actual device, a device separation region being formed by a trench, and a dummy active region formed substantially in a rectangular shape are included, and the length of the short side of the dummy active region is less than 1 &mgr;m.

Abstract: A method of manufacturing a semiconductor device including a plurality of active regions of different area and device isolation regions formed between the active regions, the method including the steps of: forming a first insulating film and a second insulating film in sequence on a semiconductor substrate; forming a plurality of openings through the first and second insulating films at desired positions; forming trenches in the semiconductor substrate in the openings to define active regions of different area and device isolation regions between the active regions; depositing a third insulating film on the semiconductor substrate so that the trenches are filled with the third insulating film; flattening the third insulating film by CMP until the second insulating film is exposed in the active regions; and removing the third insulating film remaining in the active regions because of a difference in polishing rate derived from variation in deposit density in the third insulating film and simultaneously reducin

Abstract: A process for fabricating silicon oxide filled, shallow trench isolation (STI), regions, in a semiconductor substrate, featuring the use of a disposable boro-phosphosilicate glass (BPSG), layer, used for planarization of various width, silicon oxide filled, STI regions, has been developed. After completely filling all STI shapes with a high density plasma (HDP), silicon oxide layer, resulting in a non-planar, HDP silicon oxide top surface topography, a BPSG layer is deposited. An anneal procedure is then performed resulting in a planar top surface topography of the reflowed BPSG layer. A chemical mechanical polishing procedure is next employed to remove the planar, reflowed BPSG layer, and portions of the underlying HDP silicon oxide, from the top surface of a silicon nitride stop layer, resulting in a planar top surface topography for all silicon oxide filled, insulator regions.

Abstract: In order to isolate a plurality of MOS and bipolar devices provided on the same chip, a plurality of first and second trenches are provided on a semiconductor substrate. Each of the first trenches is filled with silicon oxide containing no impurity and is used to isolate the MOS devices. On the other hand, the second trenches are formed within the first trenches. Each second trench is filled silicon oxide containing phosphorous and boron and is used to isolate the bipolar devices. The inner surface of each second trench is coated with a silicon nitride film for preventing boron (or phosphorous) from being diffused into the surrounding region.

Abstract: The present invention provides a process for fabricating semiconductor device comprising the steps of: forming an etching-stop layer on a semiconductor substrate; patterning the etching-stop layer so that the etching-stop layer remains in a region to be an active region and is removed from a region to be a device isolation region, followed by forming a trench in the region to be the device isolation region; depositing on the semiconductor substrate an insulating film having a thickness greater than or equal to the depth of the trench; forming a resist pattern having an opening above the etching-stop layer above the active region adjacent to a device isolation region whose width is greater than or equal to a predetermined value, followed by etching the insulating film using the resist pattern as a mask; and polishing the insulating film existing on the resulting semiconductor substrate for flattening after removing the resist pattern.

Abstract: A method for forming shallow trench isolation is disclosed. A pad oxide layer and a mask layer are sequentially formed on a substrate. Afterwards, an opening is formed through the mask layer and the pad oxide layer such that regions of the substrate are exposed. Thereafter, the exposed regions are etched to form trenches inside said substrate. Next, nitrogen ions are implanted into the sidewall of the trenches to form a silicon nitride layer, and then a siliconoxynitride layer is formed inside the sidewall of the trenches. Subsequently, a silicon oxide layer is formed on the siliconoxynitride layer and on the mask layer. The excess portion of the silicon oxide layer over said mask layer is removed to expose the mask layer, and then the mask layer is removed away. Finally, the pad oxide layer is removed by using hydrofluoric acid (HF).

Abstract: A multiple dielectric device and its method of manufacture overlaying a semiconductor material, comprising a substrate, an opening relative to the substrate, the opening having an aspect ratio greater than about two, a first dielectric layer in the opening, wherein a portion of the opening not filled with the first dielectric layer has an aspect ratio of not greater than about two, and a second dielectric layer over said first dielectric layer. The deposition rates of the first and second dielectric layers may be achieved through changes in process settings, such as temperature, reactor chamber pressure, dopant concentration, flow rate, and a spacing between the shower head and the assembly. The dielectric layer of present invention provides a first layer dielectric having a low deposition rate as a first step, and an efficiently formed second dielectric layer as a second completing step.

Abstract: A plurality of chips each having two or more alignment holes for transmitting a laser beam are stacked. The laser beam is irradiated onto the uppermost or lowermost one of the stacked chips. A photodetector detects the laser beam output from the stacked chips through the alignment holes in these chips. The positions of the chips are so controlled that the amount of the light detected by this photodetector is a maximum.

Abstract: A method of forming a T-shaped isolation layer, a method of forming an elevated salicide source/drain region using the same, and a semiconductor device having the T-shaped isolation layer are provided. In the method of forming the T-shaped isolation layer, an isolation layer having a narrow trench region in the lower portion thereof and a wide trench region in the upper portion thereof is formed on a semiconductor substrate. Also, in the method of forming the elevated salicide source/drain region, the method of forming the T-shaped isolation layer is used. In particular, conductive impurities can also be implanted into the lower portion of the wide trench region which constitutes the head of the T-shaped isolation layer and is extended to both sides from the upper end of the narrow trench region by controlling the depth of the wide trench region in an ion implantation step for forming the source/drain region.

Abstract: A method for forming a dielectric zone in a region of a semiconductor substrate is described. A first trench and a second trench are formed in the region of the semiconductor substrate resulting in a web being formed between the first trench and the second trench. Afterward, a first dielectric layer is deposited in the first trench and the second trench. The web is subsequently removed, a third trench thereby being produced in the semiconductor substrate. Afterwards, a second dielectric layer is formed in the third trench. The first dielectric layer and the second dielectric layer together form a dielectric zone in the semiconductor substrate, on which it is advantageously possible to dispose components with substrate decoupling.

Abstract: An insulated trench isolation structure with large and small trenches of differing widths is formed in a semiconductor substrate with improved planarity using a simplified reverse source/drain planarization mask. Embodiments include forming large trenches and refilling them with an insulating material which also covers the substrate surface, masking the areas above the large trenches, etching to remove substantially all of the insulating material on the substrate surface and polishing to planarize the insulating material above the large trenches. Small trenches and peripheral trenches surrounding the large trenches are then formed, refilled with insulating material, and planarized. Since the large trenches are formed prior to and separately from the small trenches, etching can be carried out after the formation of a relatively simple planarization mask over only the large trenches, and not the small trenches.

Abstract: A method for forming a high performance photodiode with tightly-controlled junction profile for CMOS image sensor with STI process. The following steps are performed: providing a substrate; forming a hard mask layer for defining a pattern on the substrate; etching the substrate on the surface of the substrate not covered by the hard mask layer to form a shallow trench; growing an oxide lining in the shallow trench by a thermal oxidation process; performing a first thermal annealing; defining an n-well region in the shallow trench; implanting the n-well region; performing a second thermal annealing; forming a silicon oxide layer on the substrate to fill in the shallow trench; removing a portion of the silicon oxide layer on the substrate such that the portion in the shallow trench remains; removing the hard mask layer; and forming a transistor on the substrate, wherein the transistor comprises a gate structure, a source region, and a drain region.

Abstract: During formation of shallow-trench isolation (STI) structures during semiconductor processing, an additional oxide-reduction etching step is performed prior to chemical-mechanical processing. In one implementation wet-etching and/or sputter etch-back (SEB) is performed prior to applying a reverse-tone mask. In another implementation a wet etching step is performed after the reverse-tone mask is stripped. One significant result of each of these steps is a reduction in the height and width of at least some of the oxide horns that remain after the reverse-tone mask is stripped. As such, the oxide structures that need to be planarized during CMP will be smaller than those of the prior art. Moreover, since the resulting oxide structures that need to be planarized by CMP processing are smaller, the oxide layer can be initially applied at a smaller thickness than that of the prior art.

Abstract: The present invention is an isolation trench with an insulator, and a method of forming the same using self-aligned processing techniques. The method is implemented with a single mask. A shallow trench is first formed with the mask. Subsequently, the deep trench is formed in self-alignment to the shallow trench. The shallow and deep trenches are filled with insulators. The deep trench diminishes the effects of undesirable inter-device affects, such as leakage current and latch-up. As a result, substrates can be fabricated with high device density.

Abstract: A method of chemical-mechanical polishing for forming a shallow trench isolation is disclosed. A substrate having a number of active regions, including a number of relative large active regions and a number of relative small active regions, is provided. The method comprises the following steps. A silicon nitride layer on the substrate is first formed. A number of shallow trenches are formed between the active regions. An oxide layer is formed over the substrate, so that the shallow trenches are filled with the oxide layer. A partial reverse active mask is formed on the oxide layer. The partial rever active mask has an opening at a central part of each relative large active region. The opening exposes a portion of the oxide layer. The opening has at least a dummy pattern. The oxide layer on the central part of each large active region is removed to expose the silicon nitride layer. The partial reverse active mask is removed. The oxide layer is planarized to expose the silicon nitride layer.

Abstract: A method of forming a desired rectangular pattern in a material layer above a substrate. The method includes providing a substrate having a material layer thereon. A hard mask layer is next formed over the material layer, and then a first photoresist layer having a first pattern therein is formed over the hard mask layer. A first etching operation is carried out while using the first photoresist layer as an etching mask to remove a portion of the hard mask layer, thereby transferring the pattern in the first photoresist layer to the hard mask layer. The first photoresist layer is removed. A second photoresist layer having a second pattern therein is formed over the substrate. A second etching operation is carried out to remove a portion of the material layer while using the patterned second photoresist layer and the hard mask layer as an etching mask. Hence, the desired rectangular pattern is formed in the material layer.

Abstract: A semiconductor storage unit and a method of manufacturing the same are provided. In the semiconductor storage unit, the formation of a gate electrode within a semiconductor substrate decreases the occurrence of a short circuit between conductive layers, provides an excellent electric connection in a connection hole between the semiconductor substrate and a conductive layers, and also reduces the number of manufacturing processes. In a semiconductor substrate, unit memory cells and are formed by providing a gate electrode in a region where a second opening is formed in a first opening, a first impurity-diffusion layer, a second impurity-diffusion layer, a third impurity-diffusion layer, a bit line, a charge-storage electrode, a capacity insulating film, and a plate electrode. Regions where the second opening is not formed are isolation regions and between memory cells.

Abstract: Obtained is a method of manufacturing a semiconductor device which can take a body contact while electrically isolating an NMOS transistor and a PMOS transistor from each other through a complete isolation. First of all, element isolating films (7a to 7c) of a partial isolation type are formed in a first main surface of a silicon layer (3). Next, a PMOS transistor, an NMOS transistor, a multilayer wiring structure, a spiral inductor (20) and a pad (22) are formed, respectively. Then, a support substrate (23) is formed over the whole surface. Thereafter, a silicon substrate (1) and a BOX layer (2) are removed to expose a second main surface of the silicon layer (3). Subsequently, element isolating films (27a to 27d) connected to the element isolating films (7a and 7b) are formed on the second main surface side of the silicon layer (3). Consequently, a complete isolation can be obtained.