Abstract: A method of manufacturing an SOI (silicon on insulator) wafer includes the step of selective anisotropic etching to form, in the substrate, trenches which extend to a predetermined depth from a major surface of the substrate and between which pillar portions of the substrate are defined. The method further includes the step of selective isotropic etching to enlarge the trenches, starting at a predetermined distance from the major surface, thus reducing the thicknesses of the pillar portions of the substrate between adjacent trenches. Also, the method includes the steps of selective oxidation to convert the pillar portions of reduced thickness of the substrate into silicon dioxide and to fill the trenches with silicon dioxide, starting substantially from the predetermined distance, and epitaxial growth of a silicon layer on the major surface of the substrate.

Abstract: A method of forming a vertical transistor. A pad layer is formed over a semiconductor substrate. A trough is formed through the pad layer and in the semiconductor substrate. A bit line is formed buried in the trough. The bit line is enclosed by a dielectric material. A strap is formed extending through the dielectric material to connect the bit line to the semiconductor substrate. The trough is filled above the bit line with a conductor. The conductor is cut along its longitudinal axis such that the conductor remains on one side of the trough. Wordline troughs are formed, substantially orthogonal to the bit line, above the semiconductor substrate. A portion of the conductor is removed under the wordline trough to separate the conductor into separate gate conductors. Wordlines are formed in the wordline trough connected to the separate gate conductors.

Abstract: A process for manufacturing a semiconductor device comprising the steps of: depositing a polish-stopper film on a semiconductor substrate, applying a photoresist on the polish-stopper film and removing the photoresist from a region for forming a device isolation region to form an opening; dry etching using the photoresist as an etching mask to form a trench of a predetermined depth in the semiconductor substrate; removing the photoresist; forming a first insulating film and a second insulating film in sequence to bury the trench, the second insulating film being capable of being etched by the same etching step as that for the first insulating film and having an etching rate greater than that of the first insulating film; polishing the first and second insulating films by CMP method until a surface of the polish-stopper film is exposed; removing the polish-stopper film; and removing the first and second insulating films projected from a surface of the semiconductor substrate by etching using the same etchant,

Abstract: A process for creating silicon isolation regions which utilizes silicon islands or pillars as sources of silicon for silicon dioxide (or silicon oxide) fields. These silicon oxide fields separate active areas within a device. By providing multiple sources of silicon for silicon oxide formation, the described invention minimizes the use of trench wall edges as silicon sources for silicon oxide growth. This reduction in stress helps to minimize encroachment and undergrowth or bird's beak formation. This process also leads to a reduced step height between the field oxide and active areas, thus providing a more planar wafer surface.

Abstract: In a method of fabricating a semiconductor device, a plurality of MOS devices are formed on a semiconductor substrate each with a source, a drain, and a gate electrode. A first insulating layer is formed on the semiconductor substrate with the MOS devices. A moat pattern is formed on the first insulating layer such that the portions of the first insulating layer placed at device isolation areas are exposed to the outside. Trenches are formed at the semiconductor substrate through etching the first insulating layer and the underlying semiconductor substrate using the moat pattern as a mask. The semiconductor substrate is partially etched by a predetermined depth. The trenches are filled up through forming a second insulating layer on the etched portions of the semiconductor substrate, and on the first insulating layer.

Abstract: The present invention provides a method of easily planarizing the uneven surface of a substrate having an uneven surface. This method comprises the steps of forming a coating film containing spherical fine particles on a surface of a smooth substrate; sticking the surface of the smooth substrate provided with the coating film containing spherical fine particles to the uneven surface of a substrate having an uneven surface; and transferring the coating film containing spherical fine particles to the uneven surface of the substrate so that the uneven surface is planarized.

Abstract: A method for forming a dual oxide layer on a silicon substrate provides that layer having varying thicknesses by using a damage layer formed on the silicon substrate, or a silicon nitride layer deposited on the silicon substrate. The damage layer is formed on the silicon substrate by dry etching a designated part of the silicon substrate, and the dual oxide layer is formed by using the properties of SiO2 by which the oxide layer growth speed on the damage layer is slower than that on the silicon substrate. A pattern of the damage layer is defined by photolithography, and the damage layer having a depth of about 20 to 5,000 Å is formed using CF4, CHF3, or Ar gas at a pressure of 900 mTorr or less, or using Cl2 or HBr. In the preoxidation cleaning step, a solution containing NH4F, HF, and H2O, a standard solution containing NH4OH, H2O2, and H2O, and/or HF are used.

Abstract: A method of forming a circuitry isolation region within a semiconductive wafer comprises defining active area and isolation area over a semiconductive wafer. Semiconductive wafer material within the isolation area is wet etched using an etch chemistry which forms an isolation trench proximate the active area region having lowestmost corners within the trench which are rounded. Electrically insulating material is formed within the trench over the previously formed round corners. In accordance with another aspect, the semiconductive wafer material within the isolation area is etched using an etch chemistry which is substantially selective relative to semiconductive wafer material within the active area to form an isolation trench proximate the active area region. In accordance with still another aspect, a method of forming a circuitry isolation region within a semiconductive wafer comprises masking an active area region over a semiconductive wafer.

Abstract: A process for producing a semiconductor device comprising plural element forming regions having different element region widths W and element isolating regions between said element forming regions,

Abstract: A method of forming a shallow trench isolation structure is provided. A substrate having a pad oxide layer and a first insulating layer formed thereon is provided. A first trench with a small size and a second trench with a large size are formed in the substrate. A first dielectric layer and a second insulating layer are formed on the substrate sequentially. The second insulating layer is defined to form a dummy pattern to occupy a part of the second trench. A second dielectric layer is formed on the first dielectric layer and to fill into the remaining space of the second trench. A CMP process is performed to complete the shallow trench isolation trench structure.

Abstract: A method for forming a trench structure in a silicon substrate, which trench structure serves for electrically insulating a first region of the substrate from a second substrate region. The method proceeds from a growth of a thermal oxide layer on the substrate surface and an application and patterning of a mask layer over the thermal oxide layer. A trench of predetermined depth is subsequently etched into the silicon substrate through the patterned mask layer. The trench is filled by a deposition of a conformal covering oxide layer on the substrate with an essentially uniform thickness that is sufficient for completely filling the trench. Afterwards, a polysilicon layer is deposited on the covering oxide layer and a chemical mechanical planarization method is carried out with high selectivity S between the polysilicon material and the oxide material in order to obtain a flat surface.

Abstract: A method for forming an isolation layer in a semiconductor device, to avoid the occurrence of an angular formation phenomenon at the edge portions of the upper and lower portions of the trench during formation of a shallow trench isolation layer (STI), so that malfunction of the device and the deterioration of its performance due to a parasitic transistor and leakage current, can be prevented. Advantageously, silicon nitride films are formed at the side wall of the pad oxide film and the surface of trench silicon through a nitrogen (N+) plasma nitrification process, after a trench etching process, for formation of STI, so that the generation of a moat is inhibited and deterioration of the device is prevented.

Abstract: The present invention provides a process for fabricating a semiconductor device comprising the steps of: forming an etching-stop layer on a semiconductor substrate; patterning the etching-stop layer so that the etching-stop layer remains in a region to be an active region and is removed from a region to be a device isolation region, followed by forming a trench in the region to be the device isolation region; depositing on the semiconductor substrate an insulating film having a thickness greater than or equal to the depth of the trench; forming a resist pattern having an opening above the etching-stop layer above the active region adjacent to a device isolation region whose width is greater than or equal to a predetermined value, followed by etching the insulating film using the resist pattern as a mask; and polishing the insulating film existing on the resulting semiconductor substrate for flattening after removing the resist pattern.

Abstract: Within a method for fabricating a microelectronic device there is first provided a silicon substrate. There is then formed upon the silicon substrate a first series of structures having a comparatively narrow spacing which leaves exposed a first series of comparatively narrow portions of the silicon substrate, and where the first series of structures is separated from a second series of structures also formed upon the silicon substrate, the second series of structures having a comparatively wide spacing which leaves exposed a second series of comparatively wide portions of the silicon substrate. There is then masked one of the first series of comparatively narrow portions of the silicon substrate and the second series of comparatively wide portions of the silicon substrate.

Abstract: A process for forming a device isolation region comprising the steps of: forming a pad oxide film and a silicon nitride film on a semiconductor substrate; removing the pad oxide film and the silicon nitride film on a region for device isolation and forming a trench in the semiconductor substrate by etching using the remaining pad oxide film and silicon nitride film as an etching mask; forming a first oxide film at least on the bottom and sidewalls of the trench and below the pad oxide film under an end portion of the silicon nitride film using the silicon nitride film as a mask resistant to oxidization; forming a gap between the silicon nitride film and the semiconductor substrate by removing the first oxide film on the bottom and the sidewalls of the trench and the first oxide film and the pad oxide film below the end portion of the silicon nitride film by etching using the silicon nitride film as an etching mask; forming a second oxide film at least on the bottom and the sidewalls of the trench and in the g

Abstract: A method of manufacturing a semiconductor device having a microminiture trench isolation in which an insulating film is embedded by an HDP-CVD method comprising: a step of pre-planarization by conducting a dry etching selectively with respect to the insulating film laminated excessively on the surface of substrate, which is to be an active region, and a step of polishing by a CMP method in order to improve a surface planarity of the insulating film, wherein an etching mask used at the time of opening a trench opening portion has a multi-layer structure including a silicon nitride film and a polycrystal silicon film; the polycrystal silicon film is used as an etching stopper at the time of pre-planarization; and the silicon nitride film is used as an etching stopper at the time of polishing by a CMP method in order to remove simultaneously the excessive insulating film and the polycrystal silicon film to expose and a surface of the substrate, which is the active region, whereby the trench isolation having a sa

Abstract: A shallow trench isolation structure for a semiconductor device and the method for manufacturing the shallow trench isolation device within a semiconductor substrate. The shallow trench isolation structure is divot-free and includes un-annealed dielectric material as the trench fill material. The intersection of the structure and the semiconductor surface in which it is formed, is free of silicon nitride, but the isolation structure may include a silicon nitride liner which is within the trench and recessed below the semiconductor surface.

Abstract: An object of the present invention is to improve a margin for the formation of a trench device separation region at photolitho.

Abstract: Exemplary embodiments of the present invention disclose a semiconductor assembly having at least one isolation structure formed. The semiconductor assembly comprises: a first trench in a semiconductive substrate; a second trench extending the overall trench depth in the semiconductive substrate by being aligned to the first trench; and a planarized insulation material substantially filling the first and second trenches. The isolation structure separates a non-continuous surface of a conductive region.

Abstract: A trench isolation structure is fabricated using high pressure and low temperature. A substrate is provided within which a trench is formed. The trench walls are annealed in nitrogen at a pressure above atmospheric pressure to remove silicon damage caused by plasma etching. The exposed side walls of the trench are oxidized at a pressure above atmospheric pressure to form an oxidized layer. The trench is filled with an oxide. Optionally, re-oxidation densification may be performed at a pressure above atmospheric pressure and a temperature in the range of about 600° C. to about 800° C.

Abstract: Trench isolation regions of different depths are formed through a simple manufacturing process, and reliability of a semiconductor device is increased. Trenches (103a, 103b) of different widths are formed on a semiconductor substrate (101) on which an underlying film (104) such as a silicon oxide film and a mask material (105) such as a silicon nitride film are formed. Then, an insulating film such as a silicon oxide film is deposited over the entire surface to such a degree that the narrower trench (103a) is filled up. At this time, the wider trench (103b) has an unfilled space in its central portion. The surface of the substrate (101) is then vertically etched back until it is exposed in the trench 103b. With insulating films (106a, 106b) in the trenches (103a, 103b) as a mask, the surface of the substrate (101) is anisotropically etched vertically to form a deeper bottom (103c) in the trench (103b).

Abstract: A process for creating silicon isolation regions which utilizes silicon islands or pillars as sources of silicon for silicon dioxide (or silicon oxide) fields. These silicon oxide fields separate active areas within a device. By providing multiple sources of silicon for silicon oxide formation, the described invention minimizes the use of trench wall edges as silicon sources for silicon oxide growth. This reduction in stress helps to minimize encroachment and undergrowth or bird's beak formation. This process also leads to a reduced step height between the field oxide and active areas, thus providing a more planar wafer surface.

Abstract: An isolation trench (60) comprising a trench (20) formed in a semiconductor layer (12). A barrier layer (22) may be formed along the trench (20). A layer (50) of an insulation material may be formed over the barrier layer (22). A high density layer (55) of the insulation material may be formed in the trench (20) over the layer (50).

Abstract: A resist pattern (51) is formed only on buried silicon oxide films (2) on the whole surface of an alignment mark area (11A) and a trench (10C). With the resist pattern (51), preetching is performed by dry etching, to remove the silicon oxide film (2) on the whole of a memory cell area (11B) and part of a peripheral circuit area (11C) by a predetermined thickness. After removing the resist pattern (51), a silicon oxide film (3) and a silicon nitride film (4) are removed by CMP polishing, to provide a height difference between the highest portion and the lowest portion of the silicon oxide film (2A) which serves as an alignment mark. Thus, a semiconductor device with trench isolation structure which achieves a highly accurate alignment without deterioration of device performance and a method for manufacturing the semiconductor device can be provided.

Abstract: In accordance with an aspect of the invention, a method of forming a trench isolation region includes forming a trench within a substrate. A silanol layer is formed to partially fill the trench and then converted, at least some of the silanol, to a compound including at least one of SiOn and RSiOn, where R includes an organic group. An electrically insulative material is formed over the converted silanol to fill the trench. In another aspect of the invention, a method of forming a trench isolation region includes forming a trench within a substrate. A first layer of at least one of Si(OH)x and (CH3)ySi(OH)4−y is formed to partially fill the trench. At least some of the Si(OH)x if present is converted to SiO2 and at least some of (CH3)ySi(OH)4−y if present is converted to (CH3)xSiO2−x. Next, a layer of an electrically insulative material is formed to fill the trench.

Abstract: A method for forming isolation trenches for a semiconductor device forms, in a substrate, a plurality of trenches having different widths including widths above a threshold size and widths below a threshold size. The plurality of trenches have a same first depth. A masking layer is deposited in the plurality of trenches, the masking layer has a thickness sufficient to both line the trenches with the widths above the threshold size and completely fill the trenches with the widths below the threshold size. A portion of the substrate is exposed at a bottom of the trenches with the widths above the threshold size by etching the masking layer. The plurality of trenches is etched to extend the trenches with the widths above the threshold size to different depths.

Abstract: A method and structure for improving the latch-up characteristic of semiconductor devices is provided. A dual depth STI is used to isolate the wells from each other. The trench has a first substantially horizontal surface at a first depth and a second substantially horizontal surface at a second depth which is deeper than the first depth. The n- and p-wells are formed on either side of the trench. A highly doped region is formed in the substrate underneath the second substantially horizontal surface of the trench. The highly doped region abuts both the first and the second wells and extends the isolation of the trench.

Abstract: In accordance with the present invention, a method for expanding trenches includes the steps of forming a trench in a substrate, preparing surfaces within the trench by etching the surfaces with a wet etchant to provide a hydrogen terminated silicon surface and anisotropically wet etching the trench to expand the trench.

Abstract: A method for isolating a semiconductor device is disclosed. The method includes the steps of forming a buffer film on a semiconductor substrate and an oxide prevention film on the buffer film, etching the buffer,film and the oxide prevention film of a device isolation region, etching the substrate using the oxide prevention film as a mask and forming a trench, forming an oxidizable film on the surface of the trench, forming an insulation film filled into the trench by oxidizing the oxidizable film, and removing the buffer film and the oxide prevention film, for thereby enhancing the isolation characteristic of the device.

Abstract: A method is provided for planarizing a structure such as a shallow trench isolation region on a semiconductor substrate. A semiconductor substrate is provided having raised and lowered regions with substantially vertical and horizontal surfaces. The lowered regions may correspond to trench regions. Filler material such as non-conformal high density plasma oxide may be deposited over the horizontal surfaces to at least a thickness equal to a predetermined height so as to provide raised and lowered regions of the filler material. The raised regions of the filler material may then be selectively removed without removing the filler material in the lowered regions.

Abstract: Disclosed are improved and simplified methods of forming trench isolation regions. A photoresist pattern having an opening therein is directly formed on a bare semiconductor substrate. The bare semiconductor substrate is etched through the opening in the photoresist pattern to form a trench in the substrate. The photoresist pattern is then isotropically etched to enlarge the size of the opening. A spin-on material layer is coated overlying the substrate surface to fill the trench and the enlarged opening, and then etched back until the photoresist pattern is exposed. After removing the photoresist pattern, the spin-on material layer is cured to form a trench isolation region which are less susceptible to edge defects.

Abstract: A method of fabricating a shallow trench isolation. A trench is formed in a substrate. An insulation plug is formed to fill the trench. The trench has an exposed upper portion above the substrate. A silicon spacer is formed on a side wall of the exposed upper portion. The silicon spacer is oxidized into a silicon oxide spacer.

Abstract: An improved and new process for fabricating MOSFET's in shallow trench isolation (STI), with sub-quarter micron ground rules, includes a passivating trench liner of silicon nitride. The silicon nitride passivating liner is utilized in the formation of borderless or “unframed” electrical contacts, without reducing the poly to poly spacing. Borderless contacts are formed, wherein contact openings are etched in an interlevel dielectric (ILD) layer over both an active region (P-N junction) and an inactive trench isolation region. During the contact hole opening, a selective etch process is utilized which etches the ILD layer, while the protecting passivating silicon nitride liner remains intact protecting the P-N junction at the edge of trench region. Subsequent processing of conductive tungsten metal plugs are prevented from shorting by the passivating trench liner.

Abstract: A semiconductor device comprising an integrated circuit and an information unit, said unit being electrically separate from said integrated circuit; an integrated antenna electrically connected with said unit; and an electronic data bank integral with said unit. A method of fabricating an information unit into an integrated circuit chip comprising forming an integrated circuit into a semiconductor substrate using a plurality of process steps; concurrently forming an information unit using a selection of said process steps so that said unit becomes integrated into said chip but remains electrically separate from said integrated circuit; concurrently forming an antenna using a selection of said process steps so that said antenna becomes integrated into said chip and electrically connected to said information unit; providing a data bank within said information unit; and encoding electronic data permanently into said data bank.

Abstract: A method for forming planarized isolation using a nitride hard mask and two CMP steps is described. A first nitride layer is deposited over a pad oxide layer on the surface of a semiconductor substrate. The first nitride and pad oxide layers are etched through where they are not covered by a mask to provide at least one wide opening and at least one narrow opening where the surface of the substrate is exposed. Trenches are etched into the substrate where it is exposed. An oxide layer is deposited overlying the first nitride layer and within the trenches completely filling the narrow trench wherein a trough is formed over the wide trench. A second nitride layer is deposited over the oxide layer. The second nitride layer is polished away with a polish stop at the oxide layer whereby the second nitride layer is removed except: where it lies within the trough.

Abstract: A method for planarizing a layer of photoresist on a substrate. The layer of photoresist is exposed to wavelengths of radiation that the photoresist is sensitive to. The radiation is directed at the layer of photoresist at an oblique angle with respect to a major dimension of the layer of photoresist. The photoresist is developed.

Abstract: A chemical mechanical polishing (CMP) method using a double polishing stopper by which it is possible to prevent a dishing phenomenon and a variation in the thickness of a polishing stopper, including the steps of stacking polishing stoppers to form the double polishing stopper on a semiconductor substrate, forming a trench, stacking an isolation layer, performing a first CMP process using a second polishing stopper, removing the second polishing stopper, and performing a second CMP process using a first polishing stopper. It is possible to remove the second polishing stopper by additionally interposing an etching stopper between the polishing stoppers which form the double polishing stopper.

Abstract: A first trench having a first width and a second trench having a width which is smaller than the first width are formed on a major surface of a semiconductor substrate. A first isolation insulator having an outer side wall is formed to fill up the first trench. A second isolation insulator having an outer side wall is formed to fill up the second trench. The first isolation insulator includes a side wall insulator film forming the outer side wall and an internal insulator film enclosed with the side wall insulator film for filling up the first trench. The second isolation insulator includes an internal insulator film forming the outer side wall for filling up the second trench. Thus obtained are a highly reliable semiconductor device comprising isolation insulators having different widths and a method of fabricating the same.

Abstract: The present invention provides a process for manufacturing a semiconductor structure comprising the steps of: (a) forming a first SiN film on a semiconductor substrate; (b) patterning the first SiN film, etching the resulting substrate using the first SiN film as a mask to form a plurality of first trenches and at least one second trench, so as to form a first islands group and at least one second island-like region; (c) depositing a SiO2 film to fill the first and second trenches with the SiO2 film; (d) forming a second SiN film over the resulting surface; (e) polishing the second SiN film and the SiO2 film by a CMP method using a first slurry until the surface of the first SiN film on the second island-like region is exposed; (f) polishing the second SiN film and the SiO2 film by a CMP method using a second slurry until the surface of the first SiN film on the first island-like region is exposed; (g) etching a predetermined amount of the SiO2 film; and (h) removing the second and first SiN films.

Abstract: The present invention proposes a method for forming shallow trench isolation. Isolation trenches are firstly formed on a silicon substrate. High-density plasma oxide layer is used to fill the trenches. A layer of poly-silicon and a thin oxide layer are then deposited on the high-density plasma oxide layer. Selective poly-silicon chemical mechanical polishing is then used to form a self-align reverse poly mask on the surface of the shallow trenches filled with the high-density plasma oxide layer. The high-density plasma oxide layer is locally etched. Chemical mechanical polishing is then used to perform a planarization process on the surface. In the present invention, photolithography is not necessary in the planarization process of high-density plasma oxide layer. Manufacture cost is thus lower.

Abstract: A method for fabricating a silicon on insulator wafer, comprising the steps of: preparing a base substrate and a semiconductor substrate; forming a first insulating layer on the base substrate; forming first isolation layers of trench types having a first depth in one surface of the semiconductor substrate; forming second isolation layers of trench types having a second depth between the first isolation layers, the second depth being deeper than the first depth; forming a second insulating layer over one surface of the semiconductor rate including the first and second isolation layers; bonding the base substrate and the semiconductor substrate to contact the first insulating layer with the second insulating layer; firstly polishing another surface of the semiconductor substrate to expose the second isolation layers using the second isolation layers as polishing stoppers; etching the second isolation layers to have the same depth as the first isolation layers; and secondly polishing the first polished another

Abstract: A method for forming a trench isolation region within a trench within a silicon substrate. There is first provided a silicon substrate having a trench formed therein. There is then formed over the silicon substrate and filling the trench a silicon oxide trench fill layer. There is then thermally oxidized the silicon substrate and the silicon oxide trench fill layer within a thermal oxidation atmosphere to form a densified silicon oxide trench fill layer upon a silicon oxide trench liner layer within an oxidized trench within an oxidized silicon substrate, where the silicon oxide trench liner layer is formed from oxidation of the silicon substrate when forming the oxidized silicon substrate.

Abstract: A method of forming flash memory. The method includes forming buried bit lines before the production of shallow trench isolation (STI) structures. The steps for producing the STI structures include forming a pad oxide layer and a silicon nitride layer. A plurality of openings that expose the pad oxide layer is formed in the silicon nitride layer. These openings are located directly above the buried bit lines. Silicon dioxide is deposited to form a silicon dioxide layer that fills these openings. The silicon dioxide layer is capable of preventing the buried bit lines from being cut into segments in subsequent trench-isolation operations.

Abstract: A method of minimizing mechanical stress generated during the trench-forming/trench-filling process steps in a standard shallow trench isolation (STI) process is provided. This is achieved by forming trenches with a more sloped and smoother profile, and/or limiting the trench depth to be less than 0.4 &mgr;m, and/or reducing or increasing the trench densification temperature, and/or performing the densification step after the chemical-mechanical polishing step. In addition, a furnace TEOS oxide film is used as the trench-filling material.

Abstract: A method of reducing a chemical mechanical polishing (CMP) dishing effect. A plurality of trenches are formed in the substrate, while a first insulating layer, such as silicon oxide layer is formed on the substrate to fill those trenches. A chemical reaction, such as nitridation reaction, is performed on the surface of the insulating layer to form a second insulating layer, which is harder than the first insulating layer. CMP is then performed.

Abstract: A process for producing a semiconductor device and an apparatus and a process for obtaining an optimum film thickness, the process for producing a semiconductor device comprising forming a film of a light reflecting material on a semiconductor substrate; coating a positive resist on the film of a light reflecting material; forming a resist pattern from the positive resist; and etching the film of a light reflecting material using the resist pattern as a mask, wherein simulation of light intensity is conducted by using optical constants of the semiconductor substrate, the film of a light reflecting material and the resist obtained by measuring the optical constants thereof, or when optical constants thereof are known, by using the known optical constants, with varying a film thickness of the film of a light reflecting material to plural values, so as to obtain a film thickness of the film of a light reflecting material that makes a light absorption energy at an interface between the film of a light reflecting

Abstract: In a method of fabricating electronic components of the type wherein trenches formed in a substrate are filled up with a filling material deposited by a deposition process achieving etching and deposition concurrently, the improvement which comprises portions of the filling material deposited on those portion of the substrate other than those corresponding to the trenches are leveled up to the same height by an additional deposition of the filling material, or alternatively by a full-surface etch back process. With this leveling of the deposited material, a subsequent polishing operation can be performed smoothly with high accuracy. During the polishing operation, the resistance between a conductive polish-stop layer on the substrate and a surface of a polishing member contacting the substrate is monitored to determine a polish end.

Abstract: A calibration standard comprises a supporting structure (1) of single crystal material with at least one pair of different kinds of structures consisting of a raised line (2) and a trench (3). These structures have the identical width in the range of about 500 nm. The single crystal material preferably is silicon with (110)-orientation.

Abstract: The method includes forming a pad oxide, a polysilicon layer over a substrate. Next, an oxide layer is formed over the polysilicon layer. An opening is formed in the oxide layer, the polysilicon layer, and the pad layer. A trench is formed by etching the substrate using the oxide layer as a mask. A sidewall structure is then formed on the opening. Next, an exposed portion of the substrate is etched by using the sidewall structure as a mask. The sidewall structure and the oxide layer are then removed. An oxide and an oxynitride layer are then formed on the aforesaid feature. A semiconductor layer is then formed over the oxynitride layer. A portion of the semiconductor layer is oxidized for forming an insulating layer. Finally, a refilling layer is formed over the insulating layer and the substrate is planarized for having a planar surface.

Abstract: In order to form an isolation structure in a substrate, a blocking layer (13, 14) is fabricated over the substrate (12), after which portions of the blocking layer and the substrate are removed at an isolation region (22). A dielectric layer (26) is then deposited over the blocking layer and the isolation region. Thereafter, a chemical-mechanical polishing process is carried out on the dielectric layer, so as to remove a substantial portion of the dielectric layer disposed above an upper surface of the blocking layer. A non-patterned etch is then carried out on the dielectric layer, in order to remove a remaining portion of the dielectric layer disposed above the upper surface of the blocking layer.