Abstract: A method of forming trench isolation within a semiconductor substrate includes forming a first isolation trench of a first open dimension within a semiconductor substrate. The first isolation trench has a base. A second isolation trench is formed into the semiconductor substrate through the base of the first isolation trench. The second isolation trench has a second open dimension along a line parallel with the first open dimension which is less than the first open dimension. Insulative isolation material is formed within the first and second isolation trenches. The insulative isolation material has a void therein extending from within the second isolation trench to the first isolation trench. Other aspects and implementations are contemplated.

Abstract: The present invention relates to a method of manufacturing a flash memory device. The method comprises the steps of sequentially depositing a pad oxide film and a pad nitride film on a semiconductor substrate, when trenches are formed by etching the pad nitride film, the pad oxide film and the substrate using a mask for forming a device isolation film, forming trenches having a different depth in a cell region and in a peripheral by controlling an etch angle and etch target depending on the width of the trench, depositing trench insulating films on the entire surfaces to bury the trenches with the trench insulating films, performing a chemical mechanical polishing process and a strip process for the trench insulating films to form the trench insulating film upper structures of which are protruded, forming a well region through an ion implantation process, and forming a tunnel oxide film, a floating gate, a dielectric film and a control gate.

Abstract: Grooves are defined in a substrate having device isolation regions by dry etching using silicon nitride films and side wall spacers as masks. Thereafter, the side wall spacers lying on side walls of the silicon nitride films are removed and the substrate is subjected to thermal oxidation, whereby the surface of the substrate at a peripheral portion of each active region is subjected to so-called round processing so as to have a sectional shape having a convex rounded shape.

Abstract: In a method of producing a trench insulation in a silicon substrate a first silicon-oxide layer is deposited on a front surface of a sequence of layers including the silicon substrate. Then the first silicon-oxide layer is structured so as to define a mask for a subsequent production of a trench. A trench is etched with a predetermined depth in the silicon substrate making use of the mask and filled with a silicon oxide. Then a first polysilicon layer is conformally deposited on the first silicon-oxide layer and on the oxide-filled trench. The first polysilicon layer is removed in such a way that a polysilicon cover remains on the oxide-filled trench, and the first silicon-oxide layer is removed.

Abstract: A method of forming a bottle-shaped trench in a semiconductor substrate. The method is suitable for formation of the capacitor of DRAM. First, the semiconductor substrate is selectively etched to form a trench, wherein the trench has a top portion and a bottom portion. A nitride film is then formed on the top portion of the trench. Next, the semiconductor substrate is etched through the bottom portion of the trench by a solution of hydrogen peroxide and hydrofluoric acid as the etchant to form a bottle-shaped trench followed by removal of the nitride film.

Abstract: A method for fabricating a shallow trench isolation structure includes forming a hard mask layer over a substrate. An ion bombardment step is further performed on the surface of the hard mask layer, followed by forming a patterned photoresist layer on the surface of the hard mask layer. Thereafter, the hard mask layer is patterned using the photoresist layer as an etching mask. An etching process is further performed to form a trench in the substrate. The photoresist layer is then removed, followed by filling an insulation layer in the trench. After this, the hard mask is removed to complete the fabrication of a shallow trench isolation region.

Abstract: A semiconductor device formed on a SOI substrate includes isolation trenches formed in a first region and reaching an insulation layer buried in the SOI substrate, and alignment marks formed in a second region and consisting of grooves extending into a support substrate.

Abstract: In fabricating a shallow trench isolation (STI), a silicon oxide layer, a silicon nitride layer and a moat pattern is sequentially deposited on a silicon substrate. Next, the silicon nitride layer and the silicon oxide layer is etched using the moat pattern as a mask to thereby partially expose the silicon substrate and then the moat pattern is removed. Ion implanting process is performed into the silicon substrate using the silicon nitride layer as a mask, adjusting a dose of an implanted ion and an implant energy, to thereby form an isolation region. And then, the isolation region to form a porous silicon and to form an air gap in the porous silicon is anodized, wherein a porosity of the porous silicon is determined by the dose of the implanted ion. Next, the porous silicon is oxidized through an oxidation process. Finally, the silicon nitride layer is removed.

Abstract: An improved method for producing a semiconductor device in which overpolishing is prevented at a chemical mechanical polishing time to eliminate the influence of peripheries on the object part. A plasma oxide film is formed on a semiconductor substrate so as to fill a recess and a trench. With the use of a resist film as a mask, the plasma oxide film is selectively etched to leave an overpolish-preventing support member in a neighborhood of the recess, which is a photo-related mark, for providing a support against overpolishing at a chemical mechanical polishing time. The surface of the semiconductor substrate is polished by chemical mechanical polishing. Thereafter, a nitride film and an oxide film are removed.

Abstract: The present invention enables the production of improved high-speed semiconductor devices. The present invention provides the higher speed offered by strained silicon technology coupled with the smaller overall device size provided by shallow trench isolation technology without relaxation of the portion of the strained silicon layer adjacent to a shallow trench isolation region by laterally extending a shallow trench isolation into the strained silicon layer overlying a silicon germanium layer.

Abstract: A trench structure and method for semiconductor device isolation are disclosed, including first and second regions of a substrate having first and second trenches, respectively, the first trench having an aspect ratio larger than that of the second trench, a first insulation material on a bottom and sidewalls of the first trench forming a first sub-trench in the first trench, a second insulation material completely filling the first sub-trench, a third insulation material formed on a bottom and sidewalls of the second trench forming a second sub-trench in the second trench, a fourth insulation material formed on a bottom and sidewalls of the second sub-trench, and a fifth insulation material completely filling a third sub-trench formed in the second sub-trench by the fourth insulation material. Trench structures may be formed in high and low aspect ratio trenches in a substrate without the generation of voids therein.

Abstract: A method of filling a plurality of trenches etched in a substrate. In one embodiment the method includes depositing a layer of spin-on glass material over the substrate and into the plurality of trenches; exposing the layer of spin-on glass material to a solvent; curing the layer of spin-on glass material; and depositing a layer of silica glass over the cured spin-on glass layer using a chemical vapor deposition technique.

Abstract: In an integrated circuit process for SOI including trench device isolation, the problem of voids in the trench fill is addressed by a triple fill process, in which a thermal oxide sidewall having recesses at the bottom corners is covered with a LPCVD deposition that fills in the recesses, followed by a void-free HDP deposition. Densification results in substantially the same etch rate for the three types of oxide.

Abstract: Crossing trenches of different depths may be formed in the same semiconductor structure by etching the deeper trench first. The deeper trench and the substrate may then be covered with a material that prevents further etching. The covering is etched through for the shallower trench, leaving a protective covering in the deeper trench.

Abstract: A method of forming trench isolation within a semiconductor substrate includes forming a first isolation trench of a first open dimension within a semiconductor substrate. The first isolation trench has a base. A second isolation trench is formed into the semiconductor substrate through the base of the first isolation trench. The second isolation trench has a second open dimension along a line parallel with the first open dimension which is less than the first open dimension. Insulative isolation material is formed within the first and second isolation trenches. The insulative isolation material has a void therein extending from within the second isolation trench to the first isolation trench. Other aspects and implementations are contemplated.

Abstract: The present invention relates to a method of manufacturing a flash memory device. The method comprises the steps of sequentially depositing a pad oxide film and a pad nitride film on a semiconductor substrate, when trenches are formed by etching the pad nitride film, the pad oxide film and the substrate using a mask for forming a device isolation film, forming trenches having a different depth in a cell region and in a peripheral by controlling an etch angle and etch target depending on the width of the trench, depositing trench insulating films on the entire surfaces to bury the trenches with the trench insulating films, performing a chemical mechanical polishing process and a strip process for the trench insulating films to form the trench insulating film upper structures of which are protruded, forming a well region through an ion implantation process, and forming a tunnel oxide film, a floating gate, a dielectric film and a control gate.

Abstract: A method for manufacturing a semiconductor device includes the steps of: sequentially forming a pad oxide layer, a nitride layer and a first photoresist layer on the semiconductor substrate; patterning the first photoresist layer into a predetermined shape to form a first photoresist layer pattern; etching the pad oxide layer, the nitride layer and the semiconductor substrate by using the first photoresist layer pattern as an etching mask, thereby forming first and second deep trench isolations in the semiconductor substrate; forming a barrier layer on an inside wall of the second deep trench isolation by performing a nitriding process after removing the first photoresist layer pattern and forming a second photoresist layer pattern at a region formed with the first deep trench isolation on the resultant material; and forming a shallow trench isolation by removing the second photoresist layer pattern and then growing silicon in the first deep trench isolation region covered with the second photoresist layer pa

Abstract: The present invention provides an integrated circuit which comprises a substrate having a plurality of device regions formed therein, said plurality of device regions being electrically isolated from each other by shallow trench isolation (STI) regions and said plurality of device regions each having opposing edges abutting its corresponding STI region; selected ones of said devices regions having a preselected first device width such that an oxide layer formed thereon includes substantially thicker perimeter regions, along said opposing edges, compared to a thinner central region that does not abut its corresponding STI region; and selected other ones of the device regions having a preselected device width substantially narrower in width than the first device width such that an oxide layer formed thereon includes perimeter regions, along opposing edges, that abut each other over its central region thereby preventing formation of a corresponding thinner central region.

Abstract: An apparatus including a contact point on a substrate; a first dielectric layer comprising a material having a dielectric constant less than five formed on the contact point, and a different second dielectric layer formed on the substrate and separated from the contact point by the first dielectric layer. Collectively, the first and second dielectric layers comprise a composite dielectric layer having a composite dielectric constant value. The contribution of the first dielectric layer to the composite dielectric value is up to 20 percent. Also, a method including depositing a composite dielectric layer over a contact point on a substrate, the composite dielectric layer comprising a first material having a dielectric constant less than 5 and a second different second material, and forming a conductive interconnection through the composite dielectric layer to the contact point.

Abstract: A method for integrating the zero-etch and STI-etch processes into one process is described. An etch stop layer is deposited on a substrate. A mask is formed overlying the etch stop layer having a first opening for a planned alignment mark and having a second opening for a planned shallow trench isolation region. The etch stop layer is etched away within the first and second openings and the semiconductor substrate exposed within the first and second openings is etched into a first depth to form a first trench underlying the first opening and a second trench underlying the second opening. The first trench is covered and the second trench is etched into the semiconductor substrate to a second depth greater than the first depth. The second trench is filled to complete formation of a shallow trench isolation region wherein the first trench completes formation of an alignment mark in the fabrication of an integrated circuit device.

Abstract: A method of providing isolation between active areas of memory cells in a memory device having a plurality of isolation trenches (115) separating the active areas, comprising depositing a first insulating material (116) and forming a resist (120) over the first insulating material (116) over at least the trenches (115), leaving a first top portion of the first insulating material (116) exposed. At least a second top portion of the first insulating material (116) is removed, the resist (120) is removed, and a second insulating material (216) is deposited over the wafer (100) to completely fill the isolation trenches (115).

Abstract: A technique for preventing a decrease in alignment accuracy during a photolithography process is provided. A substrate (1) is prepared, in the surface (80) of which trenches (7) for use as alignment marks and trenches (17, 27) each forming an element isolation structure are formed and on the surface (80) of which a polysilicon film (3) is formed, avoiding the trenches (7, 17, 27). The trenches (7, 17, 27) are filled with an insulation film (30). The insulation film (30) is then selectively etched to partially remove the insulation film (30) in the trenches (7) and to leave the insulation film (30) on side and bottom surfaces (81, 82) of the trenches (7). Using the insulation film (30) in the trenches (7) as a protective film, the polysilicon film (3) is selectively etched. The use of the insulation film (30) in the trenches (7) as a protective film prevents the substrate (1) from being etched and thereby prevents the shape of the trenches (7) from being changed.

Abstract: In a method of manufacturing a semiconductor device, a semiconductor substrate having device regions and an isolation region for separating the device region is provided. Then, a trench is formed in the isolation region of the semiconductor substrate. A nitride film is formed on the device regions of the semiconductor substrate. Next, an oxide film is formed within the trench and on the nitride film so that an upper surface of the oxide film within the trench is located more than about 500 Å below an upper surface of the nitride film. Finally, the oxide film is polished by CMP method so that a height of the upper surface of the oxide film within the trench portion is maintained at less than a height of the upper surface of the nitride film adjacent thereto.

Abstract: A method for manufacturing a semiconductor device enables the formation of a well optimized for a fine MOS transistor and a well formed deep with a relatively low concentration for a high voltage MOS transistor without increasing the number of manufacturing steps. The method for manufacturing a semiconductor device includes the steps of: forming a first ion implantation expendable film and an etching mask film on a first conductive type semiconductor substrate; patterning the etching mask film into a shape of an active and field region; introducing dopant into the substrate; forming a trench groove on the substrate; forming an insulation film in the trench groove; forming a first well; flattening the insulation film; removing the etching mask film; removing the expendable film; forming a second ion implantation expendable film on the substrate; forming a mask pattern; and forming a second well by introducing dopant into the substrate.

Abstract: A shallow trench isolation region formed in a layer of semiconductor material. The shallow trench isolation region includes a trench formed in the layer of semiconductor material, the trench being defined by sidewalls and a bottom; a liner within the trench formed from a high-K material, the liner conforming to the sidewalls and bottom of the trench; and a fill section made from isolating material, and disposed within and conforming to the high-K liner. A method of forming the shallow trench isolation region is also disclosed.

Abstract: A semiconductor device having a shallow trench isolation (STI) structure, which is capable of reducing leakage current in a P-FET and improving the device characteristics of a memory device, and a manufacturing method thereof, including a semiconductor substrate having a first area with a first trench formed therein and a second area with a second trench formed therein; a first sidewall oxide layer formed on the inner surface of the first trench; a second sidewall oxide layer, which is thinner than the first sidewall oxide layer, formed on the inner surface of the second trench; a liner formed on the surfaces of the first and second sidewall oxide layers; and a dielectric material that fills the first and second trenches.

Abstract: A new method of fabricating shallow trench isolations has been achieved. A pad oxide layer is formed overlying a semiconductor substrate. A silicon nitride layer is deposited overlying the pad oxide layer. A protective layer is deposited overlying the silicon nitride layer. The protective layer, the silicon nitride layer, and the pad oxide layer are patterned to expose the semiconductor substrate where shallow trench isolations are planned. The semiconductor substrate is etched to form trenches for the planned shallow trench isolations. A large trench etching angle is used. The presence of the protective layer prevents loss of the silicon nitride layer during the etching. A trench filling layer is deposited overlying the protective layer and filling the trenches. The trench filling layer and the protective layer are polished down to complete the shallow trench isolations in the manufacture of the integrated circuit device.

Abstract: A metrology method and system of structures on a wafer includes obtaining a projection image of at least a first portion of the structures on the wafer using a first metrology apparatus. A profile of at least a second portion of the structure on the wafer is obtained using a second metrology apparatus. The information from the profile obtained using the second metrology apparatus and the information from the projection image obtained using the first metrology apparatus are combined using a processor.

Abstract: An integrated circuit substrate includes first and second adjacent p-type doped regions spaced-apart from one another. A trench in the integrated circuit substrate is between the first and second adjacent p-type doped regions. An insulator layer in the trench has a side wall, wherein the side wall is free of a layer that reduces a stress between the integrated circuit substrate and the insulator layer.

Abstract: In a method of manufacturing a semiconductor device of STI structure, a semiconductor structure in which an insulating material layer is formed on a conductive layer which becomes a gate electrode, is prepared. Etching is conducted to the semiconductor structure to form a trench extending from the insulating material layer into the semiconductor substrate in accordance with a pattern of a resist film (not shown) covering an element region. Then, the insulating material layer is backed off by wet etching or the like and the gate electrode is processed while using the insulating material layer as a mask. As a result, it is possible to make the gate electrode smaller in size than the element region and to form a trench upper portion to be wider than the trench lower portion in the depth direction of the trench, thereby providing a good shape of the insulator embedded in the trench by depositing the insulator.

Abstract: A method for making a semiconductor device is described. That method comprises forming a carbon doped oxide containing layer and a dielectric layer on a substrate, such that at least part of the dielectric layer is located above at least part of the carbon doped oxide containing layer. A chemical mechanical polishing process is then applied to remove the part of the dielectric layer that is located above the part of the carbon doped oxide containing layer, such that it removes the dielectric layer at a significantly faster rate than it can remove the carbon doped oxide containing layer.

Abstract: A buried interconnect can be incorporated into the starting semiconductor on insulator wafer during the early stages of the circuit fabrication process flow for use with semiconductor devices. The buried interconnect provides an additional interconnect layer enabling an overall reduction in the silicon real estate occupied by interconnections. The buried interconnect has low resistance and can prevent the formation of unwanted PN junctions through the use of silicides. The buried interconnect and its fabrication method include an S0I wafer that has an oxidation layer formed on top of a semiconductor layer by oxidation, followed by an nitride layer formed on top of the oxide layer which then is selectively etched to form two trenches with regions of different depths. Some regions of the trenches are etched to remove all of the semiconductor layer in the trench to expose the buried oxide layer. In other regions, a thin layer of semiconductor is left at the bottom of the trenches.

Abstract: In a combined isolation oxide film (BT1), a part closer to a gate electrode (GT13) reaches a buried oxide film (2) through an SOI layer (3) while a part closer to another gate electrode (GT12) has a sectional shape provided with a well region on its lower portion. The shape of an edge portion of the combined isolation oxide film (BT1) is in the form of a bird's beak in a LOCOS isolation oxide film. Consequently, the thicknesses of portions defining edge portions of the gate oxide films (GO12, GO13) are locally increased. Thus provided are a semiconductor device including a MOS transistor having a gate oxide film prevented from dielectric breakdown without increasing its thickness and a method of manufacturing the same.

Abstract: A method of forming FLASH memory circuitry having an array of memory cells and having FLASH memory peripheral circuitry operatively configured to at least read from the memory cells of the array, includes forming a plurality of spaced isolation trenches within a semiconductor substrate within a FLASH memory array area and within a FLASH peripheral circuitry area peripheral to the memory array area. The forming includes forming at least some of the isolation trenches within the FLASH memory array to have maximum depths which are different within the substrate than that of at least some of the isolation trenches within the FLASH peripheral circuitry area.

Abstract: A method of forming a T-shaped isolation layer, a method of forming an elevated salicide source/drain region using the same, and a semiconductor device having the T-shaped isolation layer are provided. In the method of forming the T-shaped isolation layer, an isolation layer having a narrow trench region in the lower portion thereof and a wide trench region in the upper portion thereof is formed on a semiconductor substrate. Also, in the method of forming the elevated salicide source/drain region, the method of forming the T-shaped isolation layer is used. In particular, conductive impurities can also be implanted into the lower portion of the wide trench region which constitutes the head of the T-shaped isolation layer and is extended to both sides from the upper end of the narrow trench region by controlling the depth of the wide trench region in an ion implantation step for forming the source/drain region.

Abstract: A method for forming a dielectric zone in a region of a semiconductor substrate is described. A first trench and a second trench are formed in the region of the semiconductor substrate resulting in a web being formed between the first trench and the second trench. Afterward, a first dielectric layer is deposited in the first trench and the second trench. The web is subsequently removed, a third trench thereby being produced in the semiconductor substrate. Afterwards, a second dielectric layer is formed in the third trench. The first dielectric layer and the second dielectric layer together form a dielectric zone in the semiconductor substrate, on which it is advantageously possible to dispose components with substrate decoupling.

Abstract: A method of chemical-mechanical polishing for forming a shallow trench isolation is disclosed. A substrate having a number of active regions, including a number of relative large active regions and a number of relative small active regions, is provided. The method comprises the following steps. A silicon nitride layer on the substrate is first formed A number of shallow trenches are formed between the active regions An oxide layer is formed over the substrate, so that the shallow trenches are filled with the oxide layer. A partial reverse active mask is formed on the oxide layer. The partial rever active mask has an opening at a central part of each relative large active region. The opening exposes a portion of the oxide layer. The opening has at least a dummy pattern. The oxide layer on the central part of each large active region is removed to expose the silicon nitride layer. The partial reverse active mask is removed The oxide layer is planarized to expose the silicon nitride layer.

Abstract: One aspect of the present invention relates to a method of forming trench isolation regions within a semiconductor substrate, involving the steps of forming trenches in the semiconductor substrate; depositing a semi-conformal dielectric material over the substrate, wherein the semi-conformal dielectric material has valleys positioned over the trenches; forming an inorganic conformal film over the semi-conformal dielectric material; polishing the semiconductor substrate whereby a first portion of the inorganic conformal film is removed thereby exposing a portion of the semi-conformal dielectric material, and a second portion remains over the valleys of the semi-conformal dielectric material; removing the exposed portions of the semi-conformal dielectric material; and planarizing the substrate to provide the semiconductor substrate having trenches with a dielectric material therein.

Abstract: A method of making a semiconductor structure includes removing a cover layer. The cover layer is on a first dielectric layer, the dielectric layer is in a trench in a substrate, and a protective layer is on the substrate. Isolation regions formed by this method have a thickness which is independent of non-uniformities resulting form chemical-mechanical polishing.

Abstract: When a top surface area for a plurality of dummy patterns 13 and a width for a plurality of trenches 12 are set on the basis of a ratio (an occupation density of the film for polishing in an adjacent region 10) of a total top surface area for raised sections of the film for polishing to a horizontally projected area of the adjacent region 10, it is possible to suppress dishing and erosion and thereby attain a high planarity when a film for polishing is formed on a semiconductor substrate, wherein dummy patterns 13 partitioned by a plurality of trenches 12 are disposed in an element isolation region 11, and planarization by the CMP is applied thereto.

Abstract: Obtained is a method of manufacturing a semiconductor device which can take a body contact while electrically isolating an NMOS transistor and a PMOS transistor from each other through a complete isolation. First of all, element isolating films (7a to 7c) of a partial isolation type are formed in a first main surface of a silicon layer (3). Next, a PMOS transistor, an NMOS transistor, a multilayer wiring structure, a spiral inductor (20) and a pad (22) are formed, respectively. Then, a support substrate (23) is formed over the whole surface. Thereafter, a silicon substrate (1) and a BOX layer (2) are removed to expose a second main surface of the silicon layer (3). Subsequently, element isolating films (27a to 27d) connected to the element isolating films (7a and 7b) are formed on the second main surface side of the silicon layer (3). Consequently, a complete isolation can be obtained.

Abstract: Forming a semiconductor transistor by embedding the gate electrode into the substrate so that a step difference between the gate electrode and the source or drain region is reduced. Device isolation areas are defined by forming at least two first trenches having a first depth. The gate electrode is formed in a second trench located between the first trenches at a second depth being less than the first depth. A source and a drain are respectively formed between the gate electrode and the device isolation areas. The gate electrically connects the source and drain to form a semiconductor channel in the substrate.

Abstract: The present invention provides a formation method of a trench structure comprising forming a pad oxide layer on a substrate. A first polysilicon layer is formed on the pad oxide layer and an oxide layer is formed thereon. A second polysilicon layer is formed on the oxide layer. The partial second polysilicon layer, the oxide layer, the first polysilicon layer, and the pad oxide layer are removed to expose the partial substrate. The second polysilicon layer and the partial substrate are etched for forming the trench structure in the substrate. An etched depth of the trench structure is well controlled by the etched thickness of the second polysilicon layer.

Abstract: The present invention provides a method of fabricating a semiconductor device having a trench isolation structure. The method includes the following steps. A hard mask layer is formed on the semiconductor substrate having a cell array region and a peripheral circuit region. The hard mask layer is patterned to expose the semiconductor substrate. Thus, a hard mask pattern is formed to define a first isolation region at the cell array region and simultaneously to define a second isolation region at the peripheral circuit region. A sacrificial material layer is conformally formed at the entire surface of the second isolation region and the hard mask pattern of the peripheral circuit region and fills a gap region between the hard mask patterns of the cell array region. The sacrificial material layer and the semiconductor substrate are sequentially etched to form a first trench region and a second trench region at the cell array region and the peripheral circuit region, respectively.

Abstract: A method for forming multi-depth apertures in a substrate is provided. The method includes first providing a pad stack atop a surface of a substrate having regions for forming apertures therein, the pad stack includes at least a top patterned masking layer. Next, at least one of the regions of the substrate is blocked with a first block mask, while leaving at least one other region of the substrate unblocked. A plurality of first apertures having a first depth is then formed in the unblocked region of the substrate using the patterned masking layer to define the plurality of first apertures. The first block mask is then removed; and thereafter a plurality of second apertures having a second depth is formed in regions of the substrate that were previously blocked by the first block mask using the same patterned masking layer to define the second apertures, while simultaneously increasing the first depth such that the first depth is deeper than the second depth.

Abstract: A method is provided for planarizing a structure such as a shallow trench isolation region on a semiconductor substrate. A semiconductor substrate is provided having raised and lowered regions with substantially vertical and horizontal surfaces. The lowered regions may correspond to trench regions. The upper regions are covered by a masking layer of nitride having a predetermined thickness. Filler material such as non-conformal high density plasma oxide may be deposited over the horizontal surfaces to a thickness terminating within that of the thickness of the nitride layer. The raised regions of the filler material are then selectively removed in a single planarizing step without removing the filler material in the lowered regions using a fixed abrasive hard polishing pad, as opposed to an abrasive slurry.

Abstract: A method of decreasing the growth rate of silicon dioxide films on a silicon nitride pad on a silicon wafer wherein the decrease in growth rate of the silicon dioxide results in a self-planarized film on the wafer is provided. Also provided is a method of pretreating said silicon wafer wherein said wafer is contacted with a chemical, such as hydrogen peroxide, isopropyl alcohol or acetone and air-dried prior to silicon dioxide deposition. Additionally, selective oxidation sub-atmospheric chemical vapor deposition (SELOX SACVD) uses an ozone-activated tetraethylorthosilicate process to deposit said silicon dioxide on said wafer.

Abstract: A method of forming a shallow trench isolation region in a silicon wafer which results in the elimination of long range slip dislocations in the wafer and reduces leakage current across the isolation regions. Long shallow trenches are formed in a silicon wafer at a 45 degree angle to the (111) plane of the wafer. This is achieved by moving the primary flat of the wafer to the (100) plane prior to the formation of the trenches, which causes the bottom edges of the long trenches to intersect with several (111) planes, so that stresses do not propagate along any one single (111) plane. The trenches are then filled with an insulative material, such as oxide.

Abstract: A method for fabricating a semiconductor memory device is provided to increase the etch selectivity of photoresist by changing the matter properties thereof in forming a trench isolation region. The method includes the steps of: depositing first and second insulating layers on a semiconductor substrate where a shallow trench isolation (STI) region and a deep trench isolation (DTI) region are defined; forming the STI region by selectively etching the second and first insulating layers and the semiconductor substrate; forming a photoresist to cover the STI region and curing the surface of the photoresist; and forming the DTI region by using the cured photoresist and the second insulating layer as a mask.

Abstract: A method of forming trench isolation including a burying step of burying trenches by a deposition means for conducting etching and deposition simultaneously and a polishing step of flattening a burying material by polishing is conducted by disposing an isotropic etching step, a multi-layered etching stopper and a protrusion unifying structure. Polishing can be attained with satisfactory flatness uniformly or with no polishing residue even in a portion to be polished in which the etching stopper layer is distributed unevenly. The method can be applied to manufacture of a semiconductor device or the like.