Groove Formation Patents (Class 438/42)
-
Patent number: 7825031Abstract: The invention relates to a method of fabricating an integrated circuit, including the steps of providing at least one layer; performing a first implantation step, wherein particles are implanted into the layer under a first direction of incidence; performing a second implantation step, wherein particles are implanted into the layer under a second direction of incidence which is different from the first direction of incidence; performing a removal step, wherein the layer is partially removed depending on the local implant dose generated by the first and the second implantation step.Type: GrantFiled: September 14, 2007Date of Patent: November 2, 2010Assignee: Qimonda AGInventors: Dirk Manger, Rolf Weis, Christoph Noelscher
-
Publication number: 20100265981Abstract: A nitride-based semiconductor light-emitting diode capable of suppressing complication of a manufacturing process while improving light extraction efficiency from a light-emitting layer and further improving flatness of a semiconductor layer is obtained. This nitride-based semiconductor light-emitting diode (30) includes a substrate (11) formed with a recess portion (21) on a main surface and a nitride-based semiconductor layer (12) having a light-emitting layer (14) on the main surface and including a first side surface (12a) having a (000-1) plane formed to start from a first inner side surface (21a) of the recess portion and a second side surface (12b) formed at a region opposite to the first side surface with the light-emitting layer therebetween to start from a second inner side surface (21b) of the recess portion on the main surface.Type: ApplicationFiled: December 12, 2008Publication date: October 21, 2010Applicant: Sanyo Electric Co., Ltd.Inventors: Ryoji Hiroyama, Yasuto Miyake, Yasumitsu Kunoh, Yasuyuki Bessho, Masayuki Hata
-
Patent number: 7811846Abstract: A method for fabricating an array of semiconductor devices comprising the steps of providing a non-metallic substrate, placing a layer of spheres on said substrate, reducing diameter of the spheres, encapsulating the spheres in a matrix of rigid material, finishing an upper surface of said matrix to expose a portion of said spheres, removing the spheres to form an array of cavities within said matrix, and forming features in said cavities in contact with said substrate so as to form the device.Type: GrantFiled: March 21, 2006Date of Patent: October 12, 2010Assignee: Agency for Science, Technology and ResearchInventors: Benzhong Wang, Soo Jin Chua
-
Publication number: 20100253225Abstract: Light device comprising a substrate, at least one photo-organic layer, at least two electrode layers electrically separated by said at least one photo-organic layer, and at least one encapsulation layer, wherein said at least one photo-organic layer is positioned between said substrate and said at least one encapsulating layer, and wherein multiple openings are provided that extend through the light device to allow fluids and or heat to pass through, said openings being spaced apart from said at least one photo-organic layer.Type: ApplicationFiled: June 1, 2007Publication date: October 7, 2010Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.Inventors: Herbert Lifka, Margreet De Kok, Reinder Coehoorn, Siebe Laurentius Maria Van Mensfoort
-
Patent number: 7803645Abstract: The present invention is to provide a light-emitting device, a laser diode, formed without using the mechanical cleavage, and a process for manufacturing the device. The process comprises, after stacking semiconductor layers of the first cladding layer, the active layer, and the second cladding layer, a forming of a groove to define the laser resonator, the depth of which reaches the substrate, and the mass-transportation, within the groove, from the side surface of the groove in a portion of the substrate and the first cladding layer to the facet of the active layer and the second cladding layer. Since the facet layer thus transported reflects the crystal orientation of the side of the groove, the crystal quality of the facet layer can be maintained.Type: GrantFiled: February 27, 2006Date of Patent: September 28, 2010Assignee: Sumitomo Electric Industries, Ltd.Inventor: Michio Murata
-
Patent number: 7798970Abstract: An ultrasonic monitor implemented on a PCB includes a gel pad comprised of a gel layer and a membrane layer. Ultrasonic signals are transmitted between the ultrasonic monitor and a living subject through the gel pad. An air gap is formed in the PCB underneath transducer elements to provide for more efficient signal transmission. These features provide for a low power, low cost, more efficient ultrasonic monitor. The entire ultrasonic monitor may be encapsulated in plastic, a gel, or both to provide water resistant properties.Type: GrantFiled: November 17, 2004Date of Patent: September 21, 2010Assignee: Salutron, IncInventors: Thomas Ying-Ching Lo, Rong Jong Chang
-
Patent number: 7800201Abstract: A thinned wafer having stress dispersion parts that make the wafer resistant to warpage and a method for manufacturing a semiconductor package using the same is described. The wafer includes a wafer body having a semiconductor chip forming zone and a peripheral zone located around the semiconductor chip forming zone; and the stress dispersion parts are located in the peripheral zone so as to disperse stress induced in the peripheral zone and the semiconductor chip forming zone.Type: GrantFiled: March 6, 2008Date of Patent: September 21, 2010Assignee: Hynix Semiconductor Inc.Inventor: Sung Ho Hyun
-
Publication number: 20100226134Abstract: An apparatus for collimating radiation can include an aperture of subwavelength dimensions and a neighboring set of grooves defined on a metal film integrated with an active or passive device that emits radiation. Integration of the beam collimator onto the facet of a laser or other radiation-emitting device provides for beam collimation and polarization selection. Beam divergence can be reduced by more than one order of magnitude compared with the output of a conventional laser. An active beam collimator with an aperture-groove structure can be integrated with a wide range of optical devices, such as semiconductor lasers (e.g., quantum cascade lasers), light emitting diodes, optical fibers, and fiber lasers.Type: ApplicationFiled: November 19, 2008Publication date: September 9, 2010Applicant: PRESIDENT AND FELLOWS OF HARVARD COLLEGEInventors: Federico Capasso, Nanfang Yu, Jonathan Fan
-
Patent number: 7791061Abstract: A light emitting diode is disclosed that includes a support structure and a Group III nitride light emitting active structure mesa on the support structure. The mesa has its sidewalls along an indexed crystal plane of the Group III nitride. A method of forming the diode is also disclosed that includes the steps of removing a substrate from a Group III nitride light emitting structure that includes a sub-mount structure on the Group III nitride light emitting structure opposite the substrate, and thereafter etching the surface of the Group III nitride from which the substrate has been removed with an anisotropic etch to develop crystal facets on the surface in which the facets are along an index plane of the Group III nitride. The method can also include etching the light emitting structure with an anisotropic etch to form a mesa with edges along an index plane of the Group III nitride.Type: GrantFiled: January 30, 2006Date of Patent: September 7, 2010Assignee: Cree, Inc.Inventors: John A. Edmond, David B. Slater, Jr., Hua Shuang Kong, Matthew Donofrio
-
Publication number: 20100220759Abstract: Provided is a semiconductor laser, wherein (?a??w)>15 (nm) and Lt<25 (?m), where ?w is the wavelength of light corresponding to the band gap of the active layer disposed at a position within a distance of 2 ?m from one end surface in a resonator direction, ?a is the wavelength of light corresponding to the band gap of the active layer disposed at a position that is spaced a distance of equal to or more than ( 3/10)L and <( 7/10)L from the one end surface in a resonator direction, “L” is the resonator length, and “Lt” is the length of a transition region provided between the position of the active layer with a band gap corresponding to a light wavelength of ?w+2 (nm) and the position of the active layer with a band gap corresponding to a light wavelength of ?a?2 (nm) in the resonator direction.Type: ApplicationFiled: February 23, 2010Publication date: September 2, 2010Applicant: NEC ELECTRONICS CORPORATIONInventors: Kentaro TADA, Kenji ENDO, Kazuo FUKAGAI, Tetsuro OKUDA, Masahide KOBAYASHI
-
Publication number: 20100219442Abstract: Provided is a semiconductor light emitting device and a method for manufacturing the same. The semiconductor light emitting device includes a light emitting structure, an insulating substrate, a first electrode, a second electrode, and a conductive supporting substrate. The light emitting structure includes a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer. The insulating substrate is formed on the light emitting structure to include a contact groove. The first electrode is formed on the insulating substrate. The second electrode is formed under the light emitting structure. The conductive supporting substrate is formed under the second electrode.Type: ApplicationFiled: February 14, 2007Publication date: September 2, 2010Inventor: Sang Youl Lee
-
Patent number: 7785908Abstract: A method of forming a light emitting diode includes forming a transparent substrate and a GaN buffer layer on the transparent substrate. An n-GaN layer is formed on the buffer layer. An active layer is formed on the n-GaN layer. A p-GaN layer is formed on the active layer. A p-electrode is formed on the p-GaN layer and an n-electrode is formed on the n-GaN layer. A reflective layer is formed on a second side of the transparent substrate. A scribe line is formed on the substrate for separating the diodes on the substrate. Also, a cladding layer of AlGaN is between the p-GaN layer and the active layer.Type: GrantFiled: March 2, 2007Date of Patent: August 31, 2010Assignee: LG Electronics Inc.Inventor: Myung Cheol Yoo
-
Patent number: 7781796Abstract: A nitride semiconductor laser element includes a substrate and a nitride semiconductor layer in which a first semiconductor layer, an active layer, and a second semiconductor layer are laminated in this order on the substrate. At least one of the first semiconductor layer and the second semiconductor layer includes a first section forming recessed and raised portions and a second section embedding the recessed and raised portions of the first section. A region with a higher aluminum mixed crystal ratio than the second section that embeds the recessed and raised portions is disposed on top faces of the raised portions. The nitride semiconductor layer defines resonant planes, and the recessed and raised portions are formed in a shape of stripes that extend substantially parallel to the resonant planes.Type: GrantFiled: June 14, 2007Date of Patent: August 24, 2010Assignee: Nichia CorporationInventors: Shingo Masui, Kazutaka Tsukayama
-
Patent number: 7781275Abstract: A method of manufacturing a flash memory device is disclosed. The method includes the steps of providing a semiconductor substrate in which a cell region and a select transistor region are defined, etching the semiconductor substrate in the select transistor region so that there is a first step between the cell region and the select transistor region, forming a cell gate in the cell region, and forming a transistor in the select transistor region.Type: GrantFiled: June 5, 2007Date of Patent: August 24, 2010Assignee: Hynix Semiconductor Inc.Inventor: Young Ho Yang
-
Patent number: 7777241Abstract: A semiconductor sensor, solar cell or emitter or a precursor therefore having a substrate and textured semiconductor layer deposited onto the substrate. The layer can be textured as grown on the substrate or textured by replicating a textured substrate surface. The substrate or first layer is then a template for growing and texturing other semiconductor layers from the device. The textured layers are replicated to the surface from the substrate to enhance light extraction or light absorption. Multiple quantum wells, comprising several barrier and quantum well layers, are deposited as alternating textured layers. The texturing in the region of the quantum well layers greatly enhances internal quantum efficiency if the semiconductor is polar and the quantum wells are grown along the polar direction. This is the case in nitride semiconductors grown along the polar [0001] or [000-1] directions.Type: GrantFiled: April 15, 2005Date of Patent: August 17, 2010Assignee: The Trustees of Boston UniversityInventors: Theodore D. Moustakas, Jasper S. Cabalu
-
Publication number: 20100203662Abstract: A light emitting device includes a substrate having a first surface and a second surface not parallel to the first surface, and a light emission layer disposed over the second surface to emit light. The light emission layer has a light emission surface which is not parallel to the first surface.Type: ApplicationFiled: April 26, 2010Publication date: August 12, 2010Inventor: Shaoher X. Pan
-
Patent number: 7771532Abstract: A nitride semiconductor crystal substrate is produced by forming a network mask repeating a closed loop unit shape upon an undersubstrate, growing a nitride semiconductor crystal in vapor phase, producing convex facet hills covered with facets on exposed parts ?, forming outlining concavities on mask-covered parts , not burying the facets, maintaining the convex facet hills on ? and the network concavities on , excluding dislocations in the facet hills down to the outlining concavities on , forming a defect accumulating region H on , decreasing dislocations in the facet hills and improving the facet hills to low defect density single crystal regions Z, producing a rugged nitride crystal, and slicing and polishing the nitride crystal into mirror nitride crystal wafers. After the fabrication of devices on the nitride wafer, dry-etching or wet etching of hot KOH or NaOH divides the device-carrying wafer into chips by corroding the network defect accumulating region H.Type: GrantFiled: February 19, 2009Date of Patent: August 10, 2010Assignee: Sumitomo Electric Industries, Ltd.Inventors: Koji Uematsu, Fumitaka Sato, Ryu Hirota, Seiji Nakahata, Hideaki Nakahata
-
Patent number: 7772585Abstract: A nitride semiconductor crystal substrate is produced by forming a network mask repeating a closed loop unit shape upon an undersubstrate, growing a nitride semiconductor crystal in vapor phase, producing convex facet hills covered with facets on exposed parts ?, forming outlining concavities on mask-covered parts , not burying the facets, maintaining the convex facet hills on ? and the network concavities on , excluding dislocations in the facet hills down to the outlining concavities on , forming a defect accumulating region H on , decreasing dislocations in the facet hills and improving the facet hills to low defect density single crystal regions Z, producing a rugged nitride crystal, and slicing and polishing the nitride crystal into mirror nitride crystal wafers. After the fabrication of devices on the nitride wafer, dry-etching or wet etching of hot KOH or NaOH divides the device-carrying wafer into chips by corroding the network defect accumulating region H.Type: GrantFiled: June 6, 2006Date of Patent: August 10, 2010Assignee: Sumitomo Electric Industries, Ltd.Inventors: Koji Uematsu, Fumitaka Sato, Ryu Hirota, Seiji Nakahata, Hideaki Nakahata
-
Patent number: 7772020Abstract: A vertical topology device includes a conductive adhesion structure having a first surface and a second surface, a conductive thick film support formed on the first surface, and a semiconductive device having an upper electrical contact and located over the conductive adhesion layer. Electrical current can flow between the conductive thick film and the upper electrical contact.Type: GrantFiled: August 2, 2007Date of Patent: August 10, 2010Assignee: LG Electronics Inc.Inventor: Myung Cheol Yoo
-
Publication number: 20100187559Abstract: Provided is a semiconductor light emitting device and a method of fabricating the same. The semiconductor light emitting device comprises: a first conductive semiconductor layer; an active layer on the first conductive semiconductor layer; a second conductive semiconductor layer on the active layer; a second electrode part on the second conductive semiconductor layer; an insulation layer on the second electrode part; and a first electrode part on the insulation layer, a portion of the first electrode part being electrically connected to the first conductive semiconductor layer.Type: ApplicationFiled: December 12, 2008Publication date: July 29, 2010Inventor: Jae Cheon Han
-
Patent number: 7763485Abstract: A method for etching facets of a laser die prior to coating in such a way as to control the formation of oxides and metallic films on the facet is disclosed. In one embodiment, the method includes placing a wafer on which the laser is included in the interior volume of an etching chamber. Nitrogen is introduced into the interior volume to define a nitrogen-rich environment. The laser facet is then etched in the nitrogen-rich environment with argon delivered from an ion gun. In another embodiment, the method includes placing the laser in an ion beam etching chamber, then physically etching the facet of the laser with an ion beam that includes an argon/nitrogen mixture. The laser facet(s) can then be coated as desired. The etching method reduces the incidence of leakage current during operation of the laser die caused by metallic film formation on the facet before coating.Type: GrantFiled: May 15, 2007Date of Patent: July 27, 2010Assignee: Finisar CorporationInventors: Roman Dimitrov, Ashish Verma, Tsurugi Sudo, Scott Lehmann
-
Patent number: 7763898Abstract: A light emitting device includes a lower semiconductor layer of a first conductivity type; an optical emission layer formed on said lower semiconductor layer; an upper semiconductor layer of a second conductivity type opposite to said first conductivity type, said upper semiconductor layer being formed on said optical emission layer; a lower side electrode electrically connected to said lower semiconductor layer; and an upper side electrode electrically connected to said upper semiconductor layer, wherein said upper side electrode is formed on said upper semiconductor layer, and said upper semiconductor layer has a mesh pattern defining a plurality of sections each surrounded by said upper side electrode, and wherein at least one dent is disposed in at least one of said sections, said dent having a bottom reaching at least an upper surface of said lower semiconductor layer and having an opening with an upper edge spaced apart from said upper side electrode.Type: GrantFiled: October 30, 2006Date of Patent: July 27, 2010Assignee: Stanley Electric Co., Ltd.Inventors: Satoshi Tanaka, Naochika Horio, Masahiko Tsuchiya
-
Patent number: 7759142Abstract: Embodiments described include straining transistor quantum well (QW) channel regions with metal source/drains, and conformal regrowth source/drains to impart a uni-axial strain in a MOS channel region. Removed portions of a channel layer may be filled with a junction material having a lattice spacing different than that of the channel material to causes a uni-axial strain in the channel, in addition to a bi-axial strain caused in the channel layer by a top barrier layer and a bottom buffer layer of the quantum well.Type: GrantFiled: December 31, 2008Date of Patent: July 20, 2010Assignee: Intel CorporationInventors: Prashant Majhi, Mantu K. Hudait, Jack T. Kavalieros, Ravi Pillarisetty, Marko Radosavljevic, Gilbert Dewey, Titash Rakshit, Willman Tsai
-
Patent number: 7754511Abstract: The present invention discloses a laser lift-off method, which applies to lift off a transient substrate from an epitaxial layer grown on the transient substrate after a support substrate having an adhesion metal layer is bonded to the epitaxial layer. Firstly, the epitaxial layer is etched to define separation channels around each chip section, and the epitaxial layer between two separation channels is not etched but preserved to form a separation zone. Each laser illumination area only covers one illuminated chip section, the separation channels surrounding the illuminated chip section, and the separation zones surrounding the illuminated chip section. Thus, the adhesion metal layer on the separation channels is only heated once. Further, the outward stress generated by the illuminated chip section is counterbalanced by the outward stress generated by the illuminated separation zones, and the stress-induced structural damage on the chip section is reduced.Type: GrantFiled: July 8, 2008Date of Patent: July 13, 2010Assignee: High Power Opto. Inc.Inventors: Wei-Chih Wen, Liang-Jyi Yan, Chih-Sung Chang
-
Patent number: 7745246Abstract: A light emitting device wafer is fabricated, having a light emitting layer section, composed of AlGaInP, based on a double heterostructure and a GaP light extraction layer disposed on the light emitting layer portion, having a first main surface thereof appearing on the first main surface of the wafer, so as that a P-rich off-angled {100} surface, having a higher existence rate of P atoms than an exact {100} surface, appears on the first main surface the GaP light extraction layer. The main first surface of the GaP light extraction layer is etched with an etching solution FEA so as to form surface roughening projections. Therefore, it provides a method of fabricating a light emitting device capable of applying surface roughening easily to the GaP light extraction surface having the {100} surface, off-angled to be P-rich, as a main surface thereof.Type: GrantFiled: May 29, 2006Date of Patent: June 29, 2010Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Yukari Suzuki, Hitoshi Ikeda
-
Publication number: 20100155715Abstract: A display substrate according to the present invention comprises a gate line formed on a substrate. a data line, a thin film transistor connected to the gate line and the data line respectively and pixel electrode connected to the thin film transistor, wherein a channel of the thin film transistor is formed in a direction perpendicular to the substrate and, a layer where the channel is formed includes an oxide semiconductor pattern. ON current of thin film transistor of the display substrate can be increased without loss of aperture ratio.Type: ApplicationFiled: February 26, 2009Publication date: June 24, 2010Applicant: SAMSUNG ELECTRONICS CO., LTDInventors: Pil-Sang YUN, Do-Hyun KIM, Byeong-Beom KIM, Bong-Kyun KIM
-
Patent number: 7741134Abstract: A light source and method for fabricating the same are disclosed. The light source includes a substrate and a light emitting structure. The substrate has a first surface and a second surface, the second surface including a curved, convex surface with respect to the first surface of the substrate. The light emitting structure includes a first layer of a material of a first conductivity type overlying the first surface, an active layer overlying the first layer, the active layer generating light when holes and electrons recombine therein, and a second layer includes a material of a second conductivity type overlying the active layer and a second surface opposite to the first surface. A mirror layer overlies the light emitting structure.Type: GrantFiled: September 15, 2008Date of Patent: June 22, 2010Assignee: Bridgelux, Inc.Inventor: Ghulam Hasnain
-
Patent number: 7736923Abstract: An optical semiconductor device includes: a first conductivity type first semiconductor region; a first conductivity type second semiconductor region formed on the first semiconductor region; a second conductivity type third semiconductor region formed on the second semiconductor region; a photodetector section formed of the second semiconductor region and the third semiconductor region; a micro mirror formed of a trench formed selectively in a region of the first semiconductor region and the second semiconductor region except the photodetector section; and a semiconductor laser element held on the bottom face of the trench. A first conductivity type buried layer of which impurity concentration is higher than those of the first semiconductor region and the second semiconductor region is selectively formed between the first semiconductor region and the second semiconductor region in the photodetector section.Type: GrantFiled: April 7, 2008Date of Patent: June 15, 2010Assignee: Panasonic CorporationInventor: Takaki Iwai
-
Publication number: 20100144075Abstract: Provided is a method of forming optical waveguide. The method includes forming a trench on a semiconductor substrate to define an active portion, and partially oxidizing the active portion. An non-oxidized portion of the active portion is included in a core through which an optical signal passes, and an oxidized portion of the active portion is included in a cladding.Type: ApplicationFiled: June 25, 2009Publication date: June 10, 2010Applicant: Electronics and Telecommunications Research InstituteInventors: In-Gyoo Kim, Dong-Woo Suh, Gyung-Ock Kim
-
Patent number: 7732817Abstract: A partition-wall structure having a concave portion corresponding to a pattern formed by a functional liquid, including: a first concave portion provided corresponding to a first pattern; a second concave portion provided corresponding to a second pattern that is coupled to the first pattern and whose width is smaller than a width of the first pattern; and a convex portion provided in the first pattern.Type: GrantFiled: August 30, 2005Date of Patent: June 8, 2010Assignee: Seiko Epson CorporationInventors: Toshimitsu Hirai, Toshihiro Ushiyama
-
Publication number: 20100133562Abstract: A light emitting device and method for making the same are disclosed. The device includes an active layer disposed between first and second layers. The first layer has top and bottom surfaces. The top surface includes a first material of a first conductivity type, including a plurality of pits in the substantially planar surface. The active layer overlies the top surface of the first layer and conforms to the top surface, the active layer generating light characterized by a wavelength when holes and electrons recombine therein. The second layer includes a second material of a second conductivity type, the second layer overlying the active layer and conforming to the active layer. The device can be constructed on a substrate having a lattice constant sufficiently different from that of the first material to give rise to dislocations in the first layer that are used to form the pits.Type: ApplicationFiled: August 21, 2009Publication date: June 3, 2010Inventors: Ling Zhang, Steven D. Lester, Jeffrey C. Ramer
-
Patent number: 7723137Abstract: In a conventional optical device which mounts a semiconductor light emitting element, the processing is difficult and a manufacturing process cost is expensive because of the necessity of forming via holes in a substrate. An optical device comprises a laser diode which needs heat radiation, a glass substrate which is integrally molded into a mold glass for arranging the laser diode, a metallic heat sink arranged at an edge of the glass substrate for radiating heat generated from the laser diode, wherein an active layer proximity surface of the laser diode is arranged to oppose the heat sink, both of them are connected with a conductive paste through a lateral groove formed in the glass substrate.Type: GrantFiled: July 31, 2006Date of Patent: May 25, 2010Assignee: Panasonic CorporationInventors: Kaoru Ishida, Tsuguhiro Korenaga
-
Patent number: 7723732Abstract: A semiconductor light-emitting device includes a substrate having two main surfaces; and an active layer forming part, which is made of a compound semiconductor material, formed on one of the main surfaces, and includes an active layer. A plurality of holes, which pass through the active layer, are formed from the upper surface of the active layer forming part; a plurality of hollow parts, each of which corresponds to each hole, are provided between the active layer and the substrate; and the area of each hollow part is larger than that of the corresponding hole in plan view, and spreads on the lower surface of the active layer forming part, so as to expose a part of the lower surface of the active layer forming part, which overlaps the hollow part in plan view.Type: GrantFiled: November 7, 2007Date of Patent: May 25, 2010Assignee: Sanken Electric Co., Ltd.Inventors: Mikio Tazima, Yoshiki Tada
-
Patent number: 7713769Abstract: The present invention discloses a light emitting diode structure and a method for fabricating the same. In the present invention, a substrate is placed in a solution to form a chemical reaction layer on carved regions; the carved region is selectively etched to form a plurality of concave zones and form a plurality of convex zones; a semiconductor layer structure is epitaxially grown on the element regions and carved regions of the substrate; the semiconductor layer structure on the element regions is fabricated into a LED element with a photolithographic process.Type: GrantFiled: December 21, 2007Date of Patent: May 11, 2010Assignee: Tekcore Co., Ltd.Inventors: Hung-Cheng Lin, Chia-Ming Lee, Jen-Inn Chyi
-
Publication number: 20100112741Abstract: A photonic semiconductor device and method are provided that ensure that the surface of the device upon completion of the SAG process is planar, or at least substantially planar, such that performance of the subsequent processes is facilitated, thereby enabling higher manufacturing yield to be achieved. A photonic semiconductor device and method are also provided that ensure that the isolation region of the device will have high resistance and low capacitance, without requiring the placement of a thick dielectric material beneath each of the contact pads. Eliminating the need to place thick dielectric materials underneath the contact pads eliminates the risk that the contact pads will peel away from the assembly.Type: ApplicationFiled: January 12, 2010Publication date: May 6, 2010Applicant: Avago Technologies Fiber IP Pte. Ltd.Inventors: Marzia Rosso, Alessandro Stano, Ruiyu Fang, Paolo Valenti, Pietro Della Casa, Simone Codato, Cesare Rigo, Claudio Coriasso
-
Patent number: 7709281Abstract: A method for manufacturing a semiconductor laser device includes forming a laminate having a semiconductor layer of a first conductivity type, an active layer and a semiconductor layer of a second conductivity type. The waveguide region is formed to guide light perpendicular to the direction of width by restricting the light from spreading in the direction of width in the active layer, such that the semiconductor laser device has a first waveguide region and a second waveguide region. The first waveguide region is formed to confine light within the limited active layer by means of a difference in the refractive index between the active layer and the regions on both sides of the active layer by limiting the width of the active layer. In forming the second waveguide region, light is confined therein by providing effective difference in refractive index in the active layer.Type: GrantFiled: November 19, 2008Date of Patent: May 4, 2010Assignee: Nichia CorporationInventor: Hiroaki Matsumura
-
Patent number: 7700391Abstract: The present invention is a method of fabricating an optical device using multiple sacrificial spacer layers. The first step in this process is to fabricate the underlying base structure and deposit an optical structure thereon. A facet is then created at the ends of the optical structure and alternating sacrificial and intermediate layers are fabricated on the device. A mask layer is deposited on the structure, with openings created in the layers to allow use of an etchant. User-defined portions of the spacer layers are subsequently removed with the etchant to create air gaps between the intermediate layers.Type: GrantFiled: May 5, 2009Date of Patent: April 20, 2010Assignee: U.S. Government as Represented by the Director, National Security Agency, TheInventors: John L. Fitz, Daniel S. Hinkel, Scott C. Horst
-
Patent number: 7700393Abstract: A method of manufacturing an enhancement type semiconductor probe and an information storage device having the enhancement type semiconductor probe are provided. The method involves using an anisotropic wet etching and a side-wall in which influence of process parameters upon the performance of a device is reduced to improve reliability of the device in mass-production, and factors of degrading measuring sensitivity is removed to improve the performance of the device.Type: GrantFiled: March 7, 2008Date of Patent: April 20, 2010Assignees: Samsung Electronics Co., Ltd., Seoul National University Industry FoundationInventors: Hyoung Soo Ko, Byung Gook Park, Seung Bum Hong, Chul Min Park, Woo Young Choi, Jong Pil Kim, Jae Young Song, Sang Wan Kim
-
Publication number: 20100093123Abstract: A nitride-based light emitting device capable of achieving an enhancement in emission efficiency and an enhancement in reliability is disclosed. The light emitting device includes a semiconductor layer, and a light extracting layer arranged on the semiconductor layer and made of a material having a refractive index equal to or higher than a reflective index of the semiconductor layer.Type: ApplicationFiled: December 14, 2009Publication date: April 15, 2010Inventors: Hyun Kyong CHO, Sun Kyung KIM, Jun Ho JANG
-
Publication number: 20100092888Abstract: A process for etching a silicon-containing substrate to form structures is provided. In the process, a metal is deposited and patterned onto a silicon-containing substrate (commonly one with a resistivity above 1-10 ohm-cm) in such a way that the metal is present and touches silicon where etching is desired and is blocked from touching silicon or not present elsewhere. The metallized substrate is submerged into an etchant aqueous solution comprising about 4 to about 49 weight percent HF and an oxidizing agent such as about 0.5 to about 30 weight percent H2O2, thus producing a metallized substrate with one or more trenches. A second silicon etch is optionally employed to remove nanowires inside the one or more trenches.Type: ApplicationFiled: October 9, 2009Publication date: April 15, 2010Inventors: Brent A. Buchine, Faris Modawar, Marcie R. Black
-
Publication number: 20100085996Abstract: A method for manufacturing a nitride semiconductor laser device with suppression of deterioration of the yield and good light emission characteristic. The method comprises a step of forming nitride semiconductor layers on an n-type GaN substrate, a step of forming a ridge composed of a p-type clad layer and a contact layer and extending in the [1-100] direction, a step of forming a trench made in the top surface of the n-type GaN substrate by applying a YAG laser beam and extending in the direction ([11-20] direction) perpendicular to the ridge, and a step of forming end surfaces of a resonator by dividing the n-type GaN substrate from the trench. The step of forming a trench includes a substep of forming the end of the trench in a region a predetermined distance W2 (about 50 ?m to about 200 ?m) apart from the side face of the ridge.Type: ApplicationFiled: October 15, 2007Publication date: April 8, 2010Applicant: SANYO ELECTRIC CO., LTD.Inventor: Yuji Matsuno
-
Publication number: 20100087021Abstract: A method of fabricating a pixel structure includes first forming a first, a second, and a third dielectric layers over an active device and a substrate. Etching rates of the first and the third dielectric layers are lower than an etching rate of the second dielectric layer. A contact opening exposing a portion of the active device is formed in the third, the second, and the first dielectric layers. The third and the second dielectric layers are patterned to form a number of stacked structures. An electrode material layer is formed and fills the contact opening. The electrode material layer located on the stacked structures and the electrode material layer located on the first dielectric layer are separated. The stacked structures and the electrode material layer thereon are simultaneously removed to define a pixel electrode and to form at least an alignment slit in the pixel electrode.Type: ApplicationFiled: June 23, 2009Publication date: April 8, 2010Applicant: AU OPTRONICS CORPORATIONInventors: Hsiang-Chih Hsiao, Chih-Chun Yang, Chin-Yueh Liao
-
Patent number: 7692200Abstract: A nitride semiconductor light-emitting device wherein a substrate or nitride semiconductor layer has a defect concentration region and a low defect density region other than the defect concentration region. A portion including the defect concentration region of the nitride semiconductor layer or substrate has a trench region deeper than the low defect density region. Thus by digging the trench in the defect concentration region, the growth detection is uniformized, and the surface planarity is improved. The uniformity of the characteristic in the wafer surface leads to improvement of the yield.Type: GrantFiled: December 3, 2008Date of Patent: April 6, 2010Assignees: Sharp Kabushiki Kaisha, Sumitomo Electric Industries, Ltd.Inventors: Takeshi Kamikawa, Yoshika Kaneko, Kensaku Motoki
-
Publication number: 20100078672Abstract: Provided is a method for producing a Group III nitride semiconductor light-emitting device including a GaN substrate serving as a growth substrate, which method realizes processing of the GaN substrate to have a membrane structure at high reproducibility. In the production method, a stopper layer of AlGaN having an Al compositional proportion of 20% is formed on the top surface of a GaN substrate; an n-type layer, an active layer, a p-type layer, and a p-electrode are sequentially formed on the stopper layer; and the p-electrode is joined to a support substrate. Subsequently, a mask having a center-opening pattern is formed on the bottom surface of the GaN substrate, and the bottom surface is subjected to PEC etching. The bottom surface is irradiated with light having a wavelength corresponding to an energy higher than the band gap of GaN, but lower than the band gap of AlGaN having an Al compositional proportion of 20%.Type: ApplicationFiled: September 30, 2009Publication date: April 1, 2010Applicant: Toyoda Gosei Co., Ltd.Inventors: Miki Moriyama, Koichi Goshonoo
-
Patent number: 7682855Abstract: A substrate-free light emitting diode (LED) including an epitaxy layer, a conductive supporting layer, and a first contact pad is provided. The epitaxy layer includes a first type doped semiconductor layer, a light emitting layer, and a second type doped semiconductor layer. The light emitting layer is disposed on the first type doped semiconductor layer, and a portion of the first type doped semiconductor layer is exposed. The second type doped semiconductor layer and the conductive supporting layer are sequentially disposed on the second type doped semiconductor layer. The first contact pad is disposed on the exposed first type doped semiconductor layer and electrically connected thereto. The first contact pad and the conductive supporting layer serving as an electrode are disposed on the same side of the epitaxy layer to avoid the light shielding effects of the electrode to improve the front light emitting efficiency of the LED.Type: GrantFiled: July 31, 2006Date of Patent: March 23, 2010Assignee: Industrial Technology Research InstituteInventors: Chien-Cheng Yang, Zhi-Cheng Hsiao, Gen-Wen Hsieh
-
Patent number: 7684661Abstract: An optical module where breaking of an optical fiber is avoided to improve ease of handling in the assembly process of the module and mechanical reliability of the module including resistance to impact. The optical module has a PD (3) and an optical fiber (5a) that are mounted on the same substrate (2). A covering section (6) for covering the optical fiber (5a) is placed on a deep trench section (24) having a predetermined depth in the Z2 direction from a V-groove-formed surface where a V-groove for mounting the optical fiber (5a) is formed. The distance h from an end face (3a) of the PD (3) to an end face (24a) of the deep trench section (24) and the distance k from an end face (51a) of the optical fiber (5a) to an end face (6a) of the covering section (6) satisfy the relationship of h>k. The optical fiber (5a) is mounted with both the end face (6a) of the covering section (6) and the end face (24a) of the deep trench section (24) made to be in contact with each other.Type: GrantFiled: December 14, 2006Date of Patent: March 23, 2010Assignee: Mitsumi Electric Co., Ltd.Inventor: Akira Nakamura
-
Patent number: 7669320Abstract: A method for fabricating an IC support for supporting a first IC die connected in series with a second IC die; the IC support comprising a stack of alternating layers of copper features and vias in insulating surround, the first IC die being bondable onto the IC support, and the second IC die being bondable within a cavity inside the IC support, wherein the cavity is formed by etching away a copper base and selectively etching away built up copper.Type: GrantFiled: April 19, 2007Date of Patent: March 2, 2010Assignee: Amitec-Advanced Multilayer Interconnect Technologies Ltd.Inventors: Dror Hurwitz, Mordechay Farkash, Eva Igner, Boris Statnikov, Benny Michaeli
-
Patent number: 7670950Abstract: A method for metallizing a through silicon via feature in a semiconductor integrated circuit device substrate comprising immersing the semiconductor integrated circuit device substrate into an electrolytic copper deposition composition comprising a source of copper ions, an organic sulfonic acid or inorganic acid, or one or more organic compounds selected from among polarizers and/or depolarizers, and chloride ions.Type: GrantFiled: August 4, 2008Date of Patent: March 2, 2010Assignee: Enthone Inc.Inventors: Thomas B. Richardson, Yun Zhang, Chen Wang, Vincent Paneccasio, Jr., Cai Wang, Xuan Lin, Richard Hurtubise, Joseph A. Abys
-
Patent number: 7667319Abstract: An electroosmotic pump may be fabricated using semiconductor processing techniques with a nanoporous open cell dielectric frit. Such a frit may result in an electroosmotic pump with better pumping capabilities.Type: GrantFiled: December 15, 2004Date of Patent: February 23, 2010Assignee: Intel CorporationInventors: R. Scott List, Alan Myers, Quat T. Vu
-
Patent number: 7662672Abstract: A manufacturing process of a leadframe-based BGA package is disclosed. A leadless leadframe with an upper layer and a lower layer is provided for the package. The upper layer includes a plurality of ball pads, and the lower layer includes a plurality of sacrificial pads aligning and connecting with the ball pads. A plurality of leads are formed in either the upper layer or the lower layer to interconnect the ball pads or the sacrificial pads. An encapsulant is formed to embed the ball pads after chip attachment and electrical connections. During manufacturing process, a half-etching process is performed after encapsulation to remove the sacrificial pads to make the ball pads electrically isolated and exposed from the encapsulant for solder ball placement where the soldering areas of the ball pads are defined without the need of solder mask(s) to solve the problem of solder bleeding of the solder balls on the leads or the undesired spots during reflow. Moreover, mold flash can easily be detected and removed.Type: GrantFiled: May 19, 2008Date of Patent: February 16, 2010Assignees: ChipMos Technologies (Bermuda) Ltd., ChipMos Technologies Inc.Inventor: Hung-Tsun Lin