Abstract: The present invention relates to a method for the production of at least one three-dimensional layer of solid material, in particular for usage as wafer, and/or at least one tree-dimensional solid body.

Abstract: Provided is a bonding device for bonding a substrate and an electronic part of an assembled body which is formed by mounting the electronic part on the substrate with a metal particle paste sandwiched therebetween. The bonding device is configured to bond the substrate and the electronic part to each other by heating a pressure applying unit having a first transfer member and a second transfer member which transfer pressure and heat to the assembled body n a state where the assembled body is sandwiched between the first transfer member and the second transfer member while applying pressure to the pressure applying unit. The bonding device further includes a heating mechanism part having a first heating part and a second heating part arranged at positions opposite to each other, a positioning mechanism part, and a pressure applying mechanism part.

Abstract: A mask is provided for vapor deposition. The mask includes a plurality of effective open areas each of which includes apertures formed therein and extending therethrough to define hollow openings through which a deposition material is allowed to pass. The mask also includes ineffective areas that include solid portions located around the effective open areas. The ineffective areas include recesses formed therein such that the ineffective areas that have the same surface area as that of the effective open areas are made to have substantially the same mass as that of the effective open areas.

Abstract: A curved display device includes a semiconductor chip package including a base film, a plurality of driving chips on the base film, and an input wire unit and an output wire unit connected to the driving chips, a printed circuit board (PCB) connected to the input wire unit of the semiconductor chip package, and a display panel including a display unit and a pad unit connected to the output wire unit of the semiconductor chip package, wherein the display panel, the semiconductor chip package, and the PCB are bendable in a first direction, and the driving chips of the of the semiconductor chip package are separated from each other in the first direction.

Abstract: A method for manufacturing a high-resistivity semiconductor-on-insulator substrate comprising the steps of: a) forming a dielectric layer and a semiconductor layer over a high-resistivity substrate, such that the dielectric layer is arranged between the high-resistivity substrate and the semiconductor layer; b) forming a hard mask or resist over the semiconductor layer, wherein the hard mask or resist has at least one opening at a predetermined position; c) forming at least one doped region in the high-resistivity substrate by ion implantation of an impurity element through the at least one opening of the hard mask or resist, the semiconductor layer and the dielectric layer; d) removing the hard mask or resist; and e) forming a radiofrequency (RF) circuit in and/or on the semiconductor layer at least partially overlapping the at least one doped region in the high-resistivity substrate.

Abstract: An organic light emitting display apparatus including a substrate including a plurality of pixel areas; a pixel electrode on the substrate; an opposite electrode on the pixel electrode, the opposite electrode transmitting light; an organic light emitting layer between the pixel electrode and the opposite electrode, the organic light emitting layer emitting a first light toward the opposite electrode; a light emitting layer on the opposite electrode, the light emitting layer absorbing a portion of the first light and emitting a second light; and a sealing layer on the light emitting layer, the sealing layer sealing the pixel electrode, the opposite electrode, the organic light emitting layer, and the light emitting layer.

Abstract: A three-dimensional (3D) integrated circuit (IC) die is provided. In some embodiments, a first IC die comprises a first semiconductor substrate, a first interconnect structure over the first semiconductor substrate, and a first hybrid bond (HB) structure over the first interconnect structure. The first HB structure comprises a HB link layer and a HB contact layer extending from the HB link layer to the first interconnect structure. A second IC die is over the first IC die, and comprises a second semiconductor substrate, a second HB structure, and a second interconnect structure between the second semiconductor substrate and the second HB structure. The second HB structure contacts the first HB structure. A seal-ring structure is in the first and second IC dies. Further, the seal-ring structure extends from the first semiconductor substrate to the second semiconductor substrate, and is defined in part by the HB contact layer.

Abstract: The present invention provides a method for firmly and inexpensively bonding at low temperature a polymer film to another polymer film or to a glass substrate without the use of an organic adhesive. A method for bonding a polymer film includes a step (S1) for forming a first inorganic material layer on part or all of a first polymer film; a step (S3) for forming a second inorganic material layer on part or all of a second polymer film; a step (S2) for surface-activating the surface of the first inorganic material layer by bombarding with particles having a predetermined kinetic energy; a step (S4) for surface-activating the surface of the second inorganic material layer by bombarding with particles having a predetermined kinetic energy; and a step (S5) for abutting the surface-activated surface of the first inorganic material layer against the surface-activated surface of the second inorganic material layer and bonding the first polymer film and second polymer film together.

Abstract: In a method of manufacturing an image sensor, photodiodes may be formed on a semiconductor layer in an active pixel region and a peripheral region. A structure including insulating interlayers and wiring structures may be formed on a first surface of the semiconductor layer in the active pixel region, the peripheral region and an input/output (I/O) region. The semiconductor layer and a first insulating interlayer of the insulating interlayers on the I/O region may be partially etched to form a via hole exposing a first wiring structure of the wiring structures. A first metal layer and a second metal layer may be formed on a second surface of the semiconductor layer and the via hole. The second metal layer may be patterned to form a second pad pattern on the semiconductor layer in the I/O region. An anti-reflective layer may be formed on the first metal layer and the second pad pattern.

Abstract: A method for processing a semiconductor wafer, the method including: providing a semiconductor wafer including an image sensor pixels layer including a plurality of image sensor pixels, the layer overlaying a wafer substrate; and then bonding the semiconductor wafer to a carrier wafer; and then cutting off a substantial portion of the wafer substrate, and then processing the substantial portion of the wafer substrate for reuse.

Abstract: This method includes steps a) providing the first structure and second structure, the first structure including a surface on which a silicon layer is formed; b) bombarding the silicon layer by a beam (F) of species configured to reach the surface of the first structure, and to preserve a part of the silicon layer with a surface roughness of less than 1 nm RMS on completion of the bombardment; c) bonding the first structure and second structure by direct bonding between the part of the silicon layer preserved in step b) and the second structure, steps b) and c) being executed in the same chamber subjected to a vacuum of less than 10?2 mbar.

Abstract: A structure includes a substrate having an upper surface provided with recesses and coated with a continuous barrier layer topped with a continuous copper layer filling at least the recesses. The structure is planarized by a chemical-mechanical polishing of the copper, such a polishing being selective with respect to the barrier layer so that copper remains in the recesses and is coplanar with the upper surface of the substrate. Two such structures are then direct bonded to each other (copper to copper) with opposite areas having a same topology.

Abstract: A method is disclosed that includes the steps outlined below. An epitaxial layer is formed on a first semiconductor substrate. At least one implant species is implanted between the epitaxial layer and the first semiconductor substrate to form an ion-implanted layer. The epitaxial layer is bonded to a bonding oxide layer of a second semiconductor substrate. The first semiconductor substrate is separated from the ion-implanted layer.

Abstract: A method for forming a group III-V semiconductor channel region in a transistor is provided herein. The method includes exposing a substrate including an oxide layer to a first plasma to treat the oxide layer, exposing the treated oxide layer to a second plasma to convert the oxide layer to an evaporable layer, evaporating the evaporable layer to expose a group III-V semiconductor material surface, and exposing the group III-V semiconductor material surface to an oxygen containing gas to oxidize the group III-V semiconductor material. The processes may be repeated until a recessed depth having a predetermined depth is formed. A group III-V semiconductor channel is then formed in the predetermined recessed depth. The control of the height of the group III-V semiconductor channel is improved.

Abstract: A semiconductor substrate and a base substrate are prepared; an oxide film is formed over the semiconductor substrate; the semiconductor substrate is irradiated with accelerated ions through the oxide film to form a separation layer at a predetermined depth from a surface of the semiconductor substrate; a nitrogen-containing layer is formed over the oxide film after the ion irradiation; the semiconductor substrate and the base substrate are disposed opposite to each other to bond a surface of the nitrogen-containing layer and a surface of the base substrate to each other; and the semiconductor substrate is heated to cause separation along the separation layer, thereby forming a single crystal semiconductor layer over the base substrate with the oxide film and the nitrogen-containing layer interposed therebetween.

Abstract: Provided is a device in which the metal content existing in a joining interface is controlled. A manufacturing method for the device comprises: a step in which the surfaces of a first substrate and a second substrate are activated using a FAB gun; a step in which a plurality of metals are discharged by using the FAB gun to sputter a discharged metal body comprising the plurality of metals, and the plurality of metals are affixed to the surfaces of the first substrate and the second substrate; a step in which the first substrate and the second substrate are joined at room temperature; and a step in which heating is performed at a temperature that is high in comparison to the agglomeration start temperature of the plurality of metals and of the elements that constitute the first substrate or the second substrate.

Abstract: The present disclosure relates to a method for reducing metal contamination on a surface of a substrate. The method involves plasma treatment of the surface of the substrate by ion bombardment, wherein a plasma of a supplied gas is generated, and a bombardment energy of the ions in the plasma is controlled by a radio frequency electromagnetic field. The bombardment energy of the ions is higher than a first threshold so as to tear the metal contamination from the surface of the substrate, and the bombardment energy of the ions is lower than a second threshold so as to prevent a surface quality degradation of the surface of the substrate.

Abstract: A method of fabricating a MEMS structure includes providing a substrate comprising a logic element region and a MEMS region. Next, a logic element is formed within the logic element region. A nitrogen-containing material layer is formed to cover the logic element region and the MEMS region conformally. Then, part of the nitrogen-containing material layer within the MEMS region is removed to form at least one shrinking region. Subsequently, a dielectric layer is formed to cover the logic element region and MEMS region, and the dielectric layer fills in the shrinking region. After that, the dielectric layer is etched to form at least one releasing hole, wherein the shrinking region surrounds the releasing hole. Finally, the substrate is etched to form a chamber.

Abstract: This method includes the following steps: a) providing a first structure successively including a substrate, an electronic device, a dielectric layer, and a first semiconductor layer; b) providing a second structure successively including a substrate, an active layer, a dielectric layer, and a second semiconductor layer, the active layer being designed to form an electronic device; c) bonding the first and second structures by direct bonding between the first and second semiconductor layers so as to form a bonding interface; d) removing the substrate of the second structure so as to expose the active layer; e) introducing dopants into the first and second semiconductor layers so as to form a ground plane.

Abstract: A method of producing a heterogeneous photonic integrated circuit includes integrating at least one III-V hybrid device on a source substrate having at least a top silicon layer, and transferring by transfer-printing or by flip-chip bonding the III-V hybrid device and at least part of the top silicon layer of the source substrate to a semiconductor-on-insulator or dielectric-on-insulator host substrate.

Abstract: Embodiments of the present invention provide an improved method and structure for flip chip implementation. The interconnections between the electronic circuit (e.g. silicon die) and the circuit board substrate are comprised of a metal alloy that becomes liquid at the operating temperature of the chip. This allows a softer underfill to be used, which in turn reduces stresses during operation and thermal cycling that are caused by the different coefficient of thermal expansion (CTE) of the electronic circuit chip and the circuit board substrate.

Abstract: To improve the yield in a peeling process and improve the yield in a manufacturing process of a flexible light-emitting device or the like, a peeling method includes a first step of forming a peeling layer over a first substrate, a second step of forming a layer to be peeled including a first layer in contact with the peeling layer over the peeling layer, a third step of curing a bonding layer in an overlapping manner with the peeling layer and the layer to be peeled, a fourth step of removing part of the first layer overlapping with the peeled layer and the bonding layer to form a peeling starting point, and a fifth step of separating the peeling layer and the layer to be peeled. The peeling starting point is preferably formed by laser light irradiation.

Abstract: A manufacturing method of a high-voltage metal-oxide-semiconductor (HV MOS) transistor device is provided. The manufacturing method includes the following steps. A semiconductor substrate is provided. A patterned conductive structure is formed on the semiconductor substrate. The patterned conductive structure includes a gate structure and a first sub-gate structure. The semiconductor substrate has a first region and a second region respectively disposed on two opposite sides of the gate structure. The first sub-gate structure is disposed on the first region of the semiconductor substrate. The first sub-gate structure is separated from the gate structure. A drain region is formed in the first region of the semiconductor substrate. A first contact structure is formed on the drain region and the first sub-gate structure. The drain region is electrically connected to the first sub-gate structure via the first contact structure.

Abstract: A method for assembling two substrates by molecular adhesion comprises: a first step (a) of putting first and second substrates in close contact in order to form an assembly having an assembly interface; a second step (b) of reinforcing the degree of adhesion of the assembly beyond a threshold adhesion value at which water is no longer able to diffuse along the assembly interface. The method also comprises a step (c) of anhydrous treatment of the first and second substrates in a treatment atmosphere having a dew point below ?10° C., and control of the dew point of a working atmosphere to which the first and second substrates are exposed from the anhydrous treatment step (c) until the end of the second step (b) so as to limit or prevent the appearance of bonding defects at the assembly interface.

Abstract: A curved display device includes a semiconductor chip package including a base film, a plurality of driving chips on the base film, and an input wire unit and an output wire unit connected to the driving chips, a printed circuit board (PCB) connected to the input wire unit of the semiconductor chip package, and a display panel including a display unit and a pad unit connected to the output wire unit of the semiconductor chip package, wherein the display panel, the semiconductor chip package, and the PCB are bendable in a first direction, and the driving chips of the of the semiconductor chip package are separated from each other in the first direction.

Abstract: System and method for bonding semiconductor substrates is presented. A preferred embodiment comprises forming a buffer layer over a surface of a semiconductor substrate while retaining TSVs that protrude from the buffer layer in order to prevent potential voids that might form. A protective layer is formed on another semiconductor substrate that will be bonded to the first semiconductor substrate. The two substrates are aligned and bonded together, with the buffer layer preventing any short circuit contacts to the surface of the original semiconductor substrate.

Abstract: In a method for fabricating a semiconductor, a first conductive pattern structure partially protruding upwardly from first insulating interlayer is formed in first insulating interlayer. A first bonding insulation layer pattern covering the protruding portion of first conductive pattern structure is formed on first insulating interlayer. A first adhesive pattern containing a polymer is formed on first bonding insulation layer pattern to fill a first recess formed on first bonding insulation layer pattern. A second bonding insulation layer pattern covering the protruding portion of second conductive pattern structure is formed on second insulating interlayer. A second adhesive pattern containing a polymer is formed on second bonding insulation layer pattern to fill a second recess formed on second bonding insulation layer pattern. The first and second adhesive patterns are melted. The first and second substrates are bonded with each other so that the conductive pattern structures contact each other.

Abstract: An industrial-scale apparatus, system, and method for handling precisely aligned and centered semiconductor wafer pairs for wafer-to-wafer aligning and bonding applications includes an end effector having a frame member and a floating carrier connected to the frame member with a gap formed therebetween, wherein the floating carrier has a semi-circular interior perimeter. The centered semiconductor wafer pairs are positionable within a processing system using the end effector under robotic control. The centered semiconductor wafer pairs are bonded together without the presence of the end effector in the bonding device.

Abstract: Provided is a substrate structure, including: a first substrate and a second substrate arranged correspondingly. A first surface of the first substrate faces a second surface of the second substrate, wherein the first surface is successively arranged with a conductor interconnection layer and a bonding layer, with the bonding layer connecting the first substrate and the conductor interconnection layer to the second substrate. The substrate structure and a method for manufacturing the same. The second substrate can serve as a support substrate and the first substrate as a substrate for directly manufacturing a device. However, the first substrate is formed by the growth of a crystal without the problem of thickness and stress thereof, thereby avoiding unnecessary stress and further improving the performance of the device formed in the first substrate.

Abstract: A device manufacturing method according to an embodiment includes forming a film on the side of a second surface of a substrate having a first surface and the second surface, cutting the substrate, cutting the film, and injecting particles onto at least one of a first cut portion formed by the cutting of the substrate and a second cut portion formed by the cutting of the film, to process the at least one of the first cut portion or the second cut portion.

Abstract: A method of ultrasonically bonding semiconductor elements includes the steps of: (a) aligning surfaces of a plurality of first conductive structures of a first semiconductor element to respective surfaces of a plurality of second conductive structures of a second semiconductor element, wherein the surfaces of each of the plurality of first conductive structures and the plurality of second conductive structures include aluminum; and (b) ultrasonically bonding ones of the first conductive structures to respective ones of the second conductive structures.

Abstract: Methods of manufacturing semiconductor devices and semiconductor devices with through-substrate vias (TSVs). One embodiment of a method of manufacturing a semiconductor device includes forming an opening through a dielectric structure and at least a portion of a semiconductor substrate, and forming a dielectric liner material having a first portion lining the opening and a second portion on an outer surface of the dielectric structure laterally outside of the opening. The method further includes removing the conductive material such that the second portion of the dielectric liner material is exposed, and forming a damascene conductive line in the second portion of the dielectric liner material that is electrically coupled to the TSV.

Abstract: The present invention relates to an epitaxial wafer for a light-emitting diode wherein the peak emission wavelength is 655 nm or more, and it is possible to improve reliability. The epitaxial wafer for light-emitting diodes includes a GaAs substrate (1) and a pn-junction type light-emitting unit (2) provided on the GaAs substrate (1), wherein light-emitting unit (2) is formed as a multilayer structure in which a strained light-emitting layer and a barrier layer are alternately stacked, and the composition formula of the barrier layer is (AlXGa1-X)YIn1-YP (0.3?X?0.7, 0.51?Y?0.54).

Abstract: A method of forming a thinned encapsulated chip structure, wherein the method comprises providing a separation structure arranged within an electronic chip, encapsulating part of the electronic chip by an encapsulating structure, and thinning selectively the electronic chip partially encapsulated by the encapsulating structure so that the encapsulating structure remains with a larger thickness than the thinned electronic chip, wherein the separation structure functions as a thinning stop.

Abstract: A metallic dopant element having a greater oxygen-affinity than copper is introduced into, and/or over, surface portions of copper-based metal pads and/or surfaces of a dielectric material layer embedding the copper-based metal pads in each of two substrates to be subsequently bonded. A dopant-metal silicate layer may be formed at the interface between the two substrates to contact portions of metal pads not in contact with a surface of another metal pad, thereby functioning as an oxygen barrier layer, and optionally as an adhesion material layer. A dopant metal rich portion may be formed in peripheral portions of the metal pads in contact with the dopant-metal silicate layer. A dopant-metal oxide portion may be formed in peripheral portions of the metal pads that are not in contact with a dopant-metal silicate layer.

Abstract: A method of manufacturing a three-dimensional (3D) semiconductor includes dividing each of a plurality of wafers into a plurality of multi-dies each including a plurality of dies; checking whether each of the dies has a defect; storing a result of checking whether each of the dies has a defect and information regarding each of the multi-dies; forming virtual combined structures by combining and stacking all the multi-dies in a predetermined number of layers; forming 3D semiconductor groups by calculating yields of the combined structures based on the result of checking whether each of the dies has a defect and the information regarding each of the multi-dies, selecting a combined structure having a highest yield from among the combined structures, and stacking the multi-dies to have the same structure as the selected combined structure; and forming a 3D semiconductor chip by dividing the 3D semiconductor groups in units of dies.

Abstract: A display may have a thin-film transistor layer and color filter layer. The display may have an active area and an inactive border area. Light blocking structures in the inactive area may prevent stray backlight from a backlight light guide plate from leaking out of the display. The thin-film transistor layer may have a clear substrate, a patterned black masking layer on the clear substrate, a clear planarization layer on the black masking layer, and a layer of thin-film transistor circuitry on the clear planarization layer. The black masking layer may be formed from black photoimageable polyimide. The clear planarization layer may be formed from spin-on glass. The light blocking structures may include a first layer formed from a portion of the black masking layer and a second layer such as a layer of black tape on the underside of the color filter layer.

Abstract: A method for local thinning of a top silicon layer of a SOI wafer includes the consecutive steps of: providing a SOI wafer which successively includes a bottom silicon layer, a buried oxide layer and a top silicon layer; successively forming a silicon dioxide layer and a polysilicon layer over the top silicon layer; etching the silicon dioxide layer and the polysilicon layer until a top surface of the top silicon layer is exposed, such that a pattern is formed in the silicon dioxide layer and the polysilicon layer; oxidizing the silicon dioxide layer and the polysilicon layer and concurrently oxidizing the exposed portion of the top silicon layer until the polysilicon layer has been completely converted to an oxide, thereby forming a cap oxide layer; and removing the cap oxide layer, so that a locally thinned area is formed in the top surface of the top silicon layer.

Abstract: [Problem] To provide a substrate bonding technique having a wide range of application. [Solution] A silicon thin film is formed on a bonding surface, and the interface with the substrate is surface-treated using energetic particles/metal particles.

Abstract: A method for the wet-chemical etching of a highly doped silicon layer in an etching solution is provided. The method includes using, as an etching solution so as to perform etching homogeneously, an HF-containing etching solution containing at least one oxidizing agent selected from the group of peroxodisulfates, peroxomonosulfates, and hydrogen peroxide.

Abstract: An integrated circuit chip is formed with a circuit layer, a trap rich layer and through-semiconductor-vias. The trap rich layer is formed above the circuit layer. The through-semiconductor-vias are also formed above the circuit layer. In some embodiments, the circuit layer is included in a wafer, and the trap rich layer and through-semiconductor-vias are included in another wafer. The two wafers are bonded together after formation of the trap rich layer and through-semiconductor-vias. Additionally, in some embodiments, yet another wafer may also be bonded to the wafer that includes the trap rich layer and through-semiconductor-vias. Furthermore, in some embodiments, another circuit layer may be formed in the wafer that includes the trap rich layer and through-semiconductor-vias.

Abstract: The invention relates to a method of producing lightweight structural elements which are produced as a composition construction element having at least one cover plate and one carrier element which are connected to one another. A carrier element, at which at least one apertures and/or at least one cut-out is/are formed and at least one further element, which is a cover plate, are connected to one another. A carrier element and at least one cover plate can be formed from a glass, a glass ceramic material, a ceramic material and/or silicon having an oxide surface layer which is formed at least in the bonding region of the elements to be connected to one another. The carrier element should have at least a double thickness with respect to the thickness of a cover plate.

Abstract: An interconnect device and a method of forming the interconnect device are provided. Two integrated circuits are bonded together. A first opening is formed through one of the substrates. One or more dielectric films are formed along sidewalls of the first opening. A second opening is formed extending from the first opening to pads in the integrated circuits, while using some of the pads as hard masks. The first opening and the second opening are filled with a conductive material to form a conductive plug.

Abstract: A method comprises providing a monocrystalline silicon wafer (11) having a principal surface (17) which supports a masking layer (24), for example silicon dioxide or polycrystalline silicon, having windows (25) to expose corresponding regions of the silicon wafer, forming silicon carbide seed regions (30) on the exposed regions of the wafer, for example by forming carbon and converting the carbon into silicon carbide, and growing monocrystalline silicon carbide (31) on the silicon carbide seed regions. Thus, monocrystalline silicon carbide can be formed selectively on the silicon wafer which can help to avoid wafer bow.

Abstract: In a method for solid body joining of a carrier body (10) and a cover layer (20), in particular by anodic bonding, the cover layer (20) is pressed with a pressing force against a curved carrier body surface (11), wherein the pressing force during the solid body joining is distributed by way of a pressure intermediary device (30) areally and simultaneously over the whole cover layer (20) and is directed perpendicularly to the curvature of the carrier body surface (11). A composite component comprising a carrier body (10) and a cover layer (20) is also disclosed, wherein a curved areal joining region (13) is formed between a cover layer surface (21) and a carrier body surface (11).

Abstract: Provided is a preparation method of a crystalline silicon film.

Abstract: Devices and components are provided that include a curved outcoupling component and an OLED, where the outcoupling component provides up to 100% outcoupling of light emitted by the OLED into air. The outcoupling component has an outer radius R and includes a material with a refractive index n. The OLED is in optical communication with the outcoupling component and disposed such that each emissive element of the OLED is within a distance r measured from the center of curvature of the surface at the outer radius R, such that R?r>(n?1)r.

Abstract: A method includes a) Providing a first substrate covered by a metal layer and a second substrate covered by a metal layer, b) Bringing into direct contact the metal layers so as to form a bonding interface having metal material bridges separated by cavities which are fluidly connected to each other, d) Immersing the bonding interface in an oxidizing fluid so as to form a metal oxide which fills at least in part the cavities and metal/metal oxide/metal contact areas. A structure is also provided having a first substrate, a first metal layer, a second metal layer forming a bonding layer with the first metal layer, and a second substrate, the bonding interface having: metal material bridges separated by cavities, a metal oxide partially filling the cavities, and metal/metal oxide/metal contact areas.

Abstract: A solar battery cell and related methodology are provided which enable a TAB wire to be accurately connected to an intended position, thus allowing a possible increase in manufacturing costs to be suppressed. The solar battery cell can include a substrate, a plurality of finger electrodes formed on a light receiving surface of the substrate, and a back surface electrode on a back surface of the substrate, the back surface electrode to be connected to a plurality of finger electrodes on an adjacent cell by applying a first TAB wire via a conductive adhesive, wherein the back surface electrode has omitted portions arranged to define at least one alignment marking indicative of a position where the first TAB wire is to be applied, the at least one alignment marking having a width less than a width of said first TAB wire.

Abstract: A method for producing a sensor module, in which a line part is provided in a first production step, which includes at least one receiving region for the force-fitting and/or form-fitting accommodation of a sensor element, and in a second production step for producing a housing, the line part is extrusion-coated with a plastic material in such a way that the at least one receiving region remains generally free of plastic material, and the sensor element is fixed in place in force-fitting and/or form-fitting manner in the at least one receiving region in a third production step.