Abstract: A structure for a semiconductor component is provided having a bi-layer capping coating integrated and built on supporting layer to be transferred. The bi-layer capping protects the layer to be transferred from possible degradation resulting from the attachment and removal processes of the carrier assembly used for layer transfer. A wafer-level layer transfer process using this structure is enabled to create three-dimensional integrated circuits.

Abstract: In a manufacturing method for layered chip packages, a layered substructure with at least one additional package joined thereto is used to produce a plurality of layered chip packages. The layered substructure includes a plurality of main bodies to be separated from each other later. Each main body includes: a main part having top and bottom surfaces and including a plurality of layer portions stacked on each other; and a plurality of main terminals disposed on at least one of the top and bottom surfaces of the main part. The additional package includes an additional semiconductor chip and at least one additional terminal that is electrically connected to the additional semiconductor chip and in contact with at least one of the plurality of main terminals.

Abstract: A manufacturing process of a vertical type solid state light emitting device is provided. A substrate is provided. M metal nitride buffer layer is formed on the substrate, and a breakable structure containing M metal droplet structures is formed on the buffer layer. A first type semiconductor layer, an active layer and a second type semiconductor layer are sequentially formed on the breakable structure. A second type electrode is formed on the second type semiconductor layer. The first type semiconductor layer, the active layer, the second type semiconductor layer and the second type electrode are stacked to form a light emitting stacking structure. The breakable structure is damaged to separate from the light emitting stacking structure, so that a surface of the first type semiconductor layer of the light emitting stacking structure is exposed. A first type electrode is formed on the surface of the first type semiconductor layer.

Abstract: Front facing piggyback wafer assembly. In accordance with an embodiment of the present invention, a plurality of piggyback substrates are attached to a carrier wafer. The plurality of piggyback substrates are dissimilar in composition to the carrier wafer. The plurality of piggyback substrates are processed, while attached to the carrier wafer, to produce a plurality of integrated circuit devices. The plurality of integrated circuit devices are singulated to form individual integrated circuit devices. The carrier wafer may be processed to form integrated circuit structures prior to the attaching.

Abstract: The invention relates to a method for manufacturing a multilayer structure on a first substrate made of a material having a first Young's modulus. The method includes: providing a second substrate covered with the multilayer structure, the multilayer structure having a planar surface opposite the second substrate, the second substrate being made of a material having a second Young's modulus; applying first deformations to said surface; molecularly boding the first substrate to said surface, the molecular bonding resulting in the appearance of second deformation in said surface in the absence of the first deformations, the first deformations being opposite the second deformations; and removing the second substrate, the resulting deformations in said surface being less than 5 ppm.

Abstract: Provided are methods for making a device or device component by providing a multi layer structure having a plurality of functional layers and a plurality of release layers and releasing the functional layers from the multilayer structure by separating one or more of the release layers to generate a plurality of transferable structures. The transferable structures are printed onto a device substrate or device component supported by a device substrate. The methods and systems provide means for making high-quality and low-cost photovoltaic devices, transferable semiconductor structures, (opto-)electronic devices and device components.

Abstract: The present invention related to a method for manufacturing a semiconductor, comprising steps of: providing a growing substrate; forming a semiconductor substrate on the growing substrate; forming a first structure with plural grooves and between the growing substrate and the semiconductor substrate; and changing the temperature of the growing substrate and the semiconductor substrate.

Abstract: A method for transferring a thin layer of monocrystalline silicon from a free face of a monocrystalline silicon donor substrate having a thickness greater than that of the thin layer includes implanting ions through the free face to form a buried brittle layer in the silicon, using a polymer layer, bonding the donor substrate, by the free face, to a receiver substrate, and fracturing the thin layer from the donor substrate at the buried brittle layer by thermal fracture processing, and selecting conditions of implantation such that a thickness of the thin layer is smaller than 10 micrometers, and a thickness of the polymer layer is below a critical threshold defined as a function of energy and dose of the implantation, the critical threshold being less than or equal to the lesser of 500 nanometers and the thin layer's thickness.

Abstract: A solar-powered autonomous CMOS circuit structure is fabricated with monolithically integrated photovoltaic solar cells. The structure includes a device layer including an integrated circuit and a solar cell layer. Solar cell structures in the solar cell layer can be series connected during metallization of the device layer or subsequently. The device layer and the solar cell layer are formed using a silicon-on-insulator substrate. Subsequent spalling of the silicon-on-insulator substrate through the handle substrate thereof facilitates production of a relatively thin solar cell layer that can be subjected to a selective etching process to isolate the solar cell structures.

Abstract: A donor substrate may include a base layer, a light-to-heat conversion layer disposed on the base layer, a buffer layer disposed on the light-to-heat conversion layer and including a composite layer of titanium dioxide and polytetrafluoroethylene, and a transfer layer disposed on the buffer layer. The buffer layer may be disposed between the transfer layer and the light-to-heat conversion layer. The buffer layer may be cleaned by incident light to preserve or improve its hydrophobicity. Accordingly, the buffer layer can be easily separated from the transfer layer. Advantageously, when (a portion of) the transfer layer is transferred onto a target substrate, unwanted material transfer may be prevented.

Abstract: A method for evaluating a shape change of a semiconductor wafer is provided. The method comprises acquiring unconstrained shape data of shape data of the semiconductor wafer being placed on a reference surface in a unconstrained state; acquiring constrained shape data of shape data of the semiconductor wafer being constrained along the reference surface in a constrained state; and comparing the unconstrained shape data and the constrained shape data. A method for manufacturing the semiconductor wafer utilizing a result of the evaluation of the wafer is also provided.

Abstract: A method for fabricating a semiconductor device includes forming a first semiconductor wafer, in which a circuit part and a first bonding layer are stacked, on a first semiconductor substrate, forming a second semiconductor wafer, which includes structures and an insulating layer for gap-filling between the structures, on a second semiconductor substrate, the structures including a pillar and bit lines stacked therein, bonding the first semiconductor wafer with the second semiconductor wafer so that the first bonding layer faces the insulating layer, and separating the second semiconductor substrate from the bonded second semiconductor wafer.

Abstract: A method for forming a radio frequency device is provided. The method may include: providing a semiconductor-on-insulator layer, which comprises a back substrate, a buried oxide layer and a top semiconductor layer, where a plurality of transistors and an interlayer dielectric layer covering the plurality of transistors are formed on a surface of the top semiconductor layer; providing a temporary supporting layer having a smooth surface, and adhering a surface of the interlayer dielectric layer to the temporary supporting layer; removing the back substrate to expose the buried oxide; providing a high resistivity substrate, and adhering the high resistivity substrate to the buried oxide layer; and removing the temporary supporting layer to expose the surface of the interlayer dielectric layer after the high resistivity substrate and the buried oxide layer is adhered. Signal loss of the radio frequency devices may be reduced, and signal linearity is improved.

Abstract: A semiconductor device can include a first substrate and conductive patterns on the first substrate, where the conductive patterns are disposed in stacks vertically extending from the substrate. An active pillar can be on the first substrate vertically extend from the first substrate throughthe conductive patterns to provide vertical string transistors on the first substrate. A second substrate can be on the conductive patterns and the active pillar opposite the first substrate. A peripheral circuit transistor can be on the second substrate opposite the first substrate, where the peripheral circuit transistor can be adjacent to and overlap an uppermost pattern of the conductive patterns.

Abstract: A method for preparing a composite substrate for GaN growth includes: growing a GaN monocrystal epitaxial layer on a sapphire substrate, bonding the GaN epitaxial layer onto a temporary substrate, lifting off the sapphire substrate, bonding the GaN epitaxial layer on the temporary substrate with a thermally and electrically conducting substrate, shedding the temporary substrate, and obtaining the composite substrate in which the GaN layer having a surface of gallium polarity is bonded to the conducting substrate. If the GaN layer on the sapphire substrate is directly bonded to the conducting substrate, after the sapphire substrate is lifted off, a composite substrate in which a GaN epitaxial layer having a surface of nitrogen polarity is bonded to the conducting substrate. The disclosed composite substrates have homoepitaxy and improved crystal quality; they can be used for forming LED and other devices at greatly reduces costs.

Abstract: The invention provides a substrate detergent composition used for cleaning a surface of a substrate, comprising: (A) A quaternary ammonium salt: 0.1 to 2.0% by mass; (B) Water: 0.1 to 0.4% by mass; and (C) An organic solvent: 94.0 to 99.8% by mass. There can be provided a substrate detergent composition used for cleaning a surface of a substrate contaminated with a silicone component whose water contact angle is 100° or more.

Abstract: In a method for manufacturing a diode, a semiconductor crystal wafer is used to produce a p-n or n-p junction, which extends in planar fashion across the top side of a semiconductor crystal wafer. Separation edges form perpendicularly to the top side of the semiconductor crystal wafer, which edges extend across the p-n or n-p junction. The separation of the semiconductor crystal wafer is achieved in that, starting from a disturbance, a fissure is propagated by local heating and local cooling of the semiconductor crystal wafer. The separation fissure thus formed extends along crystal planes of the semiconductor crystal, which avoids the formation of defects in the area of the p-n or n-p junction.

Abstract: A technique for peeling an element manufactured through a process at relatively low temperature (lower than 500° C.) from a substrate and transferring the element to a flexible substrate (typically, a plastic film). With the use of an existing manufacturing device for a large glass substrate, a molybdenum film (Mo film) is formed over a glass substrate, an oxide film is formed over the molybdenum film, and an element is formed over the oxide film through a process at relatively low temperature (lower than 500° C.). Then, the element is peeled from the glass substrate and transferred to a flexible substrate.

Abstract: Provided is a semiconductor wafer including a base wafer, a first insulating layer, and a semiconductor layer. Here, the base wafer, the first insulating layer and the semiconductor layer are arranged in an order of the base wafer, the first insulating layer and the semiconductor layer, the first insulating layer is made of an amorphous metal oxide or an amorphous metal nitride, the semiconductor layer includes a first crystal layer and a second crystal layer, the first crystal layer and the second crystal layer are arranged in an order of the first crystal layer and the second crystal layer in such a manner that the first crystal layer is positioned closer to the base wafer, and the electron affinity Ea1 of the first crystal layer is larger than the electron affinity Ea2 of the second crystal layer.

Abstract: The invention relates to a process for manufacturing a semiconductor substrate, characterized in that it comprises providing at least one donor semiconductor substrate comprising at least one useful silicon layer; inspecting the donor substrate via an inspecting machine in order to detect whether the useful layer contains emerging cavities of a size larger than or equal to a critical size, said critical size being strictly smaller than 44 nm; and manufacturing a semiconductor substrate comprising at least part of the useful layer of the donor substrate if, considering cavities of a size larger than or equal to the critical size, the density or number of cavities in the useful layer of the donor substrate is lower than or equal to a critical defect density or number.

Abstract: A semiconductor light-emitting device comprises a light-emitting epitaxial structure, a first electrode structure, a light reflective layer and an resistivity-enhancing structure. The light-emitting epitaxial structure has a first surface and a second surface opposite to the first surface. The first electrode structure is electrically connected to the first surface. The light reflective layer is disposed adjacent to the second surface. The resistivity-enhancing structure is disposed adjacent to the light reflective layer and away from the second surface corresponding to a position of the first electrode structure.

Abstract: Presented is an integrated circuit packaged at the wafer level wafer (also referred to as a wafer level chip scale package, WLCSP), and a method of manufacturing the same. The WLCSP comprises a die having an electrically conductive redistribution layer, RDL, formed above the upper surface of the die, the RDL defining a signal routing circuit. The method comprises the steps of: depositing the electrically conductive RDL so as to form an electrically conductive ring surrounding the signal routing circuit; and coating the side and lower surfaces of the die with an electrically conductive shielding material.

Abstract: A manufacturing method of an SOI substrate which possesses a base substrate having low heat resistance and a very thin semiconductor layer having high planarity is demonstrated. The method includes: implanting hydrogen ions into a semiconductor substrate to form an ion implantation layer; bonding the semiconductor substrate and a base substrate such as a glass substrate, placing a bonding layer therebetween; heating the substrates bonded to each other to separate the semiconductor substrate from the base substrate, leaving a thin semiconductor layer over the base substrate; irradiating the surface of the thin semiconductor layer with laser light to improve the planarity and recover the crystallinity of the thin semiconductor layer; and thinning the thin semiconductor layer. This method allows the formation of an SOI substrate which has a single-crystalline semiconductor layer with a thickness of 100 nm or less over a base substrate.

Abstract: The disclosure provides a method for fabricating a semiconductor layer having a textured surface, including: (a) providing a textured substrate; (b) forming at least one semiconductor layer on the textured substrate; (c) forming a metal layer on the semiconductor layer; and (d) conducting a thermal process or a low temperature process to the textured substrate, the semiconductor layer and the metal layer, wherein the semiconductor layer is separated from the textured substrate by the thermal process to obtain the semiconductor layer having the metal layer and a textured surface.

Abstract: Methods for manufacturing semiconductor-on-insulator (SOI) integrated circuits are disclosed. An SOI wafer is provided having a first surface and a second surface. The substrate of the SOI wafer forms the second surface. A transistor is formed in the semiconductor layer of the SOI wafer. A handle wafer is bonded to the first surface of the SOI wafer. The substrate layer is then removed to expose a back surface of the buried insulator of the SOI wafer. Conductive material is deposited on the SOI wafer that covers the back surface of the buried insulator. The conductive material is patterned to form a second gate electrode for the transistor on the back surface of the insulator.

Abstract: Provided is a method of transferring semiconductor elements formed on a non-flexible substrate to a flexible substrate. Also, provided is a method of manufacturing a flexible semiconductor device based on the method of transferring semiconductor elements. A semiconductor element grown or formed on the substrate may be efficiently transferred to the resin layer while maintaining an arrangement of the semiconductor elements. Furthermore, the resin layer acts as a flexible substrate supporting the vertical semiconductor elements.

Abstract: A strained Ge-on-insulator structure is provided, comprising: a silicon substrate, in which an oxide insulating layer is formed on a surface of the silicon substrate; a Ge layer formed on the oxide insulating layer, in which a first passivation layer is formed between the Ge layer and the oxide insulating layer; a gate stack formed on the Ge layer, a channel region formed below the gate stack, and a source and a drain formed on sides of the channel region; and a SiN stress cap layer covering the gate stack to produce a strain in the channel region. Further, a method for forming the strained Ge-on-insulator structure is also provided.

Abstract: The present invention provides a method for separating an epitaxial layer from a growth substrate, comprising growing an epitaxial layer including a plurality of layers on a growth substrate; etching an edge of at least one layer in the epitaxial layer to form a notch; forming a bonding layer on the epitaxial layer, contacting a bonding substrate onto the bonding layer, and then heating the bonding layer to a bonding temperature for joining the epitaxial layer and the bonding substrate; and cooling the bonding layer after the heating of the boding layer, so that the epitaxial layer and the bonding substrate are joined by the bonding layer, and the epitaxial layer is separated from the growth substrate, wherein the separating the epitaxial layer from the growth substrate starts with separation from the at least one layer where the notch is formed.

Abstract: An assembly including a liquid thermal interface material for surface tension adhesion and thermal control used during electrical/thermal test of a 3D wafer and methods of use. The method includes temporarily attaching a thinned wafer to a carrier wafer by applying a non-adhesive material therebetween and pressing the thinned wafer and the blank silicon-based carrier wafer together.

Abstract: A disclosed method of manufacturing a semiconductor device includes forming a groove on a first surface of a semiconductor wafer along an outer periphery of the semiconductor wafer, forming a semiconductor device on the first surface, forming an adhesive layer on the first surface to cover the semiconductor device, bonding a support substrate to the first surface by the adhesive layer, grinding after the adhering of the support substrate a second surface of the semiconductor wafer opposite to the first surface, and dicing after the grinding the semiconductor wafer into individual semiconductor chips.

Abstract: An integrated silicon and III-N semiconductor device may be formed by growing III-N semiconductor material on a first silicon substrate having a first orientation. A second silicon substrate with a second, different, orientation has a release layer between a silicon device film and a carrier wafer. The silicon device film is attached to the III-N semiconductor material while the silicon device film is connected to the carrier wafer through the release layer. The carrier wafer is subsequently removed from the silicon device film. A first plurality of components is formed in and/or on the silicon device film. A second plurality of components is formed in and/or on III-N semiconductor material in the exposed region. In an alternate process, a dielectric interlayer may be disposed between the silicon device film and the III-N semiconductor material in the integrated silicon and III-N semiconductor device.

Abstract: An SOI substrate having an SOI layer that can be used in practical applications even when a substrate with low upper temperature limit, such as a glass substrate, is used, is provided. A semiconductor device using such an SOI substrate, is provided. In bonding a single-crystal semiconductor layer to a substrate having an insulating surface or an insulating substrate, a silicon oxide film formed using organic silane as a material on one or both surfaces that are to form a bond is used. According to the present invention, a substrate with an upper temperature limit of 700° C. or lower, such as a glass substrate, can be used, and an SOI layer that is strongly bonded to the substrate can be obtained. In other words, a single-crystal semiconductor layer can be formed over a large-area substrate that is longer than one meter on each side.

Abstract: A method for manufacturing a SOI wafer, including a step of performing a thickness reducing adjustment to a SOI layer of the SOI wafer by carrying out a sacrificial oxidation to the SOI wafer for effecting thermal oxidation to a surface of the SOI layer and removing a formed thermal oxide film, wherein, when the thermal oxidation in the sacrificial oxidation treatment is carried out with the use of a batch processing heat treatment furnace during the rising of a temperature and/or the falling of a temperature, a substantially concentric oxide film thickness distribution is formed on the surface of the SOI layer. The result is a method for manufacturing a SOI wafer that enables manufacturing a SOI wafer that has improved radial film thickness distribution with good productivity by performing the sacrificial oxidation treatment for forming a substantially concentric oxide film and removing the formed thermal oxide film.

Abstract: Methods of forming integrated circuit devices include forming a sacrificial layer on a handling substrate and forming a semiconductor active layer on the sacrificial layer. A step is performed to selectively etch through the semiconductor active layer and the sacrificial layer in sequence to define an semiconductor-on-insulator (SOI) substrate, which includes a first portion of the semiconductor active layer. A multi-layer electrical interconnect network may be formed on the SOI substrate. This multi-layer electrical interconnect network may be encapsulated by an inorganic capping layer that contacts an upper surface of the first portion of the semiconductor active layer. A step can be performed to selectively etch through the capping layer and the first portion of the semiconductor active layer to thereby expose the sacrificial layer.

Abstract: To suppress desorption of hydrogen ions with which a single crystal semiconductor substrate is irradiated. A method for manufacturing an SOI substrate includes the following steps: irradiating a semiconductor substrate with carbon ions; irradiating the semiconductor substrate with a hydrogen ion after the irradiation with the carbon ion so as to form an embrittled region in the semiconductor substrate; disposing a surface of the semiconductor substrate and a surface of a base substrate to face each other and to be in contact with each other so that the semiconductor substrate and the base substrate are bonded; and heating the semiconductor substrate and the base substrate which are bonded to each other and separating the semiconductor substrate along the embrittled region so that a semiconductor layer is formed over the base substrate.

Abstract: The present invention provides a method for preparing a GOI chip structure, where, in the method, first, a SiGe on insulator (SGOI) chip structure is made by using a SMART CUT technology, and then, germanium condensation technology is performed on the SGOI chip structure, so as to obtain a GOI chip structure. Because the SGOI made by the Smart-Cut technology basically has no misfit dislocation in an SGOI/BOX interface, the threading dislocation density of the GOI is finally reduced. A technique of the present invention is simple, the high-quality GOI chip structure can be implemented, and the germanium condensation technology is greatly improved. An ion implantation technology and an annealing technology are quite mature techniques in the current semiconductor industry, so that such a preparation method greatly improves the possibility of wide use of the germanium concentration technology in the semiconductor industry.

Abstract: A graphene device manufacturing apparatus includes an electrode, a graphene structure including a metal catalyst layer formed on a substrate, a protection layer, and a graphene layer between the protection layer and the metal catalyst layer, a power unit configured to apply a voltage between the electrode and the metal catalyst layer, and an electrolyte in which the graphene structure is at least partially submerged.

Abstract: Semiconductor-on-oxide structures and related methods of forming such structures are disclosed. In one case, a method includes: forming a first dielectric layer over a substrate; forming a first conductive layer over the first dielectric layer, the first conductive layer including one of a metal or a silicide; forming a second dielectric layer over the first conductive layer; bonding a donor wafer to the second dielectric layer, the donor wafer including a donor dielectric and a semiconductor layer; cleaving the donor wafer to remove a portion of the donor semiconductor layer; forming at least one semiconductor isolation region from an unremoved portion of the donor semiconductor layer; and forming a contact to the first conductive layer through donor dielectric and the second dielectric layer.

Abstract: An embodiment is a method for bonding. The method comprises bonding a handle substrate to a capping substrate; thinning the capping substrate; etching the capping substrate; and after the thinning and the etching the capping substrate, bonding the capping substrate to an active substrate. The handle substrate has an opening therethrough. The method also comprises removing the handle substrate from the capping substrate. The removing comprises providing an etchant through the opening to separate the handle substrate from the capping substrate. Other embodiments further include forming a bonding material on a surface of at least one of the handle substrate and the capping substrate such that the capping substrate is bonded to the handle substrate by the bonding material. The bonding material may be removed by using a dry etching to remove the handle substrate from the capping substrate.

Abstract: A method for manufacturing a semiconductor device with a treated member, includes: subjecting an adhesive support having a substrate and an adhesive layer capable of increasing or decreasing in adhesiveness upon irradiation with an actinic ray, radiation or heat to irradiation of the adhesive layer with an actinic ray, radiation or heat, adhering a first surface of a to-be-treated member to the adhesive layer of the adhesive support, applying a mechanical or chemical treatment to a second surface different from the first surface of the to-be-treated member to obtain a treated member, and detaching a first surface of the treated member from the adhesive layer of the adhesive support, wherein the irradiation of the adhesive layer with an actinic ray, radiation or heat is conducted so that adhesiveness decreases toward an outer surface from an inner surface on the substrate side of the adhesive layer.

Abstract: According to the present invention, there is provided a method for manufacturing an SOI wafer having the step of performing a first sacrificial oxidation treatment on the aforementioned bonded SOI wafer in which the delamination has been performed after a first RTA treatment has been performed thereon and then performing a second sacrificial oxidation treatment thereon after a second RTA treatment has been performed thereon, wherein the first and second RTA treatments are performed under a hydrogen gas containing atmosphere and at a temperature of 1100° C. or more, wherein after a thermal oxide film has been formed on the aforementioned SOI layer front surface by performing only thermal oxidation by a batch type heat treating furnace at a temperature of 900° C. or more and 1000° C. or less in the first and second sacrificial oxidation treatments, a treatment for removing the thermal oxide film is performed.

Abstract: A method of fabricating a memory cell comprises forming a plurality of doped semiconductor layers on a carrier substrate. The method further comprises forming a plurality of digit lines separated by an insulating material. The digit lines are arrayed over the doped semiconductor layers. The method further comprises etching a plurality of trenches into the doped semiconductor layers. The method further comprises depositing an insulating material into the plurality of trenches to form a plurality of electrically isolated transistor pillars. The method further comprises bonding at least a portion of the structure formed on the carrier substrate to a host substrate. The method further comprises separating the carrier substrate from the host substrate.

Abstract: A thin wafer handling structure includes a semiconductor wafer, a release layer that can be released by applying energy, an adhesive layer that can be removed by a solvent, and a carrier, where the release layer is applied on the carrier by coating or laminating, the adhesive layer is applied on the semiconductor wafer by coating or laminating, and the semiconductor wafer and the carrier is bonded together with the release layer and the adhesive layer in between. The method includes applying a release layer on a carrier, applying an adhesive layer on a semiconductor wafer, bonding the carrier and the semiconductor wafer, releasing the carrier by applying energy on the release layer, e.g. UV or laser, and cleaning the semiconductor's surface by a solvent to remove any residue of the adhesive layer.

Abstract: A method for producing a hybrid substrate, including a support substrate, a continuous buried insulator layer and, on this continuous layer, a hybrid layer including alternating zones of a first material and at least one second material, wherein these two materials are different by their nature and/or their crystallographic characteristics. The method forms a hybrid layer, including alternating zones of first and second materials, on a homogeneous substrate, assembles this hybrid layer, the continuous insulator layer and the support substrate, and eliminates a part at least of the homogeneous substrate, before or after the assembling.

Abstract: A method of producing a silicon-on-insulator article, the method including: forming a first aluminium nitride layer thermally coupled to a first silicon substrate; forming a second aluminium nitride layer thermally coupled to a second substrate, the second substrate including at least a surface layer of silicon; bonding the first and second aluminium nitride layers of the first and second substrates together so that the first and second aluminium nitride layers are disposed between the first and second substrates; and removing most of the second substrate to leave a layer of silicon that is electrically insulated from but thermally coupled to the first silicon substrate by the first and second aluminium nitride layers.

Abstract: A vertical GaN-based blue LED has an n-type GaN layer that was grown directly on Low Resistance Layer (LRL) that in turn was grown over a silicon substrate. In one example, the LRL is a low sheet resistance GaN/AlGaN superlattice having periods that are less than 300 nm thick. Growing the n-type GaN layer on the superlattice reduces lattice defect density in the n-type layer. After the epitaxial layers of the LED are formed, a conductive carrier is wafer bonded to the structure. The silicon substrate is then removed. Electrodes are added and the structure is singulated to form finished LED devices. In some examples, some or all of the LRL remains in the completed LED device such that the LRL also serves a current spreading function. In other examples, the LRL is entirely removed so that no portion of the LRL is present in the completed LED device.

Abstract: A method of forming a semiconductor device that includes providing a logic device on a semiconductor on insulating layer of a transfer substrate. The transfer substrate may further include a dielectric layer and a first handle substrate. A second handle substrate may be contacted to the semiconductor on insulating layer of the transfer substrate that includes logic device. The first handle substrate may be removed to expose the dielectric layer. A memory device can then be formed on the dielectric layer. Interconnect wiring can then be formed connecting the logic device with the memory device.

Abstract: A method for connecting a semiconductor chip to a metal layer of a carrier substrate is disclosed. A semiconductor chip is provided which has a first side, a second side opposite the first side, a glass substrate bonded to the second side of the semiconductor chip and including at least one opening leaving an area of the second side of the semiconductor chip uncovered by the glass substrate, and a metallization region arranged in the opening of the glass substrate and electrically contacting the second side of the semiconductor chip. The semiconductor chip with the bonded glass substrate is brought onto a metal layer of a carrier substrate. A firm mechanical and electrical connection is formed between the metal layer of the carrier substrate and the metallization region.

Abstract: A method for fabricating a solar cell commences by bonding a first metal-coated substrate to a second metal-coated substrate to provide a bonded substrate. The bonded substrate is then coated with a first precursor solution to provide a coated bonded substrate. Finally, the procedure de-bonds the coated bonded substrate to provide a first solar cell device and a second solar cell device. A system for fabricating the solar cell comprises a first precursor solution deposition system containing a first precursor solution for deposition on a substrate, a first heating element for heating the substrate after deposition of the first precursor solution, a second precursor solution deposition system containing a second precursor solution for deposition on the substrate, and a second heating element for heating the substrate after deposition of the second precursor solution.

Abstract: Provided is a flexible device with fewer defects caused by a crack or a flexible device having high productivity. A semiconductor device including: a display portion over a flexible substrate, including a transistor and a display element; a semiconductor layer surrounding the display portion; and an insulating layer over the transistor and the semiconductor layer. When seen in a direction perpendicular to a surface of the flexible substrate, an end portion of the substrate is substantially aligned with an end portion of the semiconductor layer, and an end portion of the insulating layer is positioned over the semiconductor layer.